1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/time.h>
24 #include <linux/string.h>
25 #include <linux/pm_runtime.h>
26
27 #include <sound/core.h>
28 #include <sound/initval.h>
29
30 #include <sound/hda_codec.h>
31 #include "hda_controller.h"
32
33 /* Defines for Nvidia Tegra HDA support */
34 #define HDA_BAR0 0x8000
35
36 #define HDA_CFG_CMD 0x1004
37 #define HDA_CFG_BAR0 0x1010
38
39 #define HDA_ENABLE_IO_SPACE (1 << 0)
40 #define HDA_ENABLE_MEM_SPACE (1 << 1)
41 #define HDA_ENABLE_BUS_MASTER (1 << 2)
42 #define HDA_ENABLE_SERR (1 << 8)
43 #define HDA_DISABLE_INTR (1 << 10)
44 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
45 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
46
47 /* IPFS */
48 #define HDA_IPFS_CONFIG 0x180
49 #define HDA_IPFS_EN_FPCI 0x1
50
51 #define HDA_IPFS_FPCI_BAR0 0x80
52 #define HDA_FPCI_BAR0_START 0x40
53
54 #define HDA_IPFS_INTR_MASK 0x188
55 #define HDA_IPFS_EN_INTR (1 << 16)
56
57 /* FPCI */
58 #define FPCI_DBG_CFG_2 0x10F4
59 #define FPCI_GCAP_NSDO_SHIFT 18
60 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
61
62 /* max number of SDs */
63 #define NUM_CAPTURE_SD 1
64 #define NUM_PLAYBACK_SD 1
65
66 /*
67 * Tegra194 does not reflect correct number of SDO lines. Below macro
68 * is used to update the GCAP register to workaround the issue.
69 */
70 #define TEGRA194_NUM_SDO_LINES 4
71
72 struct hda_tegra_soc {
73 bool has_hda2codec_2x_reset;
74 bool has_hda2hdmi;
75 bool has_hda2codec_2x;
76 bool input_stream;
77 bool always_on;
78 bool requires_init;
79 };
80
81 struct hda_tegra {
82 struct azx chip;
83 struct device *dev;
84 struct reset_control_bulk_data resets[3];
85 struct clk_bulk_data clocks[3];
86 unsigned int nresets;
87 unsigned int nclocks;
88 void __iomem *regs;
89 struct work_struct probe_work;
90 const struct hda_tegra_soc *soc;
91 };
92
93 #ifdef CONFIG_PM
94 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
95 module_param(power_save, bint, 0644);
96 MODULE_PARM_DESC(power_save,
97 "Automatic power-saving timeout (in seconds, 0 = disable).");
98 #else
99 #define power_save 0
100 #endif
101
102 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
103
hda_tegra_init(struct hda_tegra * hda)104 static void hda_tegra_init(struct hda_tegra *hda)
105 {
106 u32 v;
107
108 /* Enable PCI access */
109 v = readl(hda->regs + HDA_IPFS_CONFIG);
110 v |= HDA_IPFS_EN_FPCI;
111 writel(v, hda->regs + HDA_IPFS_CONFIG);
112
113 /* Enable MEM/IO space and bus master */
114 v = readl(hda->regs + HDA_CFG_CMD);
115 v &= ~HDA_DISABLE_INTR;
116 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
117 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
118 writel(v, hda->regs + HDA_CFG_CMD);
119
120 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
121 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
122 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
123
124 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
125 v |= HDA_IPFS_EN_INTR;
126 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
127 }
128
129 /*
130 * power management
131 */
hda_tegra_suspend(struct device * dev)132 static int __maybe_unused hda_tegra_suspend(struct device *dev)
133 {
134 struct snd_card *card = dev_get_drvdata(dev);
135 int rc;
136
137 rc = pm_runtime_force_suspend(dev);
138 if (rc < 0)
139 return rc;
140 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
141
142 return 0;
143 }
144
hda_tegra_resume(struct device * dev)145 static int __maybe_unused hda_tegra_resume(struct device *dev)
146 {
147 struct snd_card *card = dev_get_drvdata(dev);
148 int rc;
149
150 rc = pm_runtime_force_resume(dev);
151 if (rc < 0)
152 return rc;
153 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
154
155 return 0;
156 }
157
hda_tegra_runtime_suspend(struct device * dev)158 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
159 {
160 struct snd_card *card = dev_get_drvdata(dev);
161 struct azx *chip = card->private_data;
162 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
163
164 if (chip && chip->running) {
165 /* enable controller wake up event */
166 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
167 STATESTS_INT_MASK);
168
169 azx_stop_chip(chip);
170 azx_enter_link_reset(chip);
171 }
172 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
173
174 return 0;
175 }
176
hda_tegra_runtime_resume(struct device * dev)177 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
178 {
179 struct snd_card *card = dev_get_drvdata(dev);
180 struct azx *chip = card->private_data;
181 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
182 int rc;
183
184 if (!chip->running) {
185 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
186 if (rc)
187 return rc;
188 }
189
190 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
191 if (rc != 0)
192 return rc;
193 if (chip->running) {
194 if (hda->soc->requires_init)
195 hda_tegra_init(hda);
196
197 azx_init_chip(chip, 1);
198 /* disable controller wake up event*/
199 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
200 ~STATESTS_INT_MASK);
201 } else {
202 usleep_range(10, 100);
203
204 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
205 if (rc)
206 return rc;
207 }
208
209 return 0;
210 }
211
212 static const struct dev_pm_ops hda_tegra_pm = {
213 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
214 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
215 hda_tegra_runtime_resume,
216 NULL)
217 };
218
hda_tegra_dev_disconnect(struct snd_device * device)219 static int hda_tegra_dev_disconnect(struct snd_device *device)
220 {
221 struct azx *chip = device->device_data;
222
223 chip->bus.shutdown = 1;
224 return 0;
225 }
226
227 /*
228 * destructor
229 */
hda_tegra_dev_free(struct snd_device * device)230 static int hda_tegra_dev_free(struct snd_device *device)
231 {
232 struct azx *chip = device->device_data;
233 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
234
235 cancel_work_sync(&hda->probe_work);
236 if (azx_bus(chip)->chip_init) {
237 azx_stop_all_streams(chip);
238 azx_stop_chip(chip);
239 }
240
241 azx_free_stream_pages(chip);
242 azx_free_streams(chip);
243 snd_hdac_bus_exit(azx_bus(chip));
244
245 return 0;
246 }
247
hda_tegra_init_chip(struct azx * chip,struct platform_device * pdev)248 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
249 {
250 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
251 struct hdac_bus *bus = azx_bus(chip);
252 struct resource *res;
253
254 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
255 if (IS_ERR(hda->regs))
256 return PTR_ERR(hda->regs);
257
258 bus->remap_addr = hda->regs + HDA_BAR0;
259 bus->addr = res->start + HDA_BAR0;
260
261 if (hda->soc->requires_init)
262 hda_tegra_init(hda);
263
264 return 0;
265 }
266
hda_tegra_first_init(struct azx * chip,struct platform_device * pdev)267 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
268 {
269 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
270 struct hdac_bus *bus = azx_bus(chip);
271 struct snd_card *card = chip->card;
272 int err;
273 unsigned short gcap;
274 int irq_id = platform_get_irq(pdev, 0);
275 const char *sname, *drv_name = "tegra-hda";
276 struct device_node *np = pdev->dev.of_node;
277
278 if (irq_id < 0)
279 return irq_id;
280
281 err = hda_tegra_init_chip(chip, pdev);
282 if (err)
283 return err;
284
285 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
286 IRQF_SHARED, KBUILD_MODNAME, chip);
287 if (err) {
288 dev_err(chip->card->dev,
289 "unable to request IRQ %d, disabling device\n",
290 irq_id);
291 return err;
292 }
293 bus->irq = irq_id;
294 bus->dma_stop_delay = 100;
295 card->sync_irq = bus->irq;
296
297 /*
298 * Tegra194 has 4 SDO lines and the STRIPE can be used to
299 * indicate how many of the SDO lines the stream should be
300 * striped. But GCAP register does not reflect the true
301 * capability of HW. Below workaround helps to fix this.
302 *
303 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
304 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
305 */
306 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
307 u32 val;
308
309 dev_info(card->dev, "Override SDO lines to %u\n",
310 TEGRA194_NUM_SDO_LINES);
311
312 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
313 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
314 writel(val, hda->regs + FPCI_DBG_CFG_2);
315 }
316
317 gcap = azx_readw(chip, GCAP);
318 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
319
320 chip->align_buffer_size = 1;
321
322 /* read number of streams from GCAP register instead of using
323 * hardcoded value
324 */
325 chip->capture_streams = (gcap >> 8) & 0x0f;
326
327 /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
328 * but the HW output stream descriptor programming should start with
329 * offset 0x20*4 from base stream descriptor address. This will be a
330 * problem while calculating the offset for output stream descriptor
331 * which will be considering input stream also. So here output stream
332 * starts with offset 0 which is wrong as HW register for output stream
333 * offset starts with 4.
334 */
335 if (!hda->soc->input_stream)
336 chip->capture_streams = 4;
337
338 chip->playback_streams = (gcap >> 12) & 0x0f;
339 if (!chip->playback_streams && !chip->capture_streams) {
340 /* gcap didn't give any info, switching to old method */
341 chip->playback_streams = NUM_PLAYBACK_SD;
342 chip->capture_streams = NUM_CAPTURE_SD;
343 }
344 chip->capture_index_offset = 0;
345 chip->playback_index_offset = chip->capture_streams;
346 chip->num_streams = chip->playback_streams + chip->capture_streams;
347
348 /* initialize streams */
349 err = azx_init_streams(chip);
350 if (err < 0) {
351 dev_err(card->dev, "failed to initialize streams: %d\n", err);
352 return err;
353 }
354
355 err = azx_alloc_stream_pages(chip);
356 if (err < 0) {
357 dev_err(card->dev, "failed to allocate stream pages: %d\n",
358 err);
359 return err;
360 }
361
362 /* initialize chip */
363 azx_init_chip(chip, 1);
364
365 /*
366 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
367 * 4 SDO lines due to legacy design limitation. Following
368 * is, from HD Audio Specification (Revision 1.0a), used to
369 * control striping of the stream across multiple SDO lines
370 * for sample rates <= 48K.
371 *
372 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
373 *
374 * Due to legacy design issue it is recommended that above
375 * ratio must be greater than 8. Since number of SDO lines is
376 * in powers of 2, next available ratio is 16 which can be
377 * used as a limiting factor here.
378 */
379 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
380 chip->bus.core.sdo_limit = 16;
381
382 /* codec detection */
383 if (!bus->codec_mask) {
384 dev_err(card->dev, "no codecs found!\n");
385 return -ENODEV;
386 }
387
388 /* driver name */
389 strscpy(card->driver, drv_name, sizeof(card->driver));
390 /* shortname for card */
391 sname = of_get_property(np, "nvidia,model", NULL);
392 if (!sname)
393 sname = drv_name;
394 if (strlen(sname) > sizeof(card->shortname))
395 dev_info(card->dev, "truncating shortname for card\n");
396 strscpy(card->shortname, sname, sizeof(card->shortname));
397
398 /* longname for card */
399 snprintf(card->longname, sizeof(card->longname),
400 "%s at 0x%lx irq %i",
401 card->shortname, bus->addr, bus->irq);
402
403 return 0;
404 }
405
406 /*
407 * constructor
408 */
409
410 static void hda_tegra_probe_work(struct work_struct *work);
411
hda_tegra_create(struct snd_card * card,unsigned int driver_caps,struct hda_tegra * hda)412 static int hda_tegra_create(struct snd_card *card,
413 unsigned int driver_caps,
414 struct hda_tegra *hda)
415 {
416 static const struct snd_device_ops ops = {
417 .dev_disconnect = hda_tegra_dev_disconnect,
418 .dev_free = hda_tegra_dev_free,
419 };
420 struct azx *chip;
421 int err;
422
423 chip = &hda->chip;
424
425 mutex_init(&chip->open_mutex);
426 chip->card = card;
427 chip->ops = &hda_tegra_ops;
428 chip->driver_caps = driver_caps;
429 chip->driver_type = driver_caps & 0xff;
430 chip->dev_index = 0;
431 INIT_LIST_HEAD(&chip->pcm_list);
432
433 chip->codec_probe_mask = -1;
434
435 chip->single_cmd = false;
436 chip->snoop = true;
437
438 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
439
440 err = azx_bus_init(chip, NULL);
441 if (err < 0)
442 return err;
443
444 chip->bus.core.sync_write = 0;
445 chip->bus.core.needs_damn_long_delay = 1;
446 chip->bus.core.aligned_mmio = 1;
447
448 /*
449 * HDA power domain and clocks are always on for Tegra264 and
450 * the jack detection logic would work always, so no need of
451 * jack polling mechanism running.
452 */
453 if (!hda->soc->always_on) {
454 chip->jackpoll_interval = msecs_to_jiffies(5000);
455 chip->bus.jackpoll_in_suspend = 1;
456 }
457
458 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
459 if (err < 0) {
460 dev_err(card->dev, "Error creating device\n");
461 return err;
462 }
463
464 return 0;
465 }
466
467 static const struct hda_tegra_soc tegra30_data = {
468 .has_hda2codec_2x_reset = true,
469 .has_hda2hdmi = true,
470 .has_hda2codec_2x = true,
471 .input_stream = true,
472 .always_on = false,
473 .requires_init = true,
474 };
475
476 static const struct hda_tegra_soc tegra194_data = {
477 .has_hda2codec_2x_reset = false,
478 .has_hda2hdmi = true,
479 .has_hda2codec_2x = true,
480 .input_stream = true,
481 .always_on = false,
482 .requires_init = true,
483 };
484
485 static const struct hda_tegra_soc tegra234_data = {
486 .has_hda2codec_2x_reset = true,
487 .has_hda2hdmi = false,
488 .has_hda2codec_2x = true,
489 .input_stream = false,
490 .always_on = false,
491 .requires_init = true,
492 };
493
494 static const struct hda_tegra_soc tegra264_data = {
495 .has_hda2codec_2x_reset = true,
496 .has_hda2hdmi = false,
497 .has_hda2codec_2x = false,
498 .input_stream = false,
499 .always_on = true,
500 .requires_init = false,
501 };
502
503 static const struct of_device_id hda_tegra_match[] = {
504 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
505 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
506 { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
507 { .compatible = "nvidia,tegra264-hda", .data = &tegra264_data },
508 {},
509 };
510 MODULE_DEVICE_TABLE(of, hda_tegra_match);
511
hda_tegra_probe(struct platform_device * pdev)512 static int hda_tegra_probe(struct platform_device *pdev)
513 {
514 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
515 AZX_DCAPS_PM_RUNTIME |
516 AZX_DCAPS_4K_BDLE_BOUNDARY;
517 struct snd_card *card;
518 struct azx *chip;
519 struct hda_tegra *hda;
520 int err;
521
522 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
523 if (!hda)
524 return -ENOMEM;
525 hda->dev = &pdev->dev;
526 chip = &hda->chip;
527
528 hda->soc = of_device_get_match_data(&pdev->dev);
529
530 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
531 THIS_MODULE, 0, &card);
532 if (err < 0) {
533 dev_err(&pdev->dev, "Error creating card!\n");
534 return err;
535 }
536
537 hda->resets[hda->nresets++].id = "hda";
538
539 /*
540 * "hda2hdmi" is not applicable for Tegra234. This is because the
541 * codec is separate IP and not under display SOR partition now.
542 */
543 if (hda->soc->has_hda2hdmi)
544 hda->resets[hda->nresets++].id = "hda2hdmi";
545
546 /*
547 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
548 * be updated to reflect this, but to have backward compatibility
549 * below is necessary.
550 */
551 if (hda->soc->has_hda2codec_2x_reset)
552 hda->resets[hda->nresets++].id = "hda2codec_2x";
553
554 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
555 hda->resets);
556 if (err)
557 goto out_free;
558
559 hda->clocks[hda->nclocks++].id = "hda";
560 if (hda->soc->has_hda2hdmi)
561 hda->clocks[hda->nclocks++].id = "hda2hdmi";
562
563 if (hda->soc->has_hda2codec_2x)
564 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
565
566 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
567 if (err < 0)
568 goto out_free;
569
570 err = hda_tegra_create(card, driver_flags, hda);
571 if (err < 0)
572 goto out_free;
573 card->private_data = chip;
574
575 dev_set_drvdata(&pdev->dev, card);
576
577 pm_runtime_enable(hda->dev);
578 if (!azx_has_pm_runtime(chip))
579 pm_runtime_forbid(hda->dev);
580
581 schedule_work(&hda->probe_work);
582
583 return 0;
584
585 out_free:
586 snd_card_free(card);
587 return err;
588 }
589
hda_tegra_probe_work(struct work_struct * work)590 static void hda_tegra_probe_work(struct work_struct *work)
591 {
592 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
593 struct azx *chip = &hda->chip;
594 struct platform_device *pdev = to_platform_device(hda->dev);
595 int err;
596
597 pm_runtime_get_sync(hda->dev);
598 err = hda_tegra_first_init(chip, pdev);
599 if (err < 0)
600 goto out_free;
601
602 /* create codec instances */
603 err = azx_probe_codecs(chip, 8);
604 if (err < 0)
605 goto out_free;
606
607 err = azx_codec_configure(chip);
608 if (err < 0)
609 goto out_free;
610
611 err = snd_card_register(chip->card);
612 if (err < 0)
613 goto out_free;
614
615 chip->running = 1;
616 snd_hda_set_power_save(&chip->bus, power_save * 1000);
617
618 out_free:
619 pm_runtime_put(hda->dev);
620 return; /* no error return from async probe */
621 }
622
hda_tegra_remove(struct platform_device * pdev)623 static void hda_tegra_remove(struct platform_device *pdev)
624 {
625 snd_card_free(dev_get_drvdata(&pdev->dev));
626 pm_runtime_disable(&pdev->dev);
627 }
628
hda_tegra_shutdown(struct platform_device * pdev)629 static void hda_tegra_shutdown(struct platform_device *pdev)
630 {
631 struct snd_card *card = dev_get_drvdata(&pdev->dev);
632 struct azx *chip;
633
634 if (!card)
635 return;
636 chip = card->private_data;
637 if (chip && chip->running)
638 azx_stop_chip(chip);
639 }
640
641 static struct platform_driver tegra_platform_hda = {
642 .driver = {
643 .name = "tegra-hda",
644 .pm = &hda_tegra_pm,
645 .of_match_table = hda_tegra_match,
646 },
647 .probe = hda_tegra_probe,
648 .remove_new = hda_tegra_remove,
649 .shutdown = hda_tegra_shutdown,
650 };
651 module_platform_driver(tegra_platform_hda);
652
653 MODULE_DESCRIPTION("Tegra HDA bus driver");
654 MODULE_LICENSE("GPL v2");
655