1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30
31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
32
33 #define KVM_HALT_POLL_NS_DEFAULT 500000
34
35 #include <kvm/arm_vgic.h>
36 #include <kvm/arm_arch_timer.h>
37 #include <kvm/arm_pmu.h>
38
39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
40
41 #define KVM_VCPU_MAX_FEATURES 7
42 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
43
44 #define KVM_REQ_SLEEP \
45 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
46 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
47 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
48 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
49 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
50 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
51 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
52 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
53
54 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
55 KVM_DIRTY_LOG_INITIALLY_SET)
56
57 #define KVM_HAVE_MMU_RWLOCK
58
59 /*
60 * Mode of operation configurable with kvm-arm.mode early param.
61 * See Documentation/admin-guide/kernel-parameters.txt for more information.
62 */
63 enum kvm_mode {
64 KVM_MODE_DEFAULT,
65 KVM_MODE_PROTECTED,
66 KVM_MODE_NV,
67 KVM_MODE_NONE,
68 };
69 #ifdef CONFIG_KVM
70 enum kvm_mode kvm_get_mode(void);
71 #else
kvm_get_mode(void)72 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
73 #endif
74
75 extern unsigned int __ro_after_init kvm_sve_max_vl;
76 int __init kvm_arm_init_sve(void);
77
78 u32 __attribute_const__ kvm_target_cpu(void);
79 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
80 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
81
82 struct kvm_hyp_memcache {
83 phys_addr_t head;
84 unsigned long nr_pages;
85 };
86
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))87 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
88 phys_addr_t *p,
89 phys_addr_t (*to_pa)(void *virt))
90 {
91 *p = mc->head;
92 mc->head = to_pa(p);
93 mc->nr_pages++;
94 }
95
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))96 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
97 void *(*to_va)(phys_addr_t phys))
98 {
99 phys_addr_t *p = to_va(mc->head);
100
101 if (!mc->nr_pages)
102 return NULL;
103
104 mc->head = *p;
105 mc->nr_pages--;
106
107 return p;
108 }
109
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)110 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
111 unsigned long min_pages,
112 void *(*alloc_fn)(void *arg),
113 phys_addr_t (*to_pa)(void *virt),
114 void *arg)
115 {
116 while (mc->nr_pages < min_pages) {
117 phys_addr_t *p = alloc_fn(arg);
118
119 if (!p)
120 return -ENOMEM;
121 push_hyp_memcache(mc, p, to_pa);
122 }
123
124 return 0;
125 }
126
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)127 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
128 void (*free_fn)(void *virt, void *arg),
129 void *(*to_va)(phys_addr_t phys),
130 void *arg)
131 {
132 while (mc->nr_pages)
133 free_fn(pop_hyp_memcache(mc, to_va), arg);
134 }
135
136 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
137 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
138
139 struct kvm_vmid {
140 atomic64_t id;
141 };
142
143 struct kvm_s2_mmu {
144 struct kvm_vmid vmid;
145
146 /*
147 * stage2 entry level table
148 *
149 * Two kvm_s2_mmu structures in the same VM can point to the same
150 * pgd here. This happens when running a guest using a
151 * translation regime that isn't affected by its own stage-2
152 * translation, such as a non-VHE hypervisor running at vEL2, or
153 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
154 * canonical stage-2 page tables.
155 */
156 phys_addr_t pgd_phys;
157 struct kvm_pgtable *pgt;
158
159 /* The last vcpu id that ran on each physical CPU */
160 int __percpu *last_vcpu_ran;
161
162 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
163 /*
164 * Memory cache used to split
165 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
166 * is used to allocate stage2 page tables while splitting huge
167 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
168 * influences both the capacity of the split page cache, and
169 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
170 * too high.
171 *
172 * Protected by kvm->slots_lock.
173 */
174 struct kvm_mmu_memory_cache split_page_cache;
175 uint64_t split_page_chunk_size;
176
177 struct kvm_arch *arch;
178 };
179
180 struct kvm_arch_memory_slot {
181 };
182
183 /**
184 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
185 *
186 * @std_bmap: Bitmap of standard secure service calls
187 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
188 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
189 */
190 struct kvm_smccc_features {
191 unsigned long std_bmap;
192 unsigned long std_hyp_bmap;
193 unsigned long vendor_hyp_bmap;
194 };
195
196 typedef unsigned int pkvm_handle_t;
197
198 struct kvm_protected_vm {
199 pkvm_handle_t handle;
200 struct kvm_hyp_memcache teardown_mc;
201 };
202
203 struct kvm_arch {
204 struct kvm_s2_mmu mmu;
205
206 /* VTCR_EL2 value for this VM */
207 u64 vtcr;
208
209 /* Interrupt controller */
210 struct vgic_dist vgic;
211
212 /* Timers */
213 struct arch_timer_vm_data timer_data;
214
215 /* Mandated version of PSCI */
216 u32 psci_version;
217
218 /* Protects VM-scoped configuration data */
219 struct mutex config_lock;
220
221 /*
222 * If we encounter a data abort without valid instruction syndrome
223 * information, report this to user space. User space can (and
224 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
225 * supported.
226 */
227 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
228 /* Memory Tagging Extension enabled for the guest */
229 #define KVM_ARCH_FLAG_MTE_ENABLED 1
230 /* At least one vCPU has ran in the VM */
231 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
232 /* The vCPU feature set for the VM is configured */
233 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3
234 /* PSCI SYSTEM_SUSPEND enabled for the guest */
235 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4
236 /* VM counter offset */
237 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
238 /* Timer PPIs made immutable */
239 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
240 /* SMCCC filter initialized for the VM */
241 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 7
242 /* Initial ID reg values loaded */
243 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 8
244 unsigned long flags;
245
246 /* VM-wide vCPU feature set */
247 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
248
249 /*
250 * VM-wide PMU filter, implemented as a bitmap and big enough for
251 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
252 */
253 unsigned long *pmu_filter;
254 struct arm_pmu *arm_pmu;
255
256 cpumask_var_t supported_cpus;
257
258 /* Hypercall features firmware registers' descriptor */
259 struct kvm_smccc_features smccc_feat;
260 struct maple_tree smccc_filter;
261
262 /*
263 * Emulated CPU ID registers per VM
264 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
265 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
266 *
267 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
268 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
269 */
270 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
271 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)])
272 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
273 u64 id_regs[KVM_ARM_ID_REG_NUM];
274
275 /*
276 * For an untrusted host VM, 'pkvm.handle' is used to lookup
277 * the associated pKVM instance in the hypervisor.
278 */
279 struct kvm_protected_vm pkvm;
280 };
281
282 struct kvm_vcpu_fault_info {
283 u64 esr_el2; /* Hyp Syndrom Register */
284 u64 far_el2; /* Hyp Fault Address Register */
285 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
286 u64 disr_el1; /* Deferred [SError] Status Register */
287 };
288
289 enum vcpu_sysreg {
290 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
291 MPIDR_EL1, /* MultiProcessor Affinity Register */
292 CLIDR_EL1, /* Cache Level ID Register */
293 CSSELR_EL1, /* Cache Size Selection Register */
294 SCTLR_EL1, /* System Control Register */
295 ACTLR_EL1, /* Auxiliary Control Register */
296 CPACR_EL1, /* Coprocessor Access Control */
297 ZCR_EL1, /* SVE Control */
298 TTBR0_EL1, /* Translation Table Base Register 0 */
299 TTBR1_EL1, /* Translation Table Base Register 1 */
300 TCR_EL1, /* Translation Control Register */
301 TCR2_EL1, /* Extended Translation Control Register */
302 ESR_EL1, /* Exception Syndrome Register */
303 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
304 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
305 FAR_EL1, /* Fault Address Register */
306 MAIR_EL1, /* Memory Attribute Indirection Register */
307 VBAR_EL1, /* Vector Base Address Register */
308 CONTEXTIDR_EL1, /* Context ID Register */
309 TPIDR_EL0, /* Thread ID, User R/W */
310 TPIDRRO_EL0, /* Thread ID, User R/O */
311 TPIDR_EL1, /* Thread ID, Privileged */
312 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
313 CNTKCTL_EL1, /* Timer Control Register (EL1) */
314 PAR_EL1, /* Physical Address Register */
315 MDSCR_EL1, /* Monitor Debug System Control Register */
316 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
317 OSLSR_EL1, /* OS Lock Status Register */
318 DISR_EL1, /* Deferred Interrupt Status Register */
319
320 /* Performance Monitors Registers */
321 PMCR_EL0, /* Control Register */
322 PMSELR_EL0, /* Event Counter Selection Register */
323 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
324 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
325 PMCCNTR_EL0, /* Cycle Counter Register */
326 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
327 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
328 PMCCFILTR_EL0, /* Cycle Count Filter Register */
329 PMCNTENSET_EL0, /* Count Enable Set Register */
330 PMINTENSET_EL1, /* Interrupt Enable Set Register */
331 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
332 PMUSERENR_EL0, /* User Enable Register */
333
334 /* Pointer Authentication Registers in a strict increasing order. */
335 APIAKEYLO_EL1,
336 APIAKEYHI_EL1,
337 APIBKEYLO_EL1,
338 APIBKEYHI_EL1,
339 APDAKEYLO_EL1,
340 APDAKEYHI_EL1,
341 APDBKEYLO_EL1,
342 APDBKEYHI_EL1,
343 APGAKEYLO_EL1,
344 APGAKEYHI_EL1,
345
346 ELR_EL1,
347 SP_EL1,
348 SPSR_EL1,
349
350 CNTVOFF_EL2,
351 CNTV_CVAL_EL0,
352 CNTV_CTL_EL0,
353 CNTP_CVAL_EL0,
354 CNTP_CTL_EL0,
355
356 /* Memory Tagging Extension registers */
357 RGSR_EL1, /* Random Allocation Tag Seed Register */
358 GCR_EL1, /* Tag Control Register */
359 TFSR_EL1, /* Tag Fault Status Register (EL1) */
360 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
361
362 /* Permission Indirection Extension registers */
363 PIR_EL1, /* Permission Indirection Register 1 (EL1) */
364 PIRE0_EL1, /* Permission Indirection Register 0 (EL1) */
365
366 /* 32bit specific registers. */
367 DACR32_EL2, /* Domain Access Control Register */
368 IFSR32_EL2, /* Instruction Fault Status Register */
369 FPEXC32_EL2, /* Floating-Point Exception Control Register */
370 DBGVCR32_EL2, /* Debug Vector Catch Register */
371
372 /* EL2 registers */
373 VPIDR_EL2, /* Virtualization Processor ID Register */
374 VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */
375 SCTLR_EL2, /* System Control Register (EL2) */
376 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
377 HCR_EL2, /* Hypervisor Configuration Register */
378 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
379 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
380 HSTR_EL2, /* Hypervisor System Trap Register */
381 HACR_EL2, /* Hypervisor Auxiliary Control Register */
382 HCRX_EL2, /* Extended Hypervisor Configuration Register */
383 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
384 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
385 TCR_EL2, /* Translation Control Register (EL2) */
386 VTTBR_EL2, /* Virtualization Translation Table Base Register */
387 VTCR_EL2, /* Virtualization Translation Control Register */
388 SPSR_EL2, /* EL2 saved program status register */
389 ELR_EL2, /* EL2 exception link register */
390 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
391 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
392 ESR_EL2, /* Exception Syndrome Register (EL2) */
393 FAR_EL2, /* Fault Address Register (EL2) */
394 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
395 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
396 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
397 VBAR_EL2, /* Vector Base Address Register (EL2) */
398 RVBAR_EL2, /* Reset Vector Base Address Register */
399 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
400 TPIDR_EL2, /* EL2 Software Thread ID Register */
401 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
402 SP_EL2, /* EL2 Stack Pointer */
403 HFGRTR_EL2,
404 HFGWTR_EL2,
405 HFGITR_EL2,
406 HDFGRTR_EL2,
407 HDFGWTR_EL2,
408 CNTHP_CTL_EL2,
409 CNTHP_CVAL_EL2,
410 CNTHV_CTL_EL2,
411 CNTHV_CVAL_EL2,
412
413 NR_SYS_REGS /* Nothing after this line! */
414 };
415
416 struct kvm_cpu_context {
417 struct user_pt_regs regs; /* sp = sp_el0 */
418
419 u64 spsr_abt;
420 u64 spsr_und;
421 u64 spsr_irq;
422 u64 spsr_fiq;
423
424 struct user_fpsimd_state fp_regs;
425
426 u64 sys_regs[NR_SYS_REGS];
427
428 struct kvm_vcpu *__hyp_running_vcpu;
429 };
430
431 struct kvm_host_data {
432 struct kvm_cpu_context host_ctxt;
433 };
434
435 struct kvm_host_psci_config {
436 /* PSCI version used by host. */
437 u32 version;
438 u32 smccc_version;
439
440 /* Function IDs used by host if version is v0.1. */
441 struct psci_0_1_function_ids function_ids_0_1;
442
443 bool psci_0_1_cpu_suspend_implemented;
444 bool psci_0_1_cpu_on_implemented;
445 bool psci_0_1_cpu_off_implemented;
446 bool psci_0_1_migrate_implemented;
447 };
448
449 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
450 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
451
452 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
453 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
454
455 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
456 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
457
458 struct vcpu_reset_state {
459 unsigned long pc;
460 unsigned long r0;
461 bool be;
462 bool reset;
463 };
464
465 struct kvm_vcpu_arch {
466 struct kvm_cpu_context ctxt;
467
468 /*
469 * Guest floating point state
470 *
471 * The architecture has two main floating point extensions,
472 * the original FPSIMD and SVE. These have overlapping
473 * register views, with the FPSIMD V registers occupying the
474 * low 128 bits of the SVE Z registers. When the core
475 * floating point code saves the register state of a task it
476 * records which view it saved in fp_type.
477 */
478 void *sve_state;
479 enum fp_type fp_type;
480 unsigned int sve_max_vl;
481 u64 svcr;
482
483 /* Stage 2 paging state used by the hardware on next switch */
484 struct kvm_s2_mmu *hw_mmu;
485
486 /* Values of trap registers for the guest. */
487 u64 hcr_el2;
488 u64 mdcr_el2;
489 u64 cptr_el2;
490
491 /* Values of trap registers for the host before guest entry. */
492 u64 mdcr_el2_host;
493
494 /* Exception Information */
495 struct kvm_vcpu_fault_info fault;
496
497 /* Ownership of the FP regs */
498 enum {
499 FP_STATE_FREE,
500 FP_STATE_HOST_OWNED,
501 FP_STATE_GUEST_OWNED,
502 } fp_state;
503
504 /* Configuration flags, set once and for all before the vcpu can run */
505 u8 cflags;
506
507 /* Input flags to the hypervisor code, potentially cleared after use */
508 u8 iflags;
509
510 /* State flags for kernel bookkeeping, unused by the hypervisor code */
511 u8 sflags;
512
513 /*
514 * Don't run the guest (internal implementation need).
515 *
516 * Contrary to the flags above, this is set/cleared outside of
517 * a vcpu context, and thus cannot be mixed with the flags
518 * themselves (or the flag accesses need to be made atomic).
519 */
520 bool pause;
521
522 /*
523 * We maintain more than a single set of debug registers to support
524 * debugging the guest from the host and to maintain separate host and
525 * guest state during world switches. vcpu_debug_state are the debug
526 * registers of the vcpu as the guest sees them. host_debug_state are
527 * the host registers which are saved and restored during
528 * world switches. external_debug_state contains the debug
529 * values we want to debug the guest. This is set via the
530 * KVM_SET_GUEST_DEBUG ioctl.
531 *
532 * debug_ptr points to the set of debug registers that should be loaded
533 * onto the hardware when running the guest.
534 */
535 struct kvm_guest_debug_arch *debug_ptr;
536 struct kvm_guest_debug_arch vcpu_debug_state;
537 struct kvm_guest_debug_arch external_debug_state;
538
539 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
540 struct task_struct *parent_task;
541
542 struct {
543 /* {Break,watch}point registers */
544 struct kvm_guest_debug_arch regs;
545 /* Statistical profiling extension */
546 u64 pmscr_el1;
547 /* Self-hosted trace */
548 u64 trfcr_el1;
549 } host_debug_state;
550
551 /* VGIC state */
552 struct vgic_cpu vgic_cpu;
553 struct arch_timer_cpu timer_cpu;
554 struct kvm_pmu pmu;
555
556 /*
557 * Guest registers we preserve during guest debugging.
558 *
559 * These shadow registers are updated by the kvm_handle_sys_reg
560 * trap handler if the guest accesses or updates them while we
561 * are using guest debug.
562 */
563 struct {
564 u32 mdscr_el1;
565 bool pstate_ss;
566 } guest_debug_preserved;
567
568 /* vcpu power state */
569 struct kvm_mp_state mp_state;
570 spinlock_t mp_state_lock;
571
572 /* Cache some mmu pages needed inside spinlock regions */
573 struct kvm_mmu_memory_cache mmu_page_cache;
574
575 /* feature flags */
576 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
577
578 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
579 u64 vsesr_el2;
580
581 /* Additional reset state */
582 struct vcpu_reset_state reset_state;
583
584 /* Guest PV state */
585 struct {
586 u64 last_steal;
587 gpa_t base;
588 } steal;
589
590 /* Per-vcpu CCSIDR override or NULL */
591 u32 *ccsidr;
592 };
593
594 /*
595 * Each 'flag' is composed of a comma-separated triplet:
596 *
597 * - the flag-set it belongs to in the vcpu->arch structure
598 * - the value for that flag
599 * - the mask for that flag
600 *
601 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
602 * unpack_vcpu_flag() extract the flag value from the triplet for
603 * direct use outside of the flag accessors.
604 */
605 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
606
607 #define __unpack_flag(_set, _f, _m) _f
608 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
609
610 #define __build_check_flag(v, flagset, f, m) \
611 do { \
612 typeof(v->arch.flagset) *_fset; \
613 \
614 /* Check that the flags fit in the mask */ \
615 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
616 /* Check that the flags fit in the type */ \
617 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
618 } while (0)
619
620 #define __vcpu_get_flag(v, flagset, f, m) \
621 ({ \
622 __build_check_flag(v, flagset, f, m); \
623 \
624 READ_ONCE(v->arch.flagset) & (m); \
625 })
626
627 /*
628 * Note that the set/clear accessors must be preempt-safe in order to
629 * avoid nesting them with load/put which also manipulate flags...
630 */
631 #ifdef __KVM_NVHE_HYPERVISOR__
632 /* the nVHE hypervisor is always non-preemptible */
633 #define __vcpu_flags_preempt_disable()
634 #define __vcpu_flags_preempt_enable()
635 #else
636 #define __vcpu_flags_preempt_disable() preempt_disable()
637 #define __vcpu_flags_preempt_enable() preempt_enable()
638 #endif
639
640 #define __vcpu_set_flag(v, flagset, f, m) \
641 do { \
642 typeof(v->arch.flagset) *fset; \
643 \
644 __build_check_flag(v, flagset, f, m); \
645 \
646 fset = &v->arch.flagset; \
647 __vcpu_flags_preempt_disable(); \
648 if (HWEIGHT(m) > 1) \
649 *fset &= ~(m); \
650 *fset |= (f); \
651 __vcpu_flags_preempt_enable(); \
652 } while (0)
653
654 #define __vcpu_clear_flag(v, flagset, f, m) \
655 do { \
656 typeof(v->arch.flagset) *fset; \
657 \
658 __build_check_flag(v, flagset, f, m); \
659 \
660 fset = &v->arch.flagset; \
661 __vcpu_flags_preempt_disable(); \
662 *fset &= ~(m); \
663 __vcpu_flags_preempt_enable(); \
664 } while (0)
665
666 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
667 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
668 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
669
670 /* SVE exposed to guest */
671 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0))
672 /* SVE config completed */
673 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
674 /* PTRAUTH exposed to guest */
675 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2))
676 /* KVM_ARM_VCPU_INIT completed */
677 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(3))
678
679 /* Exception pending */
680 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
681 /*
682 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
683 * be set together with an exception...
684 */
685 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
686 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
687 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
688
689 /* Helpers to encode exceptions with minimum fuss */
690 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
691 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
692 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
693
694 /*
695 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
696 * values:
697 *
698 * For AArch32 EL1:
699 */
700 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
701 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
702 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
703 /* For AArch64: */
704 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
705 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
706 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
707 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
708 /* For AArch64 with NV: */
709 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
710 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
711 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
712 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
713 /* Guest debug is live */
714 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
715 /* Save SPE context if active */
716 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
717 /* Save TRBE context if active */
718 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
719 /* vcpu running in HYP context */
720 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
721
722 /* SVE enabled for host EL0 */
723 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
724 /* SME enabled for EL0 */
725 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1))
726 /* Physical CPU not in supported_cpus */
727 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
728 /* WFIT instruction trapped */
729 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
730 /* vcpu system registers loaded on physical CPU */
731 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
732 /* Software step state is Active-pending */
733 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
734 /* PMUSERENR for the guest EL0 is on physical CPU */
735 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6))
736 /* WFI instruction trapped */
737 #define IN_WFI __vcpu_single_flag(sflags, BIT(7))
738
739
740 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
741 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
742 sve_ffr_offset((vcpu)->arch.sve_max_vl))
743
744 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
745
746 #define vcpu_sve_state_size(vcpu) ({ \
747 size_t __size_ret; \
748 unsigned int __vcpu_vq; \
749 \
750 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
751 __size_ret = 0; \
752 } else { \
753 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
754 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
755 } \
756 \
757 __size_ret; \
758 })
759
760 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
761 KVM_GUESTDBG_USE_SW_BP | \
762 KVM_GUESTDBG_USE_HW | \
763 KVM_GUESTDBG_SINGLESTEP)
764
765 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
766 vcpu_get_flag(vcpu, GUEST_HAS_SVE))
767
768 #ifdef CONFIG_ARM64_PTR_AUTH
769 #define vcpu_has_ptrauth(vcpu) \
770 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
771 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
772 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
773 #else
774 #define vcpu_has_ptrauth(vcpu) false
775 #endif
776
777 #define vcpu_on_unsupported_cpu(vcpu) \
778 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
779
780 #define vcpu_set_on_unsupported_cpu(vcpu) \
781 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
782
783 #define vcpu_clear_on_unsupported_cpu(vcpu) \
784 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
785
786 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
787
788 /*
789 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
790 * memory backed version of a register, and not the one most recently
791 * accessed by a running VCPU. For example, for userspace access or
792 * for system registers that are never context switched, but only
793 * emulated.
794 */
795 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
796
797 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
798
799 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
800
801 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
802 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
803
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)804 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
805 {
806 /*
807 * *** VHE ONLY ***
808 *
809 * System registers listed in the switch are not saved on every
810 * exit from the guest but are only saved on vcpu_put.
811 *
812 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
813 * should never be listed below, because the guest cannot modify its
814 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
815 * thread when emulating cross-VCPU communication.
816 */
817 if (!has_vhe())
818 return false;
819
820 switch (reg) {
821 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
822 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
823 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
824 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
825 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
826 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
827 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
828 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
829 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
830 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
831 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
832 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
833 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
834 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
835 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
836 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
837 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
838 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
839 case PAR_EL1: *val = read_sysreg_par(); break;
840 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
841 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
842 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
843 default: return false;
844 }
845
846 return true;
847 }
848
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)849 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
850 {
851 /*
852 * *** VHE ONLY ***
853 *
854 * System registers listed in the switch are not restored on every
855 * entry to the guest but are only restored on vcpu_load.
856 *
857 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
858 * should never be listed below, because the MPIDR should only be set
859 * once, before running the VCPU, and never changed later.
860 */
861 if (!has_vhe())
862 return false;
863
864 switch (reg) {
865 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
866 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
867 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
868 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
869 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
870 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
871 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
872 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
873 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
874 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
875 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
876 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
877 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
878 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
879 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
880 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
881 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
882 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
883 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
884 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
885 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
886 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
887 default: return false;
888 }
889
890 return true;
891 }
892
893 struct kvm_vm_stat {
894 struct kvm_vm_stat_generic generic;
895 };
896
897 struct kvm_vcpu_stat {
898 struct kvm_vcpu_stat_generic generic;
899 u64 hvc_exit_stat;
900 u64 wfe_exit_stat;
901 u64 wfi_exit_stat;
902 u64 mmio_exit_user;
903 u64 mmio_exit_kernel;
904 u64 signal_exits;
905 u64 exits;
906 };
907
908 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
909 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
910 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
911 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
912
913 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
914 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
915
916 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
917 struct kvm_vcpu_events *events);
918
919 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
920 struct kvm_vcpu_events *events);
921
922 #define KVM_ARCH_WANT_MMU_NOTIFIER
923
924 void kvm_arm_halt_guest(struct kvm *kvm);
925 void kvm_arm_resume_guest(struct kvm *kvm);
926
927 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
928
929 #ifndef __KVM_NVHE_HYPERVISOR__
930 #define kvm_call_hyp_nvhe(f, ...) \
931 ({ \
932 struct arm_smccc_res res; \
933 \
934 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
935 ##__VA_ARGS__, &res); \
936 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
937 \
938 res.a1; \
939 })
940
941 /*
942 * The couple of isb() below are there to guarantee the same behaviour
943 * on VHE as on !VHE, where the eret to EL1 acts as a context
944 * synchronization event.
945 */
946 #define kvm_call_hyp(f, ...) \
947 do { \
948 if (has_vhe()) { \
949 f(__VA_ARGS__); \
950 isb(); \
951 } else { \
952 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
953 } \
954 } while(0)
955
956 #define kvm_call_hyp_ret(f, ...) \
957 ({ \
958 typeof(f(__VA_ARGS__)) ret; \
959 \
960 if (has_vhe()) { \
961 ret = f(__VA_ARGS__); \
962 isb(); \
963 } else { \
964 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
965 } \
966 \
967 ret; \
968 })
969 #else /* __KVM_NVHE_HYPERVISOR__ */
970 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
971 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
972 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
973 #endif /* __KVM_NVHE_HYPERVISOR__ */
974
975 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
976 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
977
978 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
979 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
980 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
981 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
982 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
983 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
984 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
985
986 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
987
988 int __init kvm_sys_reg_table_init(void);
989 int __init populate_nv_trap_config(void);
990
991 bool lock_all_vcpus(struct kvm *kvm);
992 void unlock_all_vcpus(struct kvm *kvm);
993
994 /* MMIO helpers */
995 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
996 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
997
998 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
999 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1000
1001 /*
1002 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1003 * arrived in guest context. For arm64, any event that arrives while a vCPU is
1004 * loaded is considered to be "in guest".
1005 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1006 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1007 {
1008 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1009 }
1010
1011 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1012 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1013 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1014
1015 bool kvm_arm_pvtime_supported(void);
1016 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1017 struct kvm_device_attr *attr);
1018 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1019 struct kvm_device_attr *attr);
1020 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1021 struct kvm_device_attr *attr);
1022
1023 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1024 int __init kvm_arm_vmid_alloc_init(void);
1025 void __init kvm_arm_vmid_alloc_free(void);
1026 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1027 void kvm_arm_vmid_clear_active(void);
1028
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1029 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1030 {
1031 vcpu_arch->steal.base = INVALID_GPA;
1032 }
1033
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1034 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1035 {
1036 return (vcpu_arch->steal.base != INVALID_GPA);
1037 }
1038
1039 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1040
1041 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1042
1043 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1044
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1045 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1046 {
1047 /* The host's MPIDR is immutable, so let's set it up at boot time */
1048 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1049 }
1050
kvm_system_needs_idmapped_vectors(void)1051 static inline bool kvm_system_needs_idmapped_vectors(void)
1052 {
1053 return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1054 }
1055
kvm_arch_sync_events(struct kvm * kvm)1056 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)1057 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1058
1059 void kvm_arm_init_debug(void);
1060 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1061 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1062 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1063 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1064
1065 #define kvm_vcpu_os_lock_enabled(vcpu) \
1066 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1067
1068 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1069 struct kvm_device_attr *attr);
1070 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1071 struct kvm_device_attr *attr);
1072 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1073 struct kvm_device_attr *attr);
1074
1075 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1076 struct kvm_arm_copy_mte_tags *copy_tags);
1077 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1078 struct kvm_arm_counter_offset *offset);
1079
1080 /* Guest/host FPSIMD coordination helpers */
1081 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1082 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1083 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1084 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1085 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1086 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1087
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1088 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1089 {
1090 return (!has_vhe() && attr->exclude_host);
1091 }
1092
1093 /* Flags for host debug state */
1094 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1095 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1096
1097 #ifdef CONFIG_KVM
1098 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1099 void kvm_clr_pmu_events(u32 clr);
1100 bool kvm_set_pmuserenr(u64 val);
1101 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)1102 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)1103 static inline void kvm_clr_pmu_events(u32 clr) {}
kvm_set_pmuserenr(u64 val)1104 static inline bool kvm_set_pmuserenr(u64 val)
1105 {
1106 return false;
1107 }
1108 #endif
1109
1110 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1111 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1112
1113 int __init kvm_set_ipa_limit(void);
1114
1115 #define __KVM_HAVE_ARCH_VM_ALLOC
1116 struct kvm *kvm_arch_alloc_vm(void);
1117
1118 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1119
1120 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1121
kvm_vm_is_protected(struct kvm * kvm)1122 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1123 {
1124 return false;
1125 }
1126
1127 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1128 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1129
1130 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1131
1132 #define kvm_has_mte(kvm) \
1133 (system_supports_mte() && \
1134 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1135
1136 #define kvm_supports_32bit_el0() \
1137 (system_supports_32bit_el0() && \
1138 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1139
1140 #define kvm_vm_has_ran_once(kvm) \
1141 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1142
1143 int kvm_trng_call(struct kvm_vcpu *vcpu);
1144 #ifdef CONFIG_KVM
1145 extern phys_addr_t hyp_mem_base;
1146 extern phys_addr_t hyp_mem_size;
1147 void __init kvm_hyp_reserve(void);
1148 #else
kvm_hyp_reserve(void)1149 static inline void kvm_hyp_reserve(void) { }
1150 #endif
1151
1152 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1153 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1154
1155 #endif /* __ARM64_KVM_HOST_H__ */
1156