xref: /openbmc/linux/drivers/clk/x86/clk-lgm.c (revision 7256d1f4)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2020-2022 MaxLinear, Inc.
4  * Copyright (C) 2020 Intel Corporation.
5  * Zhu Yixin <yzhu@maxlinear.com>
6  * Rahul Tanwar <rtanwar@maxlinear.com>
7  */
8 #include <linux/clk-provider.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <dt-bindings/clock/intel,lgm-clk.h>
13 #include "clk-cgu.h"
14 
15 #define PLL_DIV_WIDTH		4
16 #define PLL_DDIV_WIDTH		3
17 
18 /* Gate0 clock shift */
19 #define G_C55_SHIFT		7
20 #define G_QSPI_SHIFT		9
21 #define G_EIP197_SHIFT		11
22 #define G_VAULT130_SHIFT	12
23 #define G_TOE_SHIFT		13
24 #define G_SDXC_SHIFT		14
25 #define G_EMMC_SHIFT		15
26 #define G_SPIDBG_SHIFT		17
27 #define G_DMA3_SHIFT		28
28 
29 /* Gate1 clock shift */
30 #define G_DMA0_SHIFT		0
31 #define G_LEDC0_SHIFT		1
32 #define G_LEDC1_SHIFT		2
33 #define G_I2S0_SHIFT		3
34 #define G_I2S1_SHIFT		4
35 #define G_EBU_SHIFT		5
36 #define G_PWM_SHIFT		6
37 #define G_I2C0_SHIFT		7
38 #define G_I2C1_SHIFT		8
39 #define G_I2C2_SHIFT		9
40 #define G_I2C3_SHIFT		10
41 
42 #define G_SSC0_SHIFT		12
43 #define G_SSC1_SHIFT		13
44 #define G_SSC2_SHIFT		14
45 #define G_SSC3_SHIFT		15
46 
47 #define G_GPTC0_SHIFT		17
48 #define G_GPTC1_SHIFT		18
49 #define G_GPTC2_SHIFT		19
50 #define G_GPTC3_SHIFT		20
51 
52 #define G_ASC0_SHIFT		22
53 #define G_ASC1_SHIFT		23
54 #define G_ASC2_SHIFT		24
55 #define G_ASC3_SHIFT		25
56 
57 #define G_PCM0_SHIFT		27
58 #define G_PCM1_SHIFT		28
59 #define G_PCM2_SHIFT		29
60 
61 /* Gate2 clock shift */
62 #define G_PCIE10_SHIFT		1
63 #define G_PCIE11_SHIFT		2
64 #define G_PCIE30_SHIFT		3
65 #define G_PCIE31_SHIFT		4
66 #define G_PCIE20_SHIFT		5
67 #define G_PCIE21_SHIFT		6
68 #define G_PCIE40_SHIFT		7
69 #define G_PCIE41_SHIFT		8
70 
71 #define G_XPCS0_SHIFT		10
72 #define G_XPCS1_SHIFT		11
73 #define G_XPCS2_SHIFT		12
74 #define G_XPCS3_SHIFT		13
75 #define G_SATA0_SHIFT		14
76 #define G_SATA1_SHIFT		15
77 #define G_SATA2_SHIFT		16
78 #define G_SATA3_SHIFT		17
79 
80 /* Gate3 clock shift */
81 #define G_ARCEM4_SHIFT		0
82 #define G_IDMAR1_SHIFT		2
83 #define G_IDMAT0_SHIFT		3
84 #define G_IDMAT1_SHIFT		4
85 #define G_IDMAT2_SHIFT		5
86 
87 #define G_PPV4_SHIFT		8
88 #define G_GSWIPO_SHIFT		9
89 #define G_CQEM_SHIFT		10
90 #define G_XPCS5_SHIFT		14
91 #define G_USB1_SHIFT		25
92 #define G_USB2_SHIFT		26
93 
94 
95 /* Register definition */
96 #define CGU_PLL0CZ_CFG0		0x000
97 #define CGU_PLL0CM0_CFG0	0x020
98 #define CGU_PLL0CM1_CFG0	0x040
99 #define CGU_PLL0B_CFG0		0x060
100 #define CGU_PLL1_CFG0		0x080
101 #define CGU_PLL2_CFG0		0x0A0
102 #define CGU_PLLPP_CFG0		0x0C0
103 #define CGU_LJPLL3_CFG0		0x0E0
104 #define CGU_LJPLL4_CFG0		0x100
105 #define CGU_C55_PCMCR		0x18C
106 #define CGU_PCMCR		0x190
107 #define CGU_IF_CLK1		0x1A0
108 #define CGU_IF_CLK2		0x1A4
109 #define CGU_GATE0		0x300
110 #define CGU_GATE1		0x310
111 #define CGU_GATE2		0x320
112 #define CGU_GATE3		0x310
113 
114 #define PLL_DIV(x)		((x) + 0x04)
115 #define PLL_SSC(x)		((x) + 0x10)
116 
117 #define CLK_NR_CLKS		(LGM_GCLK_USB2 + 1)
118 
119 /*
120  * Below table defines the pair's of regval & effective dividers.
121  * It's more efficient to provide an explicit table due to non-linear
122  * relation between values.
123  */
124 static const struct clk_div_table pll_div[] = {
125 	{ .val = 0, .div = 1 },
126 	{ .val = 1, .div = 2 },
127 	{ .val = 2, .div = 3 },
128 	{ .val = 3, .div = 4 },
129 	{ .val = 4, .div = 5 },
130 	{ .val = 5, .div = 6 },
131 	{ .val = 6, .div = 8 },
132 	{ .val = 7, .div = 10 },
133 	{ .val = 8, .div = 12 },
134 	{ .val = 9, .div = 16 },
135 	{ .val = 10, .div = 20 },
136 	{ .val = 11, .div = 24 },
137 	{ .val = 12, .div = 32 },
138 	{ .val = 13, .div = 40 },
139 	{ .val = 14, .div = 48 },
140 	{ .val = 15, .div = 64 },
141 	{}
142 };
143 
144 static const struct clk_div_table dcl_div[] = {
145 	{ .val = 0, .div = 6  },
146 	{ .val = 1, .div = 12 },
147 	{ .val = 2, .div = 24 },
148 	{ .val = 3, .div = 32 },
149 	{ .val = 4, .div = 48 },
150 	{ .val = 5, .div = 96 },
151 	{}
152 };
153 
154 static const struct clk_parent_data pll_p[] = {
155 	{ .fw_name = "osc", .name = "osc" },
156 };
157 static const struct clk_parent_data pllcm_p[] = {
158 	{ .fw_name = "cpu_cm", .name = "cpu_cm" },
159 };
160 static const struct clk_parent_data emmc_p[] = {
161 	{ .fw_name = "emmc4", .name = "emmc4" },
162 	{ .fw_name = "noc4", .name = "noc4" },
163 };
164 static const struct clk_parent_data sdxc_p[] = {
165 	{ .fw_name = "sdxc3", .name = "sdxc3" },
166 	{ .fw_name = "sdxc2", .name = "sdxc2" },
167 };
168 static const struct clk_parent_data pcm_p[] = {
169 	{ .fw_name = "v_docsis", .name = "v_docsis" },
170 	{ .fw_name = "dcl", .name = "dcl" },
171 };
172 static const struct clk_parent_data cbphy_p[] = {
173 	{ .fw_name = "dd_serdes", .name = "dd_serdes" },
174 	{ .fw_name = "dd_pcie", .name = "dd_pcie" },
175 };
176 
177 static const struct lgm_pll_clk_data lgm_pll_clks[] = {
178 	LGM_PLL(LGM_CLK_PLL0CZ, "pll0cz", pll_p, CLK_IGNORE_UNUSED,
179 		CGU_PLL0CZ_CFG0, TYPE_ROPLL),
180 	LGM_PLL(LGM_CLK_PLL0CM0, "pll0cm0", pllcm_p, CLK_IGNORE_UNUSED,
181 		CGU_PLL0CM0_CFG0, TYPE_ROPLL),
182 	LGM_PLL(LGM_CLK_PLL0CM1, "pll0cm1", pllcm_p, CLK_IGNORE_UNUSED,
183 		CGU_PLL0CM1_CFG0, TYPE_ROPLL),
184 	LGM_PLL(LGM_CLK_PLL0B, "pll0b", pll_p, CLK_IGNORE_UNUSED,
185 		CGU_PLL0B_CFG0, TYPE_ROPLL),
186 	LGM_PLL(LGM_CLK_PLL1, "pll1", pll_p, 0, CGU_PLL1_CFG0, TYPE_ROPLL),
187 	LGM_PLL(LGM_CLK_PLL2, "pll2", pll_p, CLK_IGNORE_UNUSED,
188 		CGU_PLL2_CFG0, TYPE_ROPLL),
189 	LGM_PLL(LGM_CLK_PLLPP, "pllpp", pll_p, 0, CGU_PLLPP_CFG0, TYPE_ROPLL),
190 	LGM_PLL(LGM_CLK_LJPLL3, "ljpll3", pll_p, 0, CGU_LJPLL3_CFG0, TYPE_LJPLL),
191 	LGM_PLL(LGM_CLK_LJPLL4, "ljpll4", pll_p, 0, CGU_LJPLL4_CFG0, TYPE_LJPLL),
192 };
193 
194 static const struct lgm_clk_branch lgm_branch_clks[] = {
195 	LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
196 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
197 	LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
198 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
199 	LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
200 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
201 	LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
202 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
203 	LGM_DIV(LGM_CLK_DDR, "ddr", "pll2", CLK_IGNORE_UNUSED,
204 		PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
205 		pll_div),
206 	LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
207 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
208 
209 	LGM_DIV(LGM_CLK_IC, "cpu_ic", "pll0cz", CLK_IGNORE_UNUSED,
210 		PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
211 		1, 0, 0, pll_div),
212 
213 	LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
214 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
215 
216 	LGM_DIV(LGM_CLK_CPU0, "cm0", "pll0cm0",
217 		CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
218 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
219 	LGM_DIV(LGM_CLK_CPU1, "cm1", "pll0cm1",
220 		CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
221 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
222 
223 	/*
224 	 * Marking ngi_clk (next generation interconnect) and noc_clk
225 	 * (network on chip peripheral clk) as critical clocks because
226 	 * these are shared parent clock sources for many different
227 	 * peripherals.
228 	 */
229 	LGM_DIV(LGM_CLK_NGI, "ngi", "pll0b",
230 		(CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
231 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
232 	LGM_DIV(LGM_CLK_NOC4, "noc4", "pll0b",
233 		(CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
234 		4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
235 	LGM_DIV(LGM_CLK_SW, "switch", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
236 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
237 	LGM_DIV(LGM_CLK_QSPI, "qspi", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
238 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
239 	LGM_DIV(LGM_CLK_CT, "v_ct", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
240 		0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
241 	LGM_DIV(LGM_CLK_DSP, "v_dsp", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
242 		8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
243 	LGM_DIV(LGM_CLK_VIF, "v_ifclk", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
244 		12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
245 
246 	LGM_FIXED_FACTOR(LGM_CLK_EMMC4, "emmc4", "sdxc3", 0,  0,
247 			 0, 0, 0, 0, 1, 4),
248 	LGM_FIXED_FACTOR(LGM_CLK_SDXC2, "sdxc2", "noc4", 0,  0,
249 			 0, 0, 0, 0, 1, 4),
250 	LGM_MUX(LGM_CLK_EMMC, "emmc", emmc_p, 0, CGU_IF_CLK1,
251 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
252 	LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
253 		1, 1, CLK_MUX_ROUND_CLOSEST, 0),
254 	LGM_FIXED(LGM_CLK_OSC, "osc", NULL, 0, 0, 0, 0, 0, 40000000, 0),
255 	LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
256 		  8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
257 	LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
258 	LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
259 		25, 3, 0, 0, DIV_CLK_NO_MASK, 0, dcl_div),
260 	LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
261 		0, 1, CLK_MUX_ROUND_CLOSEST, 0),
262 	LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
263 			 CLK_IGNORE_UNUSED, 0,
264 			 0, 0, 0, 0, 2, 1),
265 	LGM_FIXED_FACTOR(LGM_CLK_PONDEF, "pondef", "dd_pool",
266 			 CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
267 	LGM_MUX(LGM_CLK_CBPHY0, "cbphy0", cbphy_p, 0, 0,
268 		0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
269 	LGM_MUX(LGM_CLK_CBPHY1, "cbphy1", cbphy_p, 0, 0,
270 		0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
271 	LGM_MUX(LGM_CLK_CBPHY2, "cbphy2", cbphy_p, 0, 0,
272 		0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
273 	LGM_MUX(LGM_CLK_CBPHY3, "cbphy3", cbphy_p, 0, 0,
274 		0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
275 
276 	LGM_GATE(LGM_GCLK_C55, "g_c55", NULL, 0, CGU_GATE0,
277 		 G_C55_SHIFT, 0, 0),
278 	LGM_GATE(LGM_GCLK_QSPI, "g_qspi", "qspi", 0, CGU_GATE0,
279 		 G_QSPI_SHIFT, 0, 0),
280 	LGM_GATE(LGM_GCLK_EIP197, "g_eip197", NULL, 0, CGU_GATE0,
281 		 G_EIP197_SHIFT, 0, 0),
282 	LGM_GATE(LGM_GCLK_VAULT, "g_vault130", NULL, 0, CGU_GATE0,
283 		 G_VAULT130_SHIFT, 0, 0),
284 	LGM_GATE(LGM_GCLK_TOE, "g_toe", NULL, 0, CGU_GATE0,
285 		 G_TOE_SHIFT, 0, 0),
286 	LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
287 		 G_SDXC_SHIFT, 0, 0),
288 	LGM_GATE(LGM_GCLK_EMMC, "g_emmc", "emmc", 0, CGU_GATE0,
289 		 G_EMMC_SHIFT, 0, 0),
290 	LGM_GATE(LGM_GCLK_SPI_DBG, "g_spidbg", NULL, 0, CGU_GATE0,
291 		 G_SPIDBG_SHIFT, 0, 0),
292 	LGM_GATE(LGM_GCLK_DMA3, "g_dma3", NULL, 0, CGU_GATE0,
293 		 G_DMA3_SHIFT, 0, 0),
294 
295 	LGM_GATE(LGM_GCLK_DMA0, "g_dma0", NULL, 0, CGU_GATE1,
296 		 G_DMA0_SHIFT, 0, 0),
297 	LGM_GATE(LGM_GCLK_LEDC0, "g_ledc0", NULL, 0, CGU_GATE1,
298 		 G_LEDC0_SHIFT, 0, 0),
299 	LGM_GATE(LGM_GCLK_LEDC1, "g_ledc1", NULL, 0, CGU_GATE1,
300 		 G_LEDC1_SHIFT, 0, 0),
301 	LGM_GATE(LGM_GCLK_I2S0, "g_i2s0", NULL, 0, CGU_GATE1,
302 		 G_I2S0_SHIFT, 0, 0),
303 	LGM_GATE(LGM_GCLK_I2S1, "g_i2s1", NULL, 0, CGU_GATE1,
304 		 G_I2S1_SHIFT, 0, 0),
305 	LGM_GATE(LGM_GCLK_EBU, "g_ebu", NULL, 0, CGU_GATE1,
306 		 G_EBU_SHIFT, 0, 0),
307 	LGM_GATE(LGM_GCLK_PWM, "g_pwm", NULL, 0, CGU_GATE1,
308 		 G_PWM_SHIFT, 0, 0),
309 	LGM_GATE(LGM_GCLK_I2C0, "g_i2c0", NULL, 0, CGU_GATE1,
310 		 G_I2C0_SHIFT, 0, 0),
311 	LGM_GATE(LGM_GCLK_I2C1, "g_i2c1", NULL, 0, CGU_GATE1,
312 		 G_I2C1_SHIFT, 0, 0),
313 	LGM_GATE(LGM_GCLK_I2C2, "g_i2c2", NULL, 0, CGU_GATE1,
314 		 G_I2C2_SHIFT, 0, 0),
315 	LGM_GATE(LGM_GCLK_I2C3, "g_i2c3", NULL, 0, CGU_GATE1,
316 		 G_I2C3_SHIFT, 0, 0),
317 	LGM_GATE(LGM_GCLK_SSC0, "g_ssc0", "noc4", 0, CGU_GATE1,
318 		 G_SSC0_SHIFT, 0, 0),
319 	LGM_GATE(LGM_GCLK_SSC1, "g_ssc1", "noc4", 0, CGU_GATE1,
320 		 G_SSC1_SHIFT, 0, 0),
321 	LGM_GATE(LGM_GCLK_SSC2, "g_ssc2", "noc4", 0, CGU_GATE1,
322 		 G_SSC2_SHIFT, 0, 0),
323 	LGM_GATE(LGM_GCLK_SSC3, "g_ssc3", "noc4", 0, CGU_GATE1,
324 		 G_SSC3_SHIFT, 0, 0),
325 	LGM_GATE(LGM_GCLK_GPTC0, "g_gptc0", "noc4", 0, CGU_GATE1,
326 		 G_GPTC0_SHIFT, 0, 0),
327 	LGM_GATE(LGM_GCLK_GPTC1, "g_gptc1", "noc4", 0, CGU_GATE1,
328 		 G_GPTC1_SHIFT, 0, 0),
329 	LGM_GATE(LGM_GCLK_GPTC2, "g_gptc2", "noc4", 0, CGU_GATE1,
330 		 G_GPTC2_SHIFT, 0, 0),
331 	LGM_GATE(LGM_GCLK_GPTC3, "g_gptc3", "osc", 0, CGU_GATE1,
332 		 G_GPTC3_SHIFT, 0, 0),
333 	LGM_GATE(LGM_GCLK_ASC0, "g_asc0", "noc4", 0, CGU_GATE1,
334 		 G_ASC0_SHIFT, 0, 0),
335 	LGM_GATE(LGM_GCLK_ASC1, "g_asc1", "noc4", 0, CGU_GATE1,
336 		 G_ASC1_SHIFT, 0, 0),
337 	LGM_GATE(LGM_GCLK_ASC2, "g_asc2", "noc4", 0, CGU_GATE1,
338 		 G_ASC2_SHIFT, 0, 0),
339 	LGM_GATE(LGM_GCLK_ASC3, "g_asc3", "osc", 0, CGU_GATE1,
340 		 G_ASC3_SHIFT, 0, 0),
341 	LGM_GATE(LGM_GCLK_PCM0, "g_pcm0", NULL, 0, CGU_GATE1,
342 		 G_PCM0_SHIFT, 0, 0),
343 	LGM_GATE(LGM_GCLK_PCM1, "g_pcm1", NULL, 0, CGU_GATE1,
344 		 G_PCM1_SHIFT, 0, 0),
345 	LGM_GATE(LGM_GCLK_PCM2, "g_pcm2", NULL, 0, CGU_GATE1,
346 		 G_PCM2_SHIFT, 0, 0),
347 
348 	LGM_GATE(LGM_GCLK_PCIE10, "g_pcie10", NULL, 0, CGU_GATE2,
349 		 G_PCIE10_SHIFT, 0, 0),
350 	LGM_GATE(LGM_GCLK_PCIE11, "g_pcie11", NULL, 0, CGU_GATE2,
351 		 G_PCIE11_SHIFT, 0, 0),
352 	LGM_GATE(LGM_GCLK_PCIE30, "g_pcie30", NULL, 0, CGU_GATE2,
353 		 G_PCIE30_SHIFT, 0, 0),
354 	LGM_GATE(LGM_GCLK_PCIE31, "g_pcie31", NULL, 0, CGU_GATE2,
355 		 G_PCIE31_SHIFT, 0, 0),
356 	LGM_GATE(LGM_GCLK_PCIE20, "g_pcie20", NULL, 0, CGU_GATE2,
357 		 G_PCIE20_SHIFT, 0, 0),
358 	LGM_GATE(LGM_GCLK_PCIE21, "g_pcie21", NULL, 0, CGU_GATE2,
359 		 G_PCIE21_SHIFT, 0, 0),
360 	LGM_GATE(LGM_GCLK_PCIE40, "g_pcie40", NULL, 0, CGU_GATE2,
361 		 G_PCIE40_SHIFT, 0, 0),
362 	LGM_GATE(LGM_GCLK_PCIE41, "g_pcie41", NULL, 0, CGU_GATE2,
363 		 G_PCIE41_SHIFT, 0, 0),
364 	LGM_GATE(LGM_GCLK_XPCS0, "g_xpcs0", NULL, 0, CGU_GATE2,
365 		 G_XPCS0_SHIFT, 0, 0),
366 	LGM_GATE(LGM_GCLK_XPCS1, "g_xpcs1", NULL, 0, CGU_GATE2,
367 		 G_XPCS1_SHIFT, 0, 0),
368 	LGM_GATE(LGM_GCLK_XPCS2, "g_xpcs2", NULL, 0, CGU_GATE2,
369 		 G_XPCS2_SHIFT, 0, 0),
370 	LGM_GATE(LGM_GCLK_XPCS3, "g_xpcs3", NULL, 0, CGU_GATE2,
371 		 G_XPCS3_SHIFT, 0, 0),
372 	LGM_GATE(LGM_GCLK_SATA0, "g_sata0", NULL, 0, CGU_GATE2,
373 		 G_SATA0_SHIFT, 0, 0),
374 	LGM_GATE(LGM_GCLK_SATA1, "g_sata1", NULL, 0, CGU_GATE2,
375 		 G_SATA1_SHIFT, 0, 0),
376 	LGM_GATE(LGM_GCLK_SATA2, "g_sata2", NULL, 0, CGU_GATE2,
377 		 G_SATA2_SHIFT, 0, 0),
378 	LGM_GATE(LGM_GCLK_SATA3, "g_sata3", NULL, 0, CGU_GATE2,
379 		 G_SATA3_SHIFT, 0, 0),
380 
381 	LGM_GATE(LGM_GCLK_ARCEM4, "g_arcem4", NULL, 0, CGU_GATE3,
382 		 G_ARCEM4_SHIFT, 0, 0),
383 	LGM_GATE(LGM_GCLK_IDMAR1, "g_idmar1", NULL, 0, CGU_GATE3,
384 		 G_IDMAR1_SHIFT, 0, 0),
385 	LGM_GATE(LGM_GCLK_IDMAT0, "g_idmat0", NULL, 0, CGU_GATE3,
386 		 G_IDMAT0_SHIFT, 0, 0),
387 	LGM_GATE(LGM_GCLK_IDMAT1, "g_idmat1", NULL, 0, CGU_GATE3,
388 		 G_IDMAT1_SHIFT, 0, 0),
389 	LGM_GATE(LGM_GCLK_IDMAT2, "g_idmat2", NULL, 0, CGU_GATE3,
390 		 G_IDMAT2_SHIFT, 0, 0),
391 	LGM_GATE(LGM_GCLK_PPV4, "g_ppv4", NULL, 0, CGU_GATE3,
392 		 G_PPV4_SHIFT, 0, 0),
393 	LGM_GATE(LGM_GCLK_GSWIPO, "g_gswipo", "switch", 0, CGU_GATE3,
394 		 G_GSWIPO_SHIFT, 0, 0),
395 	LGM_GATE(LGM_GCLK_CQEM, "g_cqem", "switch", 0, CGU_GATE3,
396 		 G_CQEM_SHIFT, 0, 0),
397 	LGM_GATE(LGM_GCLK_XPCS5, "g_xpcs5", NULL, 0, CGU_GATE3,
398 		 G_XPCS5_SHIFT, 0, 0),
399 	LGM_GATE(LGM_GCLK_USB1, "g_usb1", NULL, 0, CGU_GATE3,
400 		 G_USB1_SHIFT, 0, 0),
401 	LGM_GATE(LGM_GCLK_USB2, "g_usb2", NULL, 0, CGU_GATE3,
402 		 G_USB2_SHIFT, 0, 0),
403 };
404 
405 
406 static const struct lgm_clk_ddiv_data lgm_ddiv_clks[] = {
407 	LGM_DDIV(LGM_CLK_CML, "dd_cml", "ljpll3", 0,
408 		 PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
409 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
410 	LGM_DDIV(LGM_CLK_SERDES, "dd_serdes", "ljpll3", 0,
411 		 PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
412 		 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
413 	LGM_DDIV(LGM_CLK_POOL, "dd_pool", "ljpll3", 0,
414 		 PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
415 		 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
416 	LGM_DDIV(LGM_CLK_PTP, "dd_ptp", "ljpll3", 0,
417 		 PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
418 		 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
419 	LGM_DDIV(LGM_CLK_PCIE, "dd_pcie", "ljpll4", 0,
420 		 PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,
421 		 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
422 };
423 
lgm_cgu_probe(struct platform_device * pdev)424 static int lgm_cgu_probe(struct platform_device *pdev)
425 {
426 	struct lgm_clk_provider *ctx;
427 	struct device *dev = &pdev->dev;
428 	struct device_node *np = dev->of_node;
429 	int ret;
430 
431 	ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, CLK_NR_CLKS),
432 			   GFP_KERNEL);
433 	if (!ctx)
434 		return -ENOMEM;
435 
436 	ctx->clk_data.num = CLK_NR_CLKS;
437 
438 	ctx->membase = syscon_node_to_regmap(np);
439 	if (IS_ERR(ctx->membase)) {
440 		dev_err(dev, "Failed to get clk CGU iomem\n");
441 		return PTR_ERR(ctx->membase);
442 	}
443 
444 
445 	ctx->np = np;
446 	ctx->dev = dev;
447 
448 	ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
449 				    ARRAY_SIZE(lgm_pll_clks));
450 	if (ret)
451 		return ret;
452 
453 	ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
454 					ARRAY_SIZE(lgm_branch_clks));
455 	if (ret)
456 		return ret;
457 
458 	ret = lgm_clk_register_ddiv(ctx, lgm_ddiv_clks,
459 				    ARRAY_SIZE(lgm_ddiv_clks));
460 	if (ret)
461 		return ret;
462 
463 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
464 					   &ctx->clk_data);
465 }
466 
467 static const struct of_device_id of_lgm_cgu_match[] = {
468 	{ .compatible = "intel,cgu-lgm" },
469 	{}
470 };
471 
472 static struct platform_driver lgm_cgu_driver = {
473 	.probe = lgm_cgu_probe,
474 	.driver = {
475 		   .name = "cgu-lgm",
476 		   .of_match_table = of_lgm_cgu_match,
477 	},
478 };
479 builtin_platform_driver(lgm_cgu_driver);
480