1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
4 *
5 * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
6 */
7
8 #include <common.h>
9 #include <errno.h>
10 #include <spl.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/omap.h>
14 #include <asm/arch/ddr_defs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/io.h>
20 #include <asm/emif.h>
21 #include <asm/gpio.h>
22 #include <i2c.h>
23 #include <miiphy.h>
24 #include <cpsw.h>
25 #include <fdt_support.h>
26 #include <mtd_node.h>
27 #include <jffs2/load_kernel.h>
28 #include <environment.h>
29 #include "board.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
34 * and control IGEP0034 green and red LEDs.
35 * U-boot configures these pins as input pullup to detect board revision:
36 * IGEP0034-LITE = 0b00
37 * IGEP0034 (FULL) = 0b01
38 * IGEP0033 = 0b1X
39 */
40 #define GPIO_GREEN_REVISION 27
41 #define GPIO_RED_REVISION 26
42
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
44
45 /*
46 * Routine: get_board_revision
47 * Description: Returns the board revision
48 */
get_board_revision(void)49 static int get_board_revision(void)
50 {
51 int revision;
52
53 gpio_request(GPIO_GREEN_REVISION, "green_revision");
54 gpio_direction_input(GPIO_GREEN_REVISION);
55 revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
56 gpio_free(GPIO_GREEN_REVISION);
57
58 gpio_request(GPIO_RED_REVISION, "red_revision");
59 gpio_direction_input(GPIO_RED_REVISION);
60 revision = revision + gpio_get_value(GPIO_RED_REVISION);
61 gpio_free(GPIO_RED_REVISION);
62
63 return revision;
64 }
65
66 #ifdef CONFIG_SPL_BUILD
67 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
68 static const struct ddr_data ddr3_igep0034_data = {
69 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
70 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
71 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
72 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
73 };
74
75 static const struct ddr_data ddr3_igep0034_lite_data = {
76 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
77 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
78 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
79 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
80 };
81
82 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
83 .cmd0csratio = MT41K256M16HA125E_RATIO,
84 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
85
86 .cmd1csratio = MT41K256M16HA125E_RATIO,
87 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
88
89 .cmd2csratio = MT41K256M16HA125E_RATIO,
90 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
91 };
92
93 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
94 .cmd0csratio = K4B2G1646EBIH9_RATIO,
95 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
96
97 .cmd1csratio = K4B2G1646EBIH9_RATIO,
98 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
99
100 .cmd2csratio = K4B2G1646EBIH9_RATIO,
101 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
102 };
103
104 static struct emif_regs ddr3_igep0034_emif_reg_data = {
105 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
106 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
107 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
108 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
109 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
110 .zq_config = MT41K256M16HA125E_ZQ_CFG,
111 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
112 };
113
114 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
115 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
116 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
117 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
118 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
119 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
120 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
121 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
122 };
123
124 const struct ctrl_ioregs ioregs_igep0034 = {
125 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
126 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
127 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
128 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
129 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
130 };
131
132 const struct ctrl_ioregs ioregs_igep0034_lite = {
133 .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
134 .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
135 .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
136 .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
137 .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
138 };
139
140 #define OSC (V_OSCK/1000000)
141 const struct dpll_params dpll_ddr = {
142 400, OSC-1, 1, -1, -1, -1, -1};
143
get_dpll_ddr_params(void)144 const struct dpll_params *get_dpll_ddr_params(void)
145 {
146 return &dpll_ddr;
147 }
148
set_uart_mux_conf(void)149 void set_uart_mux_conf(void)
150 {
151 enable_uart0_pin_mux();
152 }
153
set_mux_conf_regs(void)154 void set_mux_conf_regs(void)
155 {
156 enable_board_pin_mux();
157 }
158
sdram_init(void)159 void sdram_init(void)
160 {
161 if (get_board_revision() == 1)
162 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
163 &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
164 else
165 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
166 &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
167 }
168
169 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)170 int spl_start_uboot(void)
171 {
172 /* break into full u-boot on 'c' */
173 return serial_tstc() && serial_getc() == 'c';
174 }
175 #endif
176 #endif
177
178 /*
179 * Basic board specific setup. Pinmux has been handled already.
180 */
board_init(void)181 int board_init(void)
182 {
183 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
184
185 gpmc_init();
186
187 return 0;
188 }
189
190 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)191 int board_late_init(void)
192 {
193 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
194 switch (get_board_revision()) {
195 case 0:
196 env_set("board_name", "igep0034-lite");
197 break;
198 case 1:
199 env_set("board_name", "igep0034");
200 break;
201 default:
202 env_set("board_name", "igep0033");
203 break;
204 }
205 #endif
206 return 0;
207 }
208 #endif
209
210 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)211 int ft_board_setup(void *blob, bd_t *bd)
212 {
213 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
214 static const struct node_info nodes[] = {
215 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
216 };
217
218 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
219 #endif
220 return 0;
221 }
222 #endif
223
224 #if defined(CONFIG_DRIVER_TI_CPSW)
cpsw_control(int enabled)225 static void cpsw_control(int enabled)
226 {
227 /* VTP can be added here */
228
229 return;
230 }
231
232 static struct cpsw_slave_data cpsw_slaves[] = {
233 {
234 .slave_reg_ofs = 0x208,
235 .sliver_reg_ofs = 0xd80,
236 .phy_addr = 0,
237 .phy_if = PHY_INTERFACE_MODE_RMII,
238 },
239 };
240
241 static struct cpsw_platform_data cpsw_data = {
242 .mdio_base = CPSW_MDIO_BASE,
243 .cpsw_base = CPSW_BASE,
244 .mdio_div = 0xff,
245 .channels = 8,
246 .cpdma_reg_ofs = 0x800,
247 .slaves = 1,
248 .slave_data = cpsw_slaves,
249 .ale_reg_ofs = 0xd00,
250 .ale_entries = 1024,
251 .host_port_reg_ofs = 0x108,
252 .hw_stats_reg_ofs = 0x900,
253 .bd_ram_ofs = 0x2000,
254 .mac_control = (1 << 5),
255 .control = cpsw_control,
256 .host_port_num = 0,
257 .version = CPSW_CTRL_VERSION_2,
258 };
259
board_eth_init(bd_t * bis)260 int board_eth_init(bd_t *bis)
261 {
262 int rv, ret = 0;
263 uint8_t mac_addr[6];
264 uint32_t mac_hi, mac_lo;
265
266 if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
267 /* try reading mac address from efuse */
268 mac_lo = readl(&cdev->macid0l);
269 mac_hi = readl(&cdev->macid0h);
270 mac_addr[0] = mac_hi & 0xFF;
271 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
272 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
273 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
274 mac_addr[4] = mac_lo & 0xFF;
275 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
276 if (is_valid_ethaddr(mac_addr))
277 eth_env_set_enetaddr("ethaddr", mac_addr);
278 }
279
280 writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
281 &cdev->miisel);
282
283 if (get_board_revision() == 1)
284 cpsw_slaves[0].phy_addr = 1;
285
286 rv = cpsw_register(&cpsw_data);
287 if (rv < 0)
288 printf("Error %d registering CPSW switch\n", rv);
289 else
290 ret += rv;
291
292 return ret;
293 }
294 #endif
295