1 // SPDX-License-Identifier: GPL-2.0-or-later
2 #define VERSION "0.23"
3 /* ns83820.c by Benjamin LaHaise with contributions.
4  *
5  * Questions/comments/discussion to linux-ns83820@kvack.org.
6  *
7  * $Revision: 1.34.2.23 $
8  *
9  * Copyright 2001 Benjamin LaHaise.
10  * Copyright 2001, 2002 Red Hat.
11  *
12  * Mmmm, chocolate vanilla mocha...
13  *
14  * ChangeLog
15  * =========
16  *	20010414	0.1 - created
17  *	20010622	0.2 - basic rx and tx.
18  *	20010711	0.3 - added duplex and link state detection support.
19  *	20010713	0.4 - zero copy, no hangs.
20  *			0.5 - 64 bit dma support (davem will hate me for this)
21  *			    - disable jumbo frames to avoid tx hangs
22  *			    - work around tx deadlocks on my 1.02 card via
23  *			      fiddling with TXCFG
24  *	20010810	0.6 - use pci dma api for ringbuffers, work on ia64
25  *	20010816	0.7 - misc cleanups
26  *	20010826	0.8 - fix critical zero copy bugs
27  *			0.9 - internal experiment
28  *	20010827	0.10 - fix ia64 unaligned access.
29  *	20010906	0.11 - accept all packets with checksum errors as
30  *			       otherwise fragments get lost
31  *			     - fix >> 32 bugs
32  *			0.12 - add statistics counters
33  *			     - add allmulti/promisc support
34  *	20011009	0.13 - hotplug support, other smaller pci api cleanups
35  *	20011204	0.13a - optical transceiver support added
36  *				by Michael Clark <michael@metaparadigm.com>
37  *	20011205	0.13b - call register_netdev earlier in initialization
38  *				suppress duplicate link status messages
39  *	20011117 	0.14 - ethtool GDRVINFO, GLINK support from jgarzik
40  *	20011204 	0.15	get ppc (big endian) working
41  *	20011218	0.16	various cleanups
42  *	20020310	0.17	speedups
43  *	20020610	0.18 -	actually use the pci dma api for highmem
44  *			     -	remove pci latency register fiddling
45  *			0.19 -	better bist support
46  *			     -	add ihr and reset_phy parameters
47  *			     -	gmii bus probing
48  *			     -	fix missed txok introduced during performance
49  *				tuning
50  *			0.20 -	fix stupid RFEN thinko.  i am such a smurf.
51  *	20040828	0.21 -	add hardware vlan accleration
52  *				by Neil Horman <nhorman@redhat.com>
53  *	20050406	0.22 -	improved DAC ifdefs from Andi Kleen
54  *			     -	removal of dead code from Adrian Bunk
55  *			     -	fix half duplex collision behaviour
56  * Driver Overview
57  * ===============
58  *
59  * This driver was originally written for the National Semiconductor
60  * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC.  Hopefully
61  * this code will turn out to be a) clean, b) correct, and c) fast.
62  * With that in mind, I'm aiming to split the code up as much as
63  * reasonably possible.  At present there are X major sections that
64  * break down into a) packet receive, b) packet transmit, c) link
65  * management, d) initialization and configuration.  Where possible,
66  * these code paths are designed to run in parallel.
67  *
68  * This driver has been tested and found to work with the following
69  * cards (in no particular order):
70  *
71  *	Cameo		SOHO-GA2000T	SOHO-GA2500T
72  *	D-Link		DGE-500T
73  *	PureData	PDP8023Z-TG
74  *	SMC		SMC9452TX	SMC9462TX
75  *	Netgear		GA621
76  *
77  * Special thanks to SMC for providing hardware to test this driver on.
78  *
79  * Reports of success or failure would be greatly appreciated.
80  */
81 //#define dprintk		printk
82 #define dprintk(x...)		do { } while (0)
83 
84 #include <linux/module.h>
85 #include <linux/moduleparam.h>
86 #include <linux/types.h>
87 #include <linux/pci.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/delay.h>
92 #include <linux/workqueue.h>
93 #include <linux/init.h>
94 #include <linux/interrupt.h>
95 #include <linux/ip.h>	/* for iph */
96 #include <linux/in.h>	/* for IPPROTO_... */
97 #include <linux/compiler.h>
98 #include <linux/prefetch.h>
99 #include <linux/ethtool.h>
100 #include <linux/sched.h>
101 #include <linux/timer.h>
102 #include <linux/if_vlan.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/jiffies.h>
105 #include <linux/slab.h>
106 
107 #include <asm/io.h>
108 #include <linux/uaccess.h>
109 
110 #define DRV_NAME "ns83820"
111 
112 /* Global parameters.  See module_param near the bottom. */
113 static int ihr = 2;
114 static int reset_phy = 0;
115 static int lnksts = 0;		/* CFG_LNKSTS bit polarity */
116 
117 /* Dprintk is used for more interesting debug events */
118 #undef Dprintk
119 #define	Dprintk			dprintk
120 
121 /* tunables */
122 #define RX_BUF_SIZE	1500	/* 8192 */
123 #if IS_ENABLED(CONFIG_VLAN_8021Q)
124 #define NS83820_VLAN_ACCEL_SUPPORT
125 #endif
126 
127 /* Must not exceed ~65000. */
128 #define NR_RX_DESC	64
129 #define NR_TX_DESC	128
130 
131 /* not tunable */
132 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14)	/* rx/tx mac addr + type */
133 
134 #define MIN_TX_DESC_FREE	8
135 
136 /* register defines */
137 #define CFGCS		0x04
138 
139 #define CR_TXE		0x00000001
140 #define CR_TXD		0x00000002
141 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
142  * The Receive engine skips one descriptor and moves
143  * onto the next one!! */
144 #define CR_RXE		0x00000004
145 #define CR_RXD		0x00000008
146 #define CR_TXR		0x00000010
147 #define CR_RXR		0x00000020
148 #define CR_SWI		0x00000080
149 #define CR_RST		0x00000100
150 
151 #define PTSCR_EEBIST_FAIL       0x00000001
152 #define PTSCR_EEBIST_EN         0x00000002
153 #define PTSCR_EELOAD_EN         0x00000004
154 #define PTSCR_RBIST_FAIL        0x000001b8
155 #define PTSCR_RBIST_DONE        0x00000200
156 #define PTSCR_RBIST_EN          0x00000400
157 #define PTSCR_RBIST_RST         0x00002000
158 
159 #define MEAR_EEDI		0x00000001
160 #define MEAR_EEDO		0x00000002
161 #define MEAR_EECLK		0x00000004
162 #define MEAR_EESEL		0x00000008
163 #define MEAR_MDIO		0x00000010
164 #define MEAR_MDDIR		0x00000020
165 #define MEAR_MDC		0x00000040
166 
167 #define ISR_TXDESC3	0x40000000
168 #define ISR_TXDESC2	0x20000000
169 #define ISR_TXDESC1	0x10000000
170 #define ISR_TXDESC0	0x08000000
171 #define ISR_RXDESC3	0x04000000
172 #define ISR_RXDESC2	0x02000000
173 #define ISR_RXDESC1	0x01000000
174 #define ISR_RXDESC0	0x00800000
175 #define ISR_TXRCMP	0x00400000
176 #define ISR_RXRCMP	0x00200000
177 #define ISR_DPERR	0x00100000
178 #define ISR_SSERR	0x00080000
179 #define ISR_RMABT	0x00040000
180 #define ISR_RTABT	0x00020000
181 #define ISR_RXSOVR	0x00010000
182 #define ISR_HIBINT	0x00008000
183 #define ISR_PHY		0x00004000
184 #define ISR_PME		0x00002000
185 #define ISR_SWI		0x00001000
186 #define ISR_MIB		0x00000800
187 #define ISR_TXURN	0x00000400
188 #define ISR_TXIDLE	0x00000200
189 #define ISR_TXERR	0x00000100
190 #define ISR_TXDESC	0x00000080
191 #define ISR_TXOK	0x00000040
192 #define ISR_RXORN	0x00000020
193 #define ISR_RXIDLE	0x00000010
194 #define ISR_RXEARLY	0x00000008
195 #define ISR_RXERR	0x00000004
196 #define ISR_RXDESC	0x00000002
197 #define ISR_RXOK	0x00000001
198 
199 #define TXCFG_CSI	0x80000000
200 #define TXCFG_HBI	0x40000000
201 #define TXCFG_MLB	0x20000000
202 #define TXCFG_ATP	0x10000000
203 #define TXCFG_ECRETRY	0x00800000
204 #define TXCFG_BRST_DIS	0x00080000
205 #define TXCFG_MXDMA1024	0x00000000
206 #define TXCFG_MXDMA512	0x00700000
207 #define TXCFG_MXDMA256	0x00600000
208 #define TXCFG_MXDMA128	0x00500000
209 #define TXCFG_MXDMA64	0x00400000
210 #define TXCFG_MXDMA32	0x00300000
211 #define TXCFG_MXDMA16	0x00200000
212 #define TXCFG_MXDMA8	0x00100000
213 
214 #define CFG_LNKSTS	0x80000000
215 #define CFG_SPDSTS	0x60000000
216 #define CFG_SPDSTS1	0x40000000
217 #define CFG_SPDSTS0	0x20000000
218 #define CFG_DUPSTS	0x10000000
219 #define CFG_TBI_EN	0x01000000
220 #define CFG_MODE_1000	0x00400000
221 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
222  * Read the Phy response and then configure the MAC accordingly */
223 #define CFG_AUTO_1000	0x00200000
224 #define CFG_PINT_CTL	0x001c0000
225 #define CFG_PINT_DUPSTS	0x00100000
226 #define CFG_PINT_LNKSTS	0x00080000
227 #define CFG_PINT_SPDSTS	0x00040000
228 #define CFG_TMRTEST	0x00020000
229 #define CFG_MRM_DIS	0x00010000
230 #define CFG_MWI_DIS	0x00008000
231 #define CFG_T64ADDR	0x00004000
232 #define CFG_PCI64_DET	0x00002000
233 #define CFG_DATA64_EN	0x00001000
234 #define CFG_M64ADDR	0x00000800
235 #define CFG_PHY_RST	0x00000400
236 #define CFG_PHY_DIS	0x00000200
237 #define CFG_EXTSTS_EN	0x00000100
238 #define CFG_REQALG	0x00000080
239 #define CFG_SB		0x00000040
240 #define CFG_POW		0x00000020
241 #define CFG_EXD		0x00000010
242 #define CFG_PESEL	0x00000008
243 #define CFG_BROM_DIS	0x00000004
244 #define CFG_EXT_125	0x00000002
245 #define CFG_BEM		0x00000001
246 
247 #define EXTSTS_UDPPKT	0x00200000
248 #define EXTSTS_TCPPKT	0x00080000
249 #define EXTSTS_IPPKT	0x00020000
250 #define EXTSTS_VPKT	0x00010000
251 #define EXTSTS_VTG_MASK	0x0000ffff
252 
253 #define SPDSTS_POLARITY	(CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
254 
255 #define MIBC_MIBS	0x00000008
256 #define MIBC_ACLR	0x00000004
257 #define MIBC_FRZ	0x00000002
258 #define MIBC_WRN	0x00000001
259 
260 #define PCR_PSEN	(1 << 31)
261 #define PCR_PS_MCAST	(1 << 30)
262 #define PCR_PS_DA	(1 << 29)
263 #define PCR_STHI_8	(3 << 23)
264 #define PCR_STLO_4	(1 << 23)
265 #define PCR_FFHI_8K	(3 << 21)
266 #define PCR_FFLO_4K	(1 << 21)
267 #define PCR_PAUSE_CNT	0xFFFE
268 
269 #define RXCFG_AEP	0x80000000
270 #define RXCFG_ARP	0x40000000
271 #define RXCFG_STRIPCRC	0x20000000
272 #define RXCFG_RX_FD	0x10000000
273 #define RXCFG_ALP	0x08000000
274 #define RXCFG_AIRL	0x04000000
275 #define RXCFG_MXDMA512	0x00700000
276 #define RXCFG_DRTH	0x0000003e
277 #define RXCFG_DRTH0	0x00000002
278 
279 #define RFCR_RFEN	0x80000000
280 #define RFCR_AAB	0x40000000
281 #define RFCR_AAM	0x20000000
282 #define RFCR_AAU	0x10000000
283 #define RFCR_APM	0x08000000
284 #define RFCR_APAT	0x07800000
285 #define RFCR_APAT3	0x04000000
286 #define RFCR_APAT2	0x02000000
287 #define RFCR_APAT1	0x01000000
288 #define RFCR_APAT0	0x00800000
289 #define RFCR_AARP	0x00400000
290 #define RFCR_MHEN	0x00200000
291 #define RFCR_UHEN	0x00100000
292 #define RFCR_ULM	0x00080000
293 
294 #define VRCR_RUDPE	0x00000080
295 #define VRCR_RTCPE	0x00000040
296 #define VRCR_RIPE	0x00000020
297 #define VRCR_IPEN	0x00000010
298 #define VRCR_DUTF	0x00000008
299 #define VRCR_DVTF	0x00000004
300 #define VRCR_VTREN	0x00000002
301 #define VRCR_VTDEN	0x00000001
302 
303 #define VTCR_PPCHK	0x00000008
304 #define VTCR_GCHK	0x00000004
305 #define VTCR_VPPTI	0x00000002
306 #define VTCR_VGTI	0x00000001
307 
308 #define CR		0x00
309 #define CFG		0x04
310 #define MEAR		0x08
311 #define PTSCR		0x0c
312 #define	ISR		0x10
313 #define	IMR		0x14
314 #define	IER		0x18
315 #define	IHR		0x1c
316 #define TXDP		0x20
317 #define TXDP_HI		0x24
318 #define TXCFG		0x28
319 #define GPIOR		0x2c
320 #define RXDP		0x30
321 #define RXDP_HI		0x34
322 #define RXCFG		0x38
323 #define PQCR		0x3c
324 #define WCSR		0x40
325 #define PCR		0x44
326 #define RFCR		0x48
327 #define RFDR		0x4c
328 
329 #define SRR		0x58
330 
331 #define VRCR		0xbc
332 #define VTCR		0xc0
333 #define VDR		0xc4
334 #define CCSR		0xcc
335 
336 #define TBICR		0xe0
337 #define TBISR		0xe4
338 #define TANAR		0xe8
339 #define TANLPAR		0xec
340 #define TANER		0xf0
341 #define TESR		0xf4
342 
343 #define TBICR_MR_AN_ENABLE	0x00001000
344 #define TBICR_MR_RESTART_AN	0x00000200
345 
346 #define TBISR_MR_LINK_STATUS	0x00000020
347 #define TBISR_MR_AN_COMPLETE	0x00000004
348 
349 #define TANAR_PS2 		0x00000100
350 #define TANAR_PS1 		0x00000080
351 #define TANAR_HALF_DUP 		0x00000040
352 #define TANAR_FULL_DUP 		0x00000020
353 
354 #define GPIOR_GP5_OE		0x00000200
355 #define GPIOR_GP4_OE		0x00000100
356 #define GPIOR_GP3_OE		0x00000080
357 #define GPIOR_GP2_OE		0x00000040
358 #define GPIOR_GP1_OE		0x00000020
359 #define GPIOR_GP3_OUT		0x00000004
360 #define GPIOR_GP1_OUT		0x00000001
361 
362 #define LINK_AUTONEGOTIATE	0x01
363 #define LINK_DOWN		0x02
364 #define LINK_UP			0x04
365 
366 #define HW_ADDR_LEN	sizeof(dma_addr_t)
367 #define desc_addr_set(desc, addr)				\
368 	do {							\
369 		((desc)[0] = cpu_to_le32(addr));		\
370 		if (HW_ADDR_LEN == 8)		 		\
371 			(desc)[1] = cpu_to_le32(((u64)addr) >> 32);	\
372 	} while(0)
373 #define desc_addr_get(desc)					\
374 	(le32_to_cpu((desc)[0]) | \
375 	(HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
376 
377 #define DESC_LINK		0
378 #define DESC_BUFPTR		(DESC_LINK + HW_ADDR_LEN/4)
379 #define DESC_CMDSTS		(DESC_BUFPTR + HW_ADDR_LEN/4)
380 #define DESC_EXTSTS		(DESC_CMDSTS + 4/4)
381 
382 #define CMDSTS_OWN	0x80000000
383 #define CMDSTS_MORE	0x40000000
384 #define CMDSTS_INTR	0x20000000
385 #define CMDSTS_ERR	0x10000000
386 #define CMDSTS_OK	0x08000000
387 #define CMDSTS_RUNT	0x00200000
388 #define CMDSTS_LEN_MASK	0x0000ffff
389 
390 #define CMDSTS_DEST_MASK	0x01800000
391 #define CMDSTS_DEST_SELF	0x00800000
392 #define CMDSTS_DEST_MULTI	0x01000000
393 
394 #define DESC_SIZE	8		/* Should be cache line sized */
395 
396 struct rx_info {
397 	spinlock_t	lock;
398 	int		up;
399 	unsigned long	idle;
400 
401 	struct sk_buff	*skbs[NR_RX_DESC];
402 
403 	__le32		*next_rx_desc;
404 	u16		next_rx, next_empty;
405 
406 	__le32		*descs;
407 	dma_addr_t	phy_descs;
408 };
409 
410 
411 struct ns83820 {
412 	u8			__iomem *base;
413 
414 	struct pci_dev		*pci_dev;
415 	struct net_device	*ndev;
416 
417 	struct rx_info		rx_info;
418 	struct tasklet_struct	rx_tasklet;
419 
420 	unsigned		ihr;
421 	struct work_struct	tq_refill;
422 
423 	/* protects everything below.  irqsave when using. */
424 	spinlock_t		misc_lock;
425 
426 	u32			CFG_cache;
427 
428 	u32			MEAR_cache;
429 	u32			IMR_cache;
430 
431 	unsigned		linkstate;
432 
433 	spinlock_t	tx_lock;
434 
435 	u16		tx_done_idx;
436 	u16		tx_idx;
437 	volatile u16	tx_free_idx;	/* idx of free desc chain */
438 	u16		tx_intr_idx;
439 
440 	atomic_t	nr_tx_skbs;
441 	struct sk_buff	*tx_skbs[NR_TX_DESC];
442 
443 	char		pad[16] __attribute__((aligned(16)));
444 	__le32		*tx_descs;
445 	dma_addr_t	tx_phy_descs;
446 
447 	struct timer_list	tx_watchdog;
448 };
449 
PRIV(struct net_device * dev)450 static inline struct ns83820 *PRIV(struct net_device *dev)
451 {
452 	return netdev_priv(dev);
453 }
454 
455 #define __kick_rx(dev)	writel(CR_RXE, dev->base + CR)
456 
kick_rx(struct net_device * ndev)457 static inline void kick_rx(struct net_device *ndev)
458 {
459 	struct ns83820 *dev = PRIV(ndev);
460 	dprintk("kick_rx: maybe kicking\n");
461 	if (test_and_clear_bit(0, &dev->rx_info.idle)) {
462 		dprintk("actually kicking\n");
463 		writel(dev->rx_info.phy_descs +
464 			(4 * DESC_SIZE * dev->rx_info.next_rx),
465 		       dev->base + RXDP);
466 		if (dev->rx_info.next_rx == dev->rx_info.next_empty)
467 			printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
468 				ndev->name);
469 		__kick_rx(dev);
470 	}
471 }
472 
473 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
474 #define start_tx_okay(dev)	\
475 	(((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
476 
477 /* Packet Receiver
478  *
479  * The hardware supports linked lists of receive descriptors for
480  * which ownership is transferred back and forth by means of an
481  * ownership bit.  While the hardware does support the use of a
482  * ring for receive descriptors, we only make use of a chain in
483  * an attempt to reduce bus traffic under heavy load scenarios.
484  * This will also make bugs a bit more obvious.  The current code
485  * only makes use of a single rx chain; I hope to implement
486  * priority based rx for version 1.0.  Goal: even under overload
487  * conditions, still route realtime traffic with as low jitter as
488  * possible.
489  */
build_rx_desc(struct ns83820 * dev,__le32 * desc,dma_addr_t link,dma_addr_t buf,u32 cmdsts,u32 extsts)490 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
491 {
492 	desc_addr_set(desc + DESC_LINK, link);
493 	desc_addr_set(desc + DESC_BUFPTR, buf);
494 	desc[DESC_EXTSTS] = cpu_to_le32(extsts);
495 	mb();
496 	desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
497 }
498 
499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
ns83820_add_rx_skb(struct ns83820 * dev,struct sk_buff * skb)500 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
501 {
502 	unsigned next_empty;
503 	u32 cmdsts;
504 	__le32 *sg;
505 	dma_addr_t buf;
506 
507 	next_empty = dev->rx_info.next_empty;
508 
509 	/* don't overrun last rx marker */
510 	if (unlikely(nr_rx_empty(dev) <= 2)) {
511 		kfree_skb(skb);
512 		return 1;
513 	}
514 
515 #if 0
516 	dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
517 		dev->rx_info.next_empty,
518 		dev->rx_info.nr_used,
519 		dev->rx_info.next_rx
520 		);
521 #endif
522 
523 	sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
524 	BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
525 	dev->rx_info.skbs[next_empty] = skb;
526 
527 	dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
528 	cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
529 	buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE,
530 			     DMA_FROM_DEVICE);
531 	build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
532 	/* update link of previous rx */
533 	if (likely(next_empty != dev->rx_info.next_rx))
534 		dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
535 
536 	return 0;
537 }
538 
rx_refill(struct net_device * ndev,gfp_t gfp)539 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
540 {
541 	struct ns83820 *dev = PRIV(ndev);
542 	unsigned i;
543 	unsigned long flags = 0;
544 
545 	if (unlikely(nr_rx_empty(dev) <= 2))
546 		return 0;
547 
548 	dprintk("rx_refill(%p)\n", ndev);
549 	if (gfp == GFP_ATOMIC)
550 		spin_lock_irqsave(&dev->rx_info.lock, flags);
551 	for (i=0; i<NR_RX_DESC; i++) {
552 		struct sk_buff *skb;
553 		long res;
554 
555 		/* extra 16 bytes for alignment */
556 		skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
557 		if (unlikely(!skb))
558 			break;
559 
560 		skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
561 		if (gfp != GFP_ATOMIC)
562 			spin_lock_irqsave(&dev->rx_info.lock, flags);
563 		res = ns83820_add_rx_skb(dev, skb);
564 		if (gfp != GFP_ATOMIC)
565 			spin_unlock_irqrestore(&dev->rx_info.lock, flags);
566 		if (res) {
567 			i = 1;
568 			break;
569 		}
570 	}
571 	if (gfp == GFP_ATOMIC)
572 		spin_unlock_irqrestore(&dev->rx_info.lock, flags);
573 
574 	return i ? 0 : -ENOMEM;
575 }
576 
rx_refill_atomic(struct net_device * ndev)577 static void rx_refill_atomic(struct net_device *ndev)
578 {
579 	rx_refill(ndev, GFP_ATOMIC);
580 }
581 
582 /* REFILL */
queue_refill(struct work_struct * work)583 static inline void queue_refill(struct work_struct *work)
584 {
585 	struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
586 	struct net_device *ndev = dev->ndev;
587 
588 	rx_refill(ndev, GFP_KERNEL);
589 	if (dev->rx_info.up)
590 		kick_rx(ndev);
591 }
592 
clear_rx_desc(struct ns83820 * dev,unsigned i)593 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
594 {
595 	build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
596 }
597 
phy_intr(struct net_device * ndev)598 static void phy_intr(struct net_device *ndev)
599 {
600 	struct ns83820 *dev = PRIV(ndev);
601 	static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
602 	u32 cfg, new_cfg;
603 	u32 tanar, tanlpar;
604 	int speed, fullduplex, newlinkstate;
605 
606 	cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
607 
608 	if (dev->CFG_cache & CFG_TBI_EN) {
609 		u32 __maybe_unused tbisr;
610 
611 		/* we have an optical transceiver */
612 		tbisr = readl(dev->base + TBISR);
613 		tanar = readl(dev->base + TANAR);
614 		tanlpar = readl(dev->base + TANLPAR);
615 		dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
616 			tbisr, tanar, tanlpar);
617 
618 		if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
619 		      (tanar & TANAR_FULL_DUP)) ) {
620 
621 			/* both of us are full duplex */
622 			writel(readl(dev->base + TXCFG)
623 			       | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
624 			       dev->base + TXCFG);
625 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
626 			       dev->base + RXCFG);
627 			/* Light up full duplex LED */
628 			writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
629 			       dev->base + GPIOR);
630 
631 		} else if (((tanlpar & TANAR_HALF_DUP) &&
632 			    (tanar & TANAR_HALF_DUP)) ||
633 			   ((tanlpar & TANAR_FULL_DUP) &&
634 			    (tanar & TANAR_HALF_DUP)) ||
635 			   ((tanlpar & TANAR_HALF_DUP) &&
636 			    (tanar & TANAR_FULL_DUP))) {
637 
638 			/* one or both of us are half duplex */
639 			writel((readl(dev->base + TXCFG)
640 				& ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
641 			       dev->base + TXCFG);
642 			writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
643 			       dev->base + RXCFG);
644 			/* Turn off full duplex LED */
645 			writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
646 			       dev->base + GPIOR);
647 		}
648 
649 		speed = 4; /* 1000F */
650 
651 	} else {
652 		/* we have a copper transceiver */
653 		new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
654 
655 		if (cfg & CFG_SPDSTS1)
656 			new_cfg |= CFG_MODE_1000;
657 		else
658 			new_cfg &= ~CFG_MODE_1000;
659 
660 		speed = ((cfg / CFG_SPDSTS0) & 3);
661 		fullduplex = (cfg & CFG_DUPSTS);
662 
663 		if (fullduplex) {
664 			new_cfg |= CFG_SB;
665 			writel(readl(dev->base + TXCFG)
666 					| TXCFG_CSI | TXCFG_HBI,
667 			       dev->base + TXCFG);
668 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
669 			       dev->base + RXCFG);
670 		} else {
671 			writel(readl(dev->base + TXCFG)
672 					& ~(TXCFG_CSI | TXCFG_HBI),
673 			       dev->base + TXCFG);
674 			writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
675 			       dev->base + RXCFG);
676 		}
677 
678 		if ((cfg & CFG_LNKSTS) &&
679 		    ((new_cfg ^ dev->CFG_cache) != 0)) {
680 			writel(new_cfg, dev->base + CFG);
681 			dev->CFG_cache = new_cfg;
682 		}
683 
684 		dev->CFG_cache &= ~CFG_SPDSTS;
685 		dev->CFG_cache |= cfg & CFG_SPDSTS;
686 	}
687 
688 	newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
689 
690 	if (newlinkstate & LINK_UP &&
691 	    dev->linkstate != newlinkstate) {
692 		netif_start_queue(ndev);
693 		netif_wake_queue(ndev);
694 		printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
695 			ndev->name,
696 			speeds[speed],
697 			fullduplex ? "full" : "half");
698 	} else if (newlinkstate & LINK_DOWN &&
699 		   dev->linkstate != newlinkstate) {
700 		netif_stop_queue(ndev);
701 		printk(KERN_INFO "%s: link now down.\n", ndev->name);
702 	}
703 
704 	dev->linkstate = newlinkstate;
705 }
706 
ns83820_setup_rx(struct net_device * ndev)707 static int ns83820_setup_rx(struct net_device *ndev)
708 {
709 	struct ns83820 *dev = PRIV(ndev);
710 	unsigned i;
711 	int ret;
712 
713 	dprintk("ns83820_setup_rx(%p)\n", ndev);
714 
715 	dev->rx_info.idle = 1;
716 	dev->rx_info.next_rx = 0;
717 	dev->rx_info.next_rx_desc = dev->rx_info.descs;
718 	dev->rx_info.next_empty = 0;
719 
720 	for (i=0; i<NR_RX_DESC; i++)
721 		clear_rx_desc(dev, i);
722 
723 	writel(0, dev->base + RXDP_HI);
724 	writel(dev->rx_info.phy_descs, dev->base + RXDP);
725 
726 	ret = rx_refill(ndev, GFP_KERNEL);
727 	if (!ret) {
728 		dprintk("starting receiver\n");
729 		/* prevent the interrupt handler from stomping on us */
730 		spin_lock_irq(&dev->rx_info.lock);
731 
732 		writel(0x0001, dev->base + CCSR);
733 		writel(0, dev->base + RFCR);
734 		writel(0x7fc00000, dev->base + RFCR);
735 		writel(0xffc00000, dev->base + RFCR);
736 
737 		dev->rx_info.up = 1;
738 
739 		phy_intr(ndev);
740 
741 		/* Okay, let it rip */
742 		spin_lock(&dev->misc_lock);
743 		dev->IMR_cache |= ISR_PHY;
744 		dev->IMR_cache |= ISR_RXRCMP;
745 		//dev->IMR_cache |= ISR_RXERR;
746 		//dev->IMR_cache |= ISR_RXOK;
747 		dev->IMR_cache |= ISR_RXORN;
748 		dev->IMR_cache |= ISR_RXSOVR;
749 		dev->IMR_cache |= ISR_RXDESC;
750 		dev->IMR_cache |= ISR_RXIDLE;
751 		dev->IMR_cache |= ISR_TXDESC;
752 		dev->IMR_cache |= ISR_TXIDLE;
753 
754 		writel(dev->IMR_cache, dev->base + IMR);
755 		writel(1, dev->base + IER);
756 		spin_unlock(&dev->misc_lock);
757 
758 		kick_rx(ndev);
759 
760 		spin_unlock_irq(&dev->rx_info.lock);
761 	}
762 	return ret;
763 }
764 
ns83820_cleanup_rx(struct ns83820 * dev)765 static void ns83820_cleanup_rx(struct ns83820 *dev)
766 {
767 	unsigned i;
768 	unsigned long flags;
769 
770 	dprintk("ns83820_cleanup_rx(%p)\n", dev);
771 
772 	/* disable receive interrupts */
773 	spin_lock_irqsave(&dev->misc_lock, flags);
774 	dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
775 	writel(dev->IMR_cache, dev->base + IMR);
776 	spin_unlock_irqrestore(&dev->misc_lock, flags);
777 
778 	/* synchronize with the interrupt handler and kill it */
779 	dev->rx_info.up = 0;
780 	synchronize_irq(dev->pci_dev->irq);
781 
782 	/* touch the pci bus... */
783 	readl(dev->base + IMR);
784 
785 	/* assumes the transmitter is already disabled and reset */
786 	writel(0, dev->base + RXDP_HI);
787 	writel(0, dev->base + RXDP);
788 
789 	for (i=0; i<NR_RX_DESC; i++) {
790 		struct sk_buff *skb = dev->rx_info.skbs[i];
791 		dev->rx_info.skbs[i] = NULL;
792 		clear_rx_desc(dev, i);
793 		kfree_skb(skb);
794 	}
795 }
796 
ns83820_rx_kick(struct net_device * ndev)797 static void ns83820_rx_kick(struct net_device *ndev)
798 {
799 	struct ns83820 *dev = PRIV(ndev);
800 	/*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
801 		if (dev->rx_info.up) {
802 			rx_refill_atomic(ndev);
803 			kick_rx(ndev);
804 		}
805 	}
806 
807 	if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
808 		schedule_work(&dev->tq_refill);
809 	else
810 		kick_rx(ndev);
811 	if (dev->rx_info.idle)
812 		printk(KERN_DEBUG "%s: BAD\n", ndev->name);
813 }
814 
815 /* rx_irq
816  *
817  */
rx_irq(struct net_device * ndev)818 static void rx_irq(struct net_device *ndev)
819 {
820 	struct ns83820 *dev = PRIV(ndev);
821 	struct rx_info *info = &dev->rx_info;
822 	unsigned next_rx;
823 	int rx_rc, len;
824 	u32 cmdsts;
825 	__le32 *desc;
826 	unsigned long flags;
827 	int nr = 0;
828 
829 	dprintk("rx_irq(%p)\n", ndev);
830 	dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
831 		readl(dev->base + RXDP),
832 		(long)(dev->rx_info.phy_descs),
833 		(int)dev->rx_info.next_rx,
834 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
835 		(int)dev->rx_info.next_empty,
836 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
837 		);
838 
839 	spin_lock_irqsave(&info->lock, flags);
840 	if (!info->up)
841 		goto out;
842 
843 	dprintk("walking descs\n");
844 	next_rx = info->next_rx;
845 	desc = info->next_rx_desc;
846 	while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
847 	       (cmdsts != CMDSTS_OWN)) {
848 		struct sk_buff *skb;
849 		u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
850 		dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
851 
852 		dprintk("cmdsts: %08x\n", cmdsts);
853 		dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
854 		dprintk("extsts: %08x\n", extsts);
855 
856 		skb = info->skbs[next_rx];
857 		info->skbs[next_rx] = NULL;
858 		info->next_rx = (next_rx + 1) % NR_RX_DESC;
859 
860 		mb();
861 		clear_rx_desc(dev, next_rx);
862 
863 		dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
864 				 DMA_FROM_DEVICE);
865 		len = cmdsts & CMDSTS_LEN_MASK;
866 #ifdef NS83820_VLAN_ACCEL_SUPPORT
867 		/* NH: As was mentioned below, this chip is kinda
868 		 * brain dead about vlan tag stripping.  Frames
869 		 * that are 64 bytes with a vlan header appended
870 		 * like arp frames, or pings, are flagged as Runts
871 		 * when the tag is stripped and hardware.  This
872 		 * also means that the OK bit in the descriptor
873 		 * is cleared when the frame comes in so we have
874 		 * to do a specific length check here to make sure
875 		 * the frame would have been ok, had we not stripped
876 		 * the tag.
877 		 */
878 		if (likely((CMDSTS_OK & cmdsts) ||
879 			((cmdsts & CMDSTS_RUNT) && len >= 56))) {
880 #else
881 		if (likely(CMDSTS_OK & cmdsts)) {
882 #endif
883 			skb_put(skb, len);
884 			if (unlikely(!skb))
885 				goto netdev_mangle_me_harder_failed;
886 			if (cmdsts & CMDSTS_DEST_MULTI)
887 				ndev->stats.multicast++;
888 			ndev->stats.rx_packets++;
889 			ndev->stats.rx_bytes += len;
890 			if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
891 				skb->ip_summed = CHECKSUM_UNNECESSARY;
892 			} else {
893 				skb_checksum_none_assert(skb);
894 			}
895 			skb->protocol = eth_type_trans(skb, ndev);
896 #ifdef NS83820_VLAN_ACCEL_SUPPORT
897 			if(extsts & EXTSTS_VPKT) {
898 				unsigned short tag;
899 
900 				tag = ntohs(extsts & EXTSTS_VTG_MASK);
901 				__vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
902 			}
903 #endif
904 			rx_rc = netif_rx(skb);
905 			if (NET_RX_DROP == rx_rc) {
906 netdev_mangle_me_harder_failed:
907 				ndev->stats.rx_dropped++;
908 			}
909 		} else {
910 			dev_kfree_skb_irq(skb);
911 		}
912 
913 		nr++;
914 		next_rx = info->next_rx;
915 		desc = info->descs + (DESC_SIZE * next_rx);
916 	}
917 	info->next_rx = next_rx;
918 	info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
919 
920 out:
921 	if (0 && !nr) {
922 		Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
923 	}
924 
925 	spin_unlock_irqrestore(&info->lock, flags);
926 }
927 
928 static void rx_action(struct tasklet_struct *t)
929 {
930 	struct ns83820 *dev = from_tasklet(dev, t, rx_tasklet);
931 	struct net_device *ndev = dev->ndev;
932 	rx_irq(ndev);
933 	writel(ihr, dev->base + IHR);
934 
935 	spin_lock_irq(&dev->misc_lock);
936 	dev->IMR_cache |= ISR_RXDESC;
937 	writel(dev->IMR_cache, dev->base + IMR);
938 	spin_unlock_irq(&dev->misc_lock);
939 
940 	rx_irq(ndev);
941 	ns83820_rx_kick(ndev);
942 }
943 
944 /* Packet Transmit code
945  */
946 static inline void kick_tx(struct ns83820 *dev)
947 {
948 	dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
949 		dev, dev->tx_idx, dev->tx_free_idx);
950 	writel(CR_TXE, dev->base + CR);
951 }
952 
953 /* No spinlock needed on the transmit irq path as the interrupt handler is
954  * serialized.
955  */
956 static void do_tx_done(struct net_device *ndev)
957 {
958 	struct ns83820 *dev = PRIV(ndev);
959 	u32 cmdsts, tx_done_idx;
960 	__le32 *desc;
961 
962 	dprintk("do_tx_done(%p)\n", ndev);
963 	tx_done_idx = dev->tx_done_idx;
964 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
965 
966 	dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
967 		tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
968 	while ((tx_done_idx != dev->tx_free_idx) &&
969 	       !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
970 		struct sk_buff *skb;
971 		unsigned len;
972 		dma_addr_t addr;
973 
974 		if (cmdsts & CMDSTS_ERR)
975 			ndev->stats.tx_errors++;
976 		if (cmdsts & CMDSTS_OK)
977 			ndev->stats.tx_packets++;
978 		if (cmdsts & CMDSTS_OK)
979 			ndev->stats.tx_bytes += cmdsts & 0xffff;
980 
981 		dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
982 			tx_done_idx, dev->tx_free_idx, cmdsts);
983 		skb = dev->tx_skbs[tx_done_idx];
984 		dev->tx_skbs[tx_done_idx] = NULL;
985 		dprintk("done(%p)\n", skb);
986 
987 		len = cmdsts & CMDSTS_LEN_MASK;
988 		addr = desc_addr_get(desc + DESC_BUFPTR);
989 		if (skb) {
990 			dma_unmap_single(&dev->pci_dev->dev, addr, len,
991 					 DMA_TO_DEVICE);
992 			dev_consume_skb_irq(skb);
993 			atomic_dec(&dev->nr_tx_skbs);
994 		} else
995 			dma_unmap_page(&dev->pci_dev->dev, addr, len,
996 				       DMA_TO_DEVICE);
997 
998 		tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
999 		dev->tx_done_idx = tx_done_idx;
1000 		desc[DESC_CMDSTS] = cpu_to_le32(0);
1001 		mb();
1002 		desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1003 	}
1004 
1005 	/* Allow network stack to resume queueing packets after we've
1006 	 * finished transmitting at least 1/4 of the packets in the queue.
1007 	 */
1008 	if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1009 		dprintk("start_queue(%p)\n", ndev);
1010 		netif_start_queue(ndev);
1011 		netif_wake_queue(ndev);
1012 	}
1013 }
1014 
1015 static void ns83820_cleanup_tx(struct ns83820 *dev)
1016 {
1017 	unsigned i;
1018 
1019 	for (i=0; i<NR_TX_DESC; i++) {
1020 		struct sk_buff *skb = dev->tx_skbs[i];
1021 		dev->tx_skbs[i] = NULL;
1022 		if (skb) {
1023 			__le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1024 			dma_unmap_single(&dev->pci_dev->dev,
1025 					 desc_addr_get(desc + DESC_BUFPTR),
1026 					 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1027 					 DMA_TO_DEVICE);
1028 			dev_kfree_skb_irq(skb);
1029 			atomic_dec(&dev->nr_tx_skbs);
1030 		}
1031 	}
1032 
1033 	memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1034 }
1035 
1036 /* transmit routine.  This code relies on the network layer serializing
1037  * its calls in, but will run happily in parallel with the interrupt
1038  * handler.  This code currently has provisions for fragmenting tx buffers
1039  * while trying to track down a bug in either the zero copy code or
1040  * the tx fifo (hence the MAX_FRAG_LEN).
1041  */
1042 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1043 					   struct net_device *ndev)
1044 {
1045 	struct ns83820 *dev = PRIV(ndev);
1046 	u32 free_idx, cmdsts, extsts;
1047 	int nr_free, nr_frags;
1048 	unsigned tx_done_idx, last_idx;
1049 	dma_addr_t buf;
1050 	unsigned len;
1051 	skb_frag_t *frag;
1052 	int stopped = 0;
1053 	int do_intr = 0;
1054 	volatile __le32 *first_desc;
1055 
1056 	dprintk("ns83820_hard_start_xmit\n");
1057 
1058 	nr_frags =  skb_shinfo(skb)->nr_frags;
1059 again:
1060 	if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1061 		netif_stop_queue(ndev);
1062 		if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1063 			return NETDEV_TX_BUSY;
1064 		netif_start_queue(ndev);
1065 	}
1066 
1067 	last_idx = free_idx = dev->tx_free_idx;
1068 	tx_done_idx = dev->tx_done_idx;
1069 	nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1070 	nr_free -= 1;
1071 	if (nr_free <= nr_frags) {
1072 		dprintk("stop_queue - not enough(%p)\n", ndev);
1073 		netif_stop_queue(ndev);
1074 
1075 		/* Check again: we may have raced with a tx done irq */
1076 		if (dev->tx_done_idx != tx_done_idx) {
1077 			dprintk("restart queue(%p)\n", ndev);
1078 			netif_start_queue(ndev);
1079 			goto again;
1080 		}
1081 		return NETDEV_TX_BUSY;
1082 	}
1083 
1084 	if (free_idx == dev->tx_intr_idx) {
1085 		do_intr = 1;
1086 		dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1087 	}
1088 
1089 	nr_free -= nr_frags;
1090 	if (nr_free < MIN_TX_DESC_FREE) {
1091 		dprintk("stop_queue - last entry(%p)\n", ndev);
1092 		netif_stop_queue(ndev);
1093 		stopped = 1;
1094 	}
1095 
1096 	frag = skb_shinfo(skb)->frags;
1097 	if (!nr_frags)
1098 		frag = NULL;
1099 	extsts = 0;
1100 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
1101 		extsts |= EXTSTS_IPPKT;
1102 		if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1103 			extsts |= EXTSTS_TCPPKT;
1104 		else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1105 			extsts |= EXTSTS_UDPPKT;
1106 	}
1107 
1108 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1109 	if (skb_vlan_tag_present(skb)) {
1110 		/* fetch the vlan tag info out of the
1111 		 * ancillary data if the vlan code
1112 		 * is using hw vlan acceleration
1113 		 */
1114 		short tag = skb_vlan_tag_get(skb);
1115 		extsts |= (EXTSTS_VPKT | htons(tag));
1116 	}
1117 #endif
1118 
1119 	len = skb->len;
1120 	if (nr_frags)
1121 		len -= skb->data_len;
1122 	buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
1123 			     DMA_TO_DEVICE);
1124 
1125 	first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1126 
1127 	for (;;) {
1128 		volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1129 
1130 		dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1131 			(unsigned long long)buf);
1132 		last_idx = free_idx;
1133 		free_idx = (free_idx + 1) % NR_TX_DESC;
1134 		desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1135 		desc_addr_set(desc + DESC_BUFPTR, buf);
1136 		desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1137 
1138 		cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1139 		cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1140 		cmdsts |= len;
1141 		desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1142 
1143 		if (!nr_frags)
1144 			break;
1145 
1146 		buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1147 				       skb_frag_size(frag), DMA_TO_DEVICE);
1148 		dprintk("frag: buf=%08Lx  page=%08lx offset=%08lx\n",
1149 			(long long)buf, (long) page_to_pfn(frag->page),
1150 			frag->page_offset);
1151 		len = skb_frag_size(frag);
1152 		frag++;
1153 		nr_frags--;
1154 	}
1155 	dprintk("done pkt\n");
1156 
1157 	spin_lock_irq(&dev->tx_lock);
1158 	dev->tx_skbs[last_idx] = skb;
1159 	first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1160 	dev->tx_free_idx = free_idx;
1161 	atomic_inc(&dev->nr_tx_skbs);
1162 	spin_unlock_irq(&dev->tx_lock);
1163 
1164 	kick_tx(dev);
1165 
1166 	/* Check again: we may have raced with a tx done irq */
1167 	if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1168 		netif_start_queue(ndev);
1169 
1170 	return NETDEV_TX_OK;
1171 }
1172 
1173 static void ns83820_update_stats(struct ns83820 *dev)
1174 {
1175 	struct net_device *ndev = dev->ndev;
1176 	u8 __iomem *base = dev->base;
1177 
1178 	/* the DP83820 will freeze counters, so we need to read all of them */
1179 	ndev->stats.rx_errors		+= readl(base + 0x60) & 0xffff;
1180 	ndev->stats.rx_crc_errors	+= readl(base + 0x64) & 0xffff;
1181 	ndev->stats.rx_missed_errors	+= readl(base + 0x68) & 0xffff;
1182 	ndev->stats.rx_frame_errors	+= readl(base + 0x6c) & 0xffff;
1183 	/*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1184 	ndev->stats.rx_length_errors	+= readl(base + 0x74) & 0xffff;
1185 	ndev->stats.rx_length_errors	+= readl(base + 0x78) & 0xffff;
1186 	/*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1187 	/*ndev->stats.rx_pause_count += */  readl(base + 0x80);
1188 	/*ndev->stats.tx_pause_count += */  readl(base + 0x84);
1189 	ndev->stats.tx_carrier_errors	+= readl(base + 0x88) & 0xff;
1190 }
1191 
1192 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1193 {
1194 	struct ns83820 *dev = PRIV(ndev);
1195 
1196 	/* somewhat overkill */
1197 	spin_lock_irq(&dev->misc_lock);
1198 	ns83820_update_stats(dev);
1199 	spin_unlock_irq(&dev->misc_lock);
1200 
1201 	return &ndev->stats;
1202 }
1203 
1204 /* Let ethtool retrieve info */
1205 static int ns83820_get_link_ksettings(struct net_device *ndev,
1206 				      struct ethtool_link_ksettings *cmd)
1207 {
1208 	struct ns83820 *dev = PRIV(ndev);
1209 	u32 cfg, tbicr;
1210 	int fullduplex   = 0;
1211 	u32 supported;
1212 
1213 	/*
1214 	 * Here's the list of available ethtool commands from other drivers:
1215 	 *	cmd->advertising =
1216 	 *	ethtool_cmd_speed_set(cmd, ...)
1217 	 *	cmd->duplex =
1218 	 *	cmd->port = 0;
1219 	 *	cmd->phy_address =
1220 	 *	cmd->transceiver = 0;
1221 	 *	cmd->autoneg =
1222 	 *	cmd->maxtxpkt = 0;
1223 	 *	cmd->maxrxpkt = 0;
1224 	 */
1225 
1226 	/* read current configuration */
1227 	cfg   = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1228 	readl(dev->base + TANAR);
1229 	tbicr = readl(dev->base + TBICR);
1230 
1231 	fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1232 
1233 	supported = SUPPORTED_Autoneg;
1234 
1235 	if (dev->CFG_cache & CFG_TBI_EN) {
1236 		/* we have optical interface */
1237 		supported |= SUPPORTED_1000baseT_Half |
1238 					SUPPORTED_1000baseT_Full |
1239 					SUPPORTED_FIBRE;
1240 		cmd->base.port       = PORT_FIBRE;
1241 	} else {
1242 		/* we have copper */
1243 		supported |= SUPPORTED_10baseT_Half |
1244 			SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1245 			SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1246 			SUPPORTED_1000baseT_Full |
1247 			SUPPORTED_MII;
1248 		cmd->base.port = PORT_MII;
1249 	}
1250 
1251 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1252 						supported);
1253 
1254 	cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1255 	switch (cfg / CFG_SPDSTS0 & 3) {
1256 	case 2:
1257 		cmd->base.speed = SPEED_1000;
1258 		break;
1259 	case 1:
1260 		cmd->base.speed = SPEED_100;
1261 		break;
1262 	default:
1263 		cmd->base.speed = SPEED_10;
1264 		break;
1265 	}
1266 	cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1267 		? AUTONEG_ENABLE : AUTONEG_DISABLE;
1268 	return 0;
1269 }
1270 
1271 /* Let ethool change settings*/
1272 static int ns83820_set_link_ksettings(struct net_device *ndev,
1273 				      const struct ethtool_link_ksettings *cmd)
1274 {
1275 	struct ns83820 *dev = PRIV(ndev);
1276 	u32 cfg, tanar;
1277 	int have_optical = 0;
1278 	int fullduplex   = 0;
1279 
1280 	/* read current configuration */
1281 	cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1282 	tanar = readl(dev->base + TANAR);
1283 
1284 	if (dev->CFG_cache & CFG_TBI_EN) {
1285 		/* we have optical */
1286 		have_optical = 1;
1287 		fullduplex   = (tanar & TANAR_FULL_DUP);
1288 
1289 	} else {
1290 		/* we have copper */
1291 		fullduplex = cfg & CFG_DUPSTS;
1292 	}
1293 
1294 	spin_lock_irq(&dev->misc_lock);
1295 	spin_lock(&dev->tx_lock);
1296 
1297 	/* Set duplex */
1298 	if (cmd->base.duplex != fullduplex) {
1299 		if (have_optical) {
1300 			/*set full duplex*/
1301 			if (cmd->base.duplex == DUPLEX_FULL) {
1302 				/* force full duplex */
1303 				writel(readl(dev->base + TXCFG)
1304 					| TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1305 					dev->base + TXCFG);
1306 				writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1307 					dev->base + RXCFG);
1308 				/* Light up full duplex LED */
1309 				writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1310 					dev->base + GPIOR);
1311 			} else {
1312 				/*TODO: set half duplex */
1313 			}
1314 
1315 		} else {
1316 			/*we have copper*/
1317 			/* TODO: Set duplex for copper cards */
1318 		}
1319 		printk(KERN_INFO "%s: Duplex set via ethtool\n",
1320 		ndev->name);
1321 	}
1322 
1323 	/* Set autonegotiation */
1324 	if (1) {
1325 		if (cmd->base.autoneg == AUTONEG_ENABLE) {
1326 			/* restart auto negotiation */
1327 			writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1328 				dev->base + TBICR);
1329 			writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1330 				dev->linkstate = LINK_AUTONEGOTIATE;
1331 
1332 			printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1333 				ndev->name);
1334 		} else {
1335 			/* disable auto negotiation */
1336 			writel(0x00000000, dev->base + TBICR);
1337 		}
1338 
1339 		printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1340 				cmd->base.autoneg ? "ENABLED" : "DISABLED");
1341 	}
1342 
1343 	phy_intr(ndev);
1344 	spin_unlock(&dev->tx_lock);
1345 	spin_unlock_irq(&dev->misc_lock);
1346 
1347 	return 0;
1348 }
1349 /* end ethtool get/set support -df */
1350 
1351 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1352 {
1353 	struct ns83820 *dev = PRIV(ndev);
1354 	strscpy(info->driver, "ns83820", sizeof(info->driver));
1355 	strscpy(info->version, VERSION, sizeof(info->version));
1356 	strscpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1357 }
1358 
1359 static u32 ns83820_get_link(struct net_device *ndev)
1360 {
1361 	struct ns83820 *dev = PRIV(ndev);
1362 	u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1363 	return cfg & CFG_LNKSTS ? 1 : 0;
1364 }
1365 
1366 static const struct ethtool_ops ops = {
1367 	.get_drvinfo     = ns83820_get_drvinfo,
1368 	.get_link        = ns83820_get_link,
1369 	.get_link_ksettings = ns83820_get_link_ksettings,
1370 	.set_link_ksettings = ns83820_set_link_ksettings,
1371 };
1372 
1373 static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1374 {
1375 	writel(0, dev->base + IMR);
1376 	writel(0, dev->base + IER);
1377 	readl(dev->base + IER);
1378 }
1379 
1380 /* this function is called in irq context from the ISR */
1381 static void ns83820_mib_isr(struct ns83820 *dev)
1382 {
1383 	unsigned long flags;
1384 	spin_lock_irqsave(&dev->misc_lock, flags);
1385 	ns83820_update_stats(dev);
1386 	spin_unlock_irqrestore(&dev->misc_lock, flags);
1387 }
1388 
1389 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1390 static irqreturn_t ns83820_irq(int foo, void *data)
1391 {
1392 	struct net_device *ndev = data;
1393 	struct ns83820 *dev = PRIV(ndev);
1394 	u32 isr;
1395 	dprintk("ns83820_irq(%p)\n", ndev);
1396 
1397 	dev->ihr = 0;
1398 
1399 	isr = readl(dev->base + ISR);
1400 	dprintk("irq: %08x\n", isr);
1401 	ns83820_do_isr(ndev, isr);
1402 	return IRQ_HANDLED;
1403 }
1404 
1405 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1406 {
1407 	struct ns83820 *dev = PRIV(ndev);
1408 	unsigned long flags;
1409 
1410 #ifdef DEBUG
1411 	if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1412 		Dprintk("odd isr? 0x%08x\n", isr);
1413 #endif
1414 
1415 	if (ISR_RXIDLE & isr) {
1416 		dev->rx_info.idle = 1;
1417 		Dprintk("oh dear, we are idle\n");
1418 		ns83820_rx_kick(ndev);
1419 	}
1420 
1421 	if ((ISR_RXDESC | ISR_RXOK) & isr) {
1422 		prefetch(dev->rx_info.next_rx_desc);
1423 
1424 		spin_lock_irqsave(&dev->misc_lock, flags);
1425 		dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1426 		writel(dev->IMR_cache, dev->base + IMR);
1427 		spin_unlock_irqrestore(&dev->misc_lock, flags);
1428 
1429 		tasklet_schedule(&dev->rx_tasklet);
1430 		//rx_irq(ndev);
1431 		//writel(4, dev->base + IHR);
1432 	}
1433 
1434 	if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1435 		ns83820_rx_kick(ndev);
1436 
1437 	if (unlikely(ISR_RXSOVR & isr)) {
1438 		//printk("overrun: rxsovr\n");
1439 		ndev->stats.rx_fifo_errors++;
1440 	}
1441 
1442 	if (unlikely(ISR_RXORN & isr)) {
1443 		//printk("overrun: rxorn\n");
1444 		ndev->stats.rx_fifo_errors++;
1445 	}
1446 
1447 	if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1448 		writel(CR_RXE, dev->base + CR);
1449 
1450 	if (ISR_TXIDLE & isr) {
1451 		u32 txdp;
1452 		txdp = readl(dev->base + TXDP);
1453 		dprintk("txdp: %08x\n", txdp);
1454 		txdp -= dev->tx_phy_descs;
1455 		dev->tx_idx = txdp / (DESC_SIZE * 4);
1456 		if (dev->tx_idx >= NR_TX_DESC) {
1457 			printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1458 			dev->tx_idx = 0;
1459 		}
1460 		/* The may have been a race between a pci originated read
1461 		 * and the descriptor update from the cpu.  Just in case,
1462 		 * kick the transmitter if the hardware thinks it is on a
1463 		 * different descriptor than we are.
1464 		 */
1465 		if (dev->tx_idx != dev->tx_free_idx)
1466 			kick_tx(dev);
1467 	}
1468 
1469 	/* Defer tx ring processing until more than a minimum amount of
1470 	 * work has accumulated
1471 	 */
1472 	if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1473 		spin_lock_irqsave(&dev->tx_lock, flags);
1474 		do_tx_done(ndev);
1475 		spin_unlock_irqrestore(&dev->tx_lock, flags);
1476 
1477 		/* Disable TxOk if there are no outstanding tx packets.
1478 		 */
1479 		if ((dev->tx_done_idx == dev->tx_free_idx) &&
1480 		    (dev->IMR_cache & ISR_TXOK)) {
1481 			spin_lock_irqsave(&dev->misc_lock, flags);
1482 			dev->IMR_cache &= ~ISR_TXOK;
1483 			writel(dev->IMR_cache, dev->base + IMR);
1484 			spin_unlock_irqrestore(&dev->misc_lock, flags);
1485 		}
1486 	}
1487 
1488 	/* The TxIdle interrupt can come in before the transmit has
1489 	 * completed.  Normally we reap packets off of the combination
1490 	 * of TxDesc and TxIdle and leave TxOk disabled (since it
1491 	 * occurs on every packet), but when no further irqs of this
1492 	 * nature are expected, we must enable TxOk.
1493 	 */
1494 	if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1495 		spin_lock_irqsave(&dev->misc_lock, flags);
1496 		dev->IMR_cache |= ISR_TXOK;
1497 		writel(dev->IMR_cache, dev->base + IMR);
1498 		spin_unlock_irqrestore(&dev->misc_lock, flags);
1499 	}
1500 
1501 	/* MIB interrupt: one of the statistics counters is about to overflow */
1502 	if (unlikely(ISR_MIB & isr))
1503 		ns83820_mib_isr(dev);
1504 
1505 	/* PHY: Link up/down/negotiation state change */
1506 	if (unlikely(ISR_PHY & isr))
1507 		phy_intr(ndev);
1508 
1509 #if 0	/* Still working on the interrupt mitigation strategy */
1510 	if (dev->ihr)
1511 		writel(dev->ihr, dev->base + IHR);
1512 #endif
1513 }
1514 
1515 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1516 {
1517 	Dprintk("resetting chip...\n");
1518 	writel(which, dev->base + CR);
1519 	do {
1520 		schedule();
1521 	} while (readl(dev->base + CR) & which);
1522 	Dprintk("okay!\n");
1523 }
1524 
1525 static int ns83820_stop(struct net_device *ndev)
1526 {
1527 	struct ns83820 *dev = PRIV(ndev);
1528 
1529 	/* FIXME: protect against interrupt handler? */
1530 	del_timer_sync(&dev->tx_watchdog);
1531 
1532 	ns83820_disable_interrupts(dev);
1533 
1534 	dev->rx_info.up = 0;
1535 	synchronize_irq(dev->pci_dev->irq);
1536 
1537 	ns83820_do_reset(dev, CR_RST);
1538 
1539 	synchronize_irq(dev->pci_dev->irq);
1540 
1541 	spin_lock_irq(&dev->misc_lock);
1542 	dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1543 	spin_unlock_irq(&dev->misc_lock);
1544 
1545 	ns83820_cleanup_rx(dev);
1546 	ns83820_cleanup_tx(dev);
1547 
1548 	return 0;
1549 }
1550 
1551 static void ns83820_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1552 {
1553 	struct ns83820 *dev = PRIV(ndev);
1554         u32 tx_done_idx;
1555 	__le32 *desc;
1556 	unsigned long flags;
1557 
1558 	spin_lock_irqsave(&dev->tx_lock, flags);
1559 
1560 	tx_done_idx = dev->tx_done_idx;
1561 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1562 
1563 	printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1564 		ndev->name,
1565 		tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1566 
1567 #if defined(DEBUG)
1568 	{
1569 		u32 isr;
1570 		isr = readl(dev->base + ISR);
1571 		printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1572 		ns83820_do_isr(ndev, isr);
1573 	}
1574 #endif
1575 
1576 	do_tx_done(ndev);
1577 
1578 	tx_done_idx = dev->tx_done_idx;
1579 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1580 
1581 	printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1582 		ndev->name,
1583 		tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1584 
1585 	spin_unlock_irqrestore(&dev->tx_lock, flags);
1586 }
1587 
1588 static void ns83820_tx_watch(struct timer_list *t)
1589 {
1590 	struct ns83820 *dev = from_timer(dev, t, tx_watchdog);
1591 	struct net_device *ndev = dev->ndev;
1592 
1593 #if defined(DEBUG)
1594 	printk("ns83820_tx_watch: %u %u %d\n",
1595 		dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1596 		);
1597 #endif
1598 
1599 	if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1600 	    dev->tx_done_idx != dev->tx_free_idx) {
1601 		printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1602 			ndev->name,
1603 			dev->tx_done_idx, dev->tx_free_idx,
1604 			atomic_read(&dev->nr_tx_skbs));
1605 		ns83820_tx_timeout(ndev, UINT_MAX);
1606 	}
1607 
1608 	mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1609 }
1610 
1611 static int ns83820_open(struct net_device *ndev)
1612 {
1613 	struct ns83820 *dev = PRIV(ndev);
1614 	unsigned i;
1615 	u32 desc;
1616 	int ret;
1617 
1618 	dprintk("ns83820_open\n");
1619 
1620 	writel(0, dev->base + PQCR);
1621 
1622 	ret = ns83820_setup_rx(ndev);
1623 	if (ret)
1624 		goto failed;
1625 
1626 	memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1627 	for (i=0; i<NR_TX_DESC; i++) {
1628 		dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1629 				= cpu_to_le32(
1630 				  dev->tx_phy_descs
1631 				  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1632 	}
1633 
1634 	dev->tx_idx = 0;
1635 	dev->tx_done_idx = 0;
1636 	desc = dev->tx_phy_descs;
1637 	writel(0, dev->base + TXDP_HI);
1638 	writel(desc, dev->base + TXDP);
1639 
1640 	timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1641 	mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1642 
1643 	netif_start_queue(ndev);	/* FIXME: wait for phy to come up */
1644 
1645 	return 0;
1646 
1647 failed:
1648 	ns83820_stop(ndev);
1649 	return ret;
1650 }
1651 
1652 static void ns83820_getmac(struct ns83820 *dev, struct net_device *ndev)
1653 {
1654 	u8 mac[ETH_ALEN];
1655 	unsigned i;
1656 
1657 	for (i=0; i<3; i++) {
1658 		u32 data;
1659 
1660 		/* Read from the perfect match memory: this is loaded by
1661 		 * the chip from the EEPROM via the EELOAD self test.
1662 		 */
1663 		writel(i*2, dev->base + RFCR);
1664 		data = readl(dev->base + RFDR);
1665 
1666 		mac[i * 2] = data;
1667 		mac[i * 2 + 1] = data >> 8;
1668 	}
1669 	eth_hw_addr_set(ndev, mac);
1670 }
1671 
1672 static void ns83820_set_multicast(struct net_device *ndev)
1673 {
1674 	struct ns83820 *dev = PRIV(ndev);
1675 	u8 __iomem *rfcr = dev->base + RFCR;
1676 	u32 and_mask = 0xffffffff;
1677 	u32 or_mask = 0;
1678 	u32 val;
1679 
1680 	if (ndev->flags & IFF_PROMISC)
1681 		or_mask |= RFCR_AAU | RFCR_AAM;
1682 	else
1683 		and_mask &= ~(RFCR_AAU | RFCR_AAM);
1684 
1685 	if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1686 		or_mask |= RFCR_AAM;
1687 	else
1688 		and_mask &= ~RFCR_AAM;
1689 
1690 	spin_lock_irq(&dev->misc_lock);
1691 	val = (readl(rfcr) & and_mask) | or_mask;
1692 	/* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1693 	writel(val & ~RFCR_RFEN, rfcr);
1694 	writel(val, rfcr);
1695 	spin_unlock_irq(&dev->misc_lock);
1696 }
1697 
1698 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1699 {
1700 	struct ns83820 *dev = PRIV(ndev);
1701 	int timed_out = 0;
1702 	unsigned long start;
1703 	u32 status;
1704 	int loops = 0;
1705 
1706 	dprintk("%s: start %s\n", ndev->name, name);
1707 
1708 	start = jiffies;
1709 
1710 	writel(enable, dev->base + PTSCR);
1711 	for (;;) {
1712 		loops++;
1713 		status = readl(dev->base + PTSCR);
1714 		if (!(status & enable))
1715 			break;
1716 		if (status & done)
1717 			break;
1718 		if (status & fail)
1719 			break;
1720 		if (time_after_eq(jiffies, start + HZ)) {
1721 			timed_out = 1;
1722 			break;
1723 		}
1724 		schedule_timeout_uninterruptible(1);
1725 	}
1726 
1727 	if (status & fail)
1728 		printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1729 			ndev->name, name, status, fail);
1730 	else if (timed_out)
1731 		printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1732 			ndev->name, name, status);
1733 
1734 	dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1735 }
1736 
1737 #ifdef PHY_CODE_IS_FINISHED
1738 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1739 {
1740 	/* drive MDC low */
1741 	dev->MEAR_cache &= ~MEAR_MDC;
1742 	writel(dev->MEAR_cache, dev->base + MEAR);
1743 	readl(dev->base + MEAR);
1744 
1745 	/* enable output, set bit */
1746 	dev->MEAR_cache |= MEAR_MDDIR;
1747 	if (bit)
1748 		dev->MEAR_cache |= MEAR_MDIO;
1749 	else
1750 		dev->MEAR_cache &= ~MEAR_MDIO;
1751 
1752 	/* set the output bit */
1753 	writel(dev->MEAR_cache, dev->base + MEAR);
1754 	readl(dev->base + MEAR);
1755 
1756 	/* Wait.  Max clock rate is 2.5MHz, this way we come in under 1MHz */
1757 	udelay(1);
1758 
1759 	/* drive MDC high causing the data bit to be latched */
1760 	dev->MEAR_cache |= MEAR_MDC;
1761 	writel(dev->MEAR_cache, dev->base + MEAR);
1762 	readl(dev->base + MEAR);
1763 
1764 	/* Wait again... */
1765 	udelay(1);
1766 }
1767 
1768 static int ns83820_mii_read_bit(struct ns83820 *dev)
1769 {
1770 	int bit;
1771 
1772 	/* drive MDC low, disable output */
1773 	dev->MEAR_cache &= ~MEAR_MDC;
1774 	dev->MEAR_cache &= ~MEAR_MDDIR;
1775 	writel(dev->MEAR_cache, dev->base + MEAR);
1776 	readl(dev->base + MEAR);
1777 
1778 	/* Wait.  Max clock rate is 2.5MHz, this way we come in under 1MHz */
1779 	udelay(1);
1780 
1781 	/* drive MDC high causing the data bit to be latched */
1782 	bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1783 	dev->MEAR_cache |= MEAR_MDC;
1784 	writel(dev->MEAR_cache, dev->base + MEAR);
1785 
1786 	/* Wait again... */
1787 	udelay(1);
1788 
1789 	return bit;
1790 }
1791 
1792 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1793 {
1794 	unsigned data = 0;
1795 	int i;
1796 
1797 	/* read some garbage so that we eventually sync up */
1798 	for (i=0; i<64; i++)
1799 		ns83820_mii_read_bit(dev);
1800 
1801 	ns83820_mii_write_bit(dev, 0);	/* start */
1802 	ns83820_mii_write_bit(dev, 1);
1803 	ns83820_mii_write_bit(dev, 1);	/* opcode read */
1804 	ns83820_mii_write_bit(dev, 0);
1805 
1806 	/* write out the phy address: 5 bits, msb first */
1807 	for (i=0; i<5; i++)
1808 		ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1809 
1810 	/* write out the register address, 5 bits, msb first */
1811 	for (i=0; i<5; i++)
1812 		ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1813 
1814 	ns83820_mii_read_bit(dev);	/* turn around cycles */
1815 	ns83820_mii_read_bit(dev);
1816 
1817 	/* read in the register data, 16 bits msb first */
1818 	for (i=0; i<16; i++) {
1819 		data <<= 1;
1820 		data |= ns83820_mii_read_bit(dev);
1821 	}
1822 
1823 	return data;
1824 }
1825 
1826 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1827 {
1828 	int i;
1829 
1830 	/* read some garbage so that we eventually sync up */
1831 	for (i=0; i<64; i++)
1832 		ns83820_mii_read_bit(dev);
1833 
1834 	ns83820_mii_write_bit(dev, 0);	/* start */
1835 	ns83820_mii_write_bit(dev, 1);
1836 	ns83820_mii_write_bit(dev, 0);	/* opcode read */
1837 	ns83820_mii_write_bit(dev, 1);
1838 
1839 	/* write out the phy address: 5 bits, msb first */
1840 	for (i=0; i<5; i++)
1841 		ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1842 
1843 	/* write out the register address, 5 bits, msb first */
1844 	for (i=0; i<5; i++)
1845 		ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1846 
1847 	ns83820_mii_read_bit(dev);	/* turn around cycles */
1848 	ns83820_mii_read_bit(dev);
1849 
1850 	/* read in the register data, 16 bits msb first */
1851 	for (i=0; i<16; i++)
1852 		ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1853 
1854 	return data;
1855 }
1856 
1857 static void ns83820_probe_phy(struct net_device *ndev)
1858 {
1859 	struct ns83820 *dev = PRIV(ndev);
1860 	int j;
1861 	unsigned a, b;
1862 
1863 	for (j = 0; j < 0x16; j += 4) {
1864 		dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1865 			ndev->name, j,
1866 			ns83820_mii_read_reg(dev, 1, 0 + j),
1867 			ns83820_mii_read_reg(dev, 1, 1 + j),
1868 			ns83820_mii_read_reg(dev, 1, 2 + j),
1869 			ns83820_mii_read_reg(dev, 1, 3 + j)
1870 			);
1871 	}
1872 
1873 	/* read firmware version: memory addr is 0x8402 and 0x8403 */
1874 	ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1875 	ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1876 	a = ns83820_mii_read_reg(dev, 1, 0x1d);
1877 
1878 	ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1879 	ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1880 	b = ns83820_mii_read_reg(dev, 1, 0x1d);
1881 	dprintk("version: 0x%04x 0x%04x\n", a, b);
1882 }
1883 #endif
1884 
1885 static const struct net_device_ops netdev_ops = {
1886 	.ndo_open		= ns83820_open,
1887 	.ndo_stop		= ns83820_stop,
1888 	.ndo_start_xmit		= ns83820_hard_start_xmit,
1889 	.ndo_get_stats		= ns83820_get_stats,
1890 	.ndo_set_rx_mode	= ns83820_set_multicast,
1891 	.ndo_validate_addr	= eth_validate_addr,
1892 	.ndo_set_mac_address	= eth_mac_addr,
1893 	.ndo_tx_timeout		= ns83820_tx_timeout,
1894 };
1895 
1896 static int ns83820_init_one(struct pci_dev *pci_dev,
1897 			    const struct pci_device_id *id)
1898 {
1899 	struct net_device *ndev;
1900 	struct ns83820 *dev;
1901 	long addr;
1902 	int err;
1903 	int using_dac = 0;
1904 
1905 	/* See if we can set the dma mask early on; failure is fatal. */
1906 	if (sizeof(dma_addr_t) == 8 &&
1907 		!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
1908 		using_dac = 1;
1909 	} else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
1910 		using_dac = 0;
1911 	} else {
1912 		dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
1913 		return -ENODEV;
1914 	}
1915 
1916 	ndev = alloc_etherdev(sizeof(struct ns83820));
1917 	err = -ENOMEM;
1918 	if (!ndev)
1919 		goto out;
1920 
1921 	dev = PRIV(ndev);
1922 	dev->ndev = ndev;
1923 
1924 	spin_lock_init(&dev->rx_info.lock);
1925 	spin_lock_init(&dev->tx_lock);
1926 	spin_lock_init(&dev->misc_lock);
1927 	dev->pci_dev = pci_dev;
1928 
1929 	SET_NETDEV_DEV(ndev, &pci_dev->dev);
1930 
1931 	INIT_WORK(&dev->tq_refill, queue_refill);
1932 	tasklet_setup(&dev->rx_tasklet, rx_action);
1933 
1934 	err = pci_enable_device(pci_dev);
1935 	if (err) {
1936 		dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1937 		goto out_free;
1938 	}
1939 
1940 	pci_set_master(pci_dev);
1941 	addr = pci_resource_start(pci_dev, 1);
1942 	dev->base = ioremap(addr, PAGE_SIZE);
1943 	dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
1944 					   4 * DESC_SIZE * NR_TX_DESC,
1945 					   &dev->tx_phy_descs, GFP_KERNEL);
1946 	dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
1947 						4 * DESC_SIZE * NR_RX_DESC,
1948 						&dev->rx_info.phy_descs, GFP_KERNEL);
1949 	err = -ENOMEM;
1950 	if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1951 		goto out_disable;
1952 
1953 	dprintk("%p: %08lx  %p: %08lx\n",
1954 		dev->tx_descs, (long)dev->tx_phy_descs,
1955 		dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1956 
1957 	ns83820_disable_interrupts(dev);
1958 
1959 	dev->IMR_cache = 0;
1960 
1961 	err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1962 			  DRV_NAME, ndev);
1963 	if (err) {
1964 		dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1965 			pci_dev->irq, err);
1966 		goto out_disable;
1967 	}
1968 
1969 	/*
1970 	 * FIXME: we are holding rtnl_lock() over obscenely long area only
1971 	 * because some of the setup code uses dev->name.  It's Wrong(tm) -
1972 	 * we should be using driver-specific names for all that stuff.
1973 	 * For now that will do, but we really need to come back and kill
1974 	 * most of the dev_alloc_name() users later.
1975 	 */
1976 	rtnl_lock();
1977 	err = dev_alloc_name(ndev, ndev->name);
1978 	if (err < 0) {
1979 		dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1980 		goto out_free_irq;
1981 	}
1982 
1983 	printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1984 		ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1985 		pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1986 
1987 	ndev->netdev_ops = &netdev_ops;
1988 	ndev->ethtool_ops = &ops;
1989 	ndev->watchdog_timeo = 5 * HZ;
1990 	pci_set_drvdata(pci_dev, ndev);
1991 
1992 	ns83820_do_reset(dev, CR_RST);
1993 
1994 	/* Must reset the ram bist before running it */
1995 	writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1996 	ns83820_run_bist(ndev, "sram bist",   PTSCR_RBIST_EN,
1997 			 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1998 	ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1999 			 PTSCR_EEBIST_FAIL);
2000 	ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2001 
2002 	/* I love config registers */
2003 	dev->CFG_cache = readl(dev->base + CFG);
2004 
2005 	if ((dev->CFG_cache & CFG_PCI64_DET)) {
2006 		printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2007 			ndev->name);
2008 		/*dev->CFG_cache |= CFG_DATA64_EN;*/
2009 		if (!(dev->CFG_cache & CFG_DATA64_EN))
2010 			printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus.  Disabled.\n",
2011 				ndev->name);
2012 	} else
2013 		dev->CFG_cache &= ~(CFG_DATA64_EN);
2014 
2015 	dev->CFG_cache &= (CFG_TBI_EN  | CFG_MRM_DIS   | CFG_MWI_DIS |
2016 			   CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2017 			   CFG_M64ADDR);
2018 	dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2019 			  CFG_EXTSTS_EN   | CFG_EXD         | CFG_PESEL;
2020 	dev->CFG_cache |= CFG_REQALG;
2021 	dev->CFG_cache |= CFG_POW;
2022 	dev->CFG_cache |= CFG_TMRTEST;
2023 
2024 	/* When compiled with 64 bit addressing, we must always enable
2025 	 * the 64 bit descriptor format.
2026 	 */
2027 	if (sizeof(dma_addr_t) == 8)
2028 		dev->CFG_cache |= CFG_M64ADDR;
2029 	if (using_dac)
2030 		dev->CFG_cache |= CFG_T64ADDR;
2031 
2032 	/* Big endian mode does not seem to do what the docs suggest */
2033 	dev->CFG_cache &= ~CFG_BEM;
2034 
2035 	/* setup optical transceiver if we have one */
2036 	if (dev->CFG_cache & CFG_TBI_EN) {
2037 		printk(KERN_INFO "%s: enabling optical transceiver\n",
2038 			ndev->name);
2039 		writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2040 
2041 		/* setup auto negotiation feature advertisement */
2042 		writel(readl(dev->base + TANAR)
2043 		       | TANAR_HALF_DUP | TANAR_FULL_DUP,
2044 		       dev->base + TANAR);
2045 
2046 		/* start auto negotiation */
2047 		writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2048 		       dev->base + TBICR);
2049 		writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2050 		dev->linkstate = LINK_AUTONEGOTIATE;
2051 
2052 		dev->CFG_cache |= CFG_MODE_1000;
2053 	}
2054 
2055 	writel(dev->CFG_cache, dev->base + CFG);
2056 	dprintk("CFG: %08x\n", dev->CFG_cache);
2057 
2058 	if (reset_phy) {
2059 		printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2060 		writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2061 		msleep(10);
2062 		writel(dev->CFG_cache, dev->base + CFG);
2063 	}
2064 
2065 #if 0	/* Huh?  This sets the PCI latency register.  Should be done via
2066 	 * the PCI layer.  FIXME.
2067 	 */
2068 	if (readl(dev->base + SRR))
2069 		writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2070 #endif
2071 
2072 	/* Note!  The DMA burst size interacts with packet
2073 	 * transmission, such that the largest packet that
2074 	 * can be transmitted is 8192 - FLTH - burst size.
2075 	 * If only the transmit fifo was larger...
2076 	 */
2077 	/* Ramit : 1024 DMA is not a good idea, it ends up banging
2078 	 * some DELL and COMPAQ SMP systems */
2079 	writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2080 		| ((1600 / 32) * 0x100),
2081 		dev->base + TXCFG);
2082 
2083 	/* Flush the interrupt holdoff timer */
2084 	writel(0x000, dev->base + IHR);
2085 	writel(0x100, dev->base + IHR);
2086 	writel(0x000, dev->base + IHR);
2087 
2088 	/* Set Rx to full duplex, don't accept runt, errored, long or length
2089 	 * range errored packets.  Use 512 byte DMA.
2090 	 */
2091 	/* Ramit : 1024 DMA is not a good idea, it ends up banging
2092 	 * some DELL and COMPAQ SMP systems
2093 	 * Turn on ALP, only we are accpeting Jumbo Packets */
2094 	writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2095 		| RXCFG_STRIPCRC
2096 		//| RXCFG_ALP
2097 		| (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2098 
2099 	/* Disable priority queueing */
2100 	writel(0, dev->base + PQCR);
2101 
2102 	/* Enable IP checksum validation and detetion of VLAN headers.
2103 	 * Note: do not set the reject options as at least the 0x102
2104 	 * revision of the chip does not properly accept IP fragments
2105 	 * at least for UDP.
2106 	 */
2107 	/* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2108 	 * the MAC it calculates the packetsize AFTER stripping the VLAN
2109 	 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2110 	 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2111 	 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2112 	 * it discrards it!.  These guys......
2113 	 * also turn on tag stripping if hardware acceleration is enabled
2114 	 */
2115 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2116 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2117 #else
2118 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2119 #endif
2120 	writel(VRCR_INIT_VALUE, dev->base + VRCR);
2121 
2122 	/* Enable per-packet TCP/UDP/IP checksumming
2123 	 * and per packet vlan tag insertion if
2124 	 * vlan hardware acceleration is enabled
2125 	 */
2126 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2127 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2128 #else
2129 #define VTCR_INIT_VALUE VTCR_PPCHK
2130 #endif
2131 	writel(VTCR_INIT_VALUE, dev->base + VTCR);
2132 
2133 	/* Ramit : Enable async and sync pause frames */
2134 	/* writel(0, dev->base + PCR); */
2135 	writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2136 		PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2137 		dev->base + PCR);
2138 
2139 	/* Disable Wake On Lan */
2140 	writel(0, dev->base + WCSR);
2141 
2142 	ns83820_getmac(dev, ndev);
2143 
2144 	/* Yes, we support dumb IP checksum on transmit */
2145 	ndev->features |= NETIF_F_SG;
2146 	ndev->features |= NETIF_F_IP_CSUM;
2147 
2148 	ndev->min_mtu = 0;
2149 
2150 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2151 	/* We also support hardware vlan acceleration */
2152 	ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2153 #endif
2154 
2155 	if (using_dac) {
2156 		printk(KERN_INFO "%s: using 64 bit addressing.\n",
2157 			ndev->name);
2158 		ndev->features |= NETIF_F_HIGHDMA;
2159 	}
2160 
2161 	printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2162 		ndev->name,
2163 		(unsigned)readl(dev->base + SRR) >> 8,
2164 		(unsigned)readl(dev->base + SRR) & 0xff,
2165 		ndev->dev_addr, addr, pci_dev->irq,
2166 		(ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2167 		);
2168 
2169 #ifdef PHY_CODE_IS_FINISHED
2170 	ns83820_probe_phy(ndev);
2171 #endif
2172 
2173 	err = register_netdevice(ndev);
2174 	if (err) {
2175 		printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2176 		goto out_cleanup;
2177 	}
2178 	rtnl_unlock();
2179 
2180 	return 0;
2181 
2182 out_cleanup:
2183 	ns83820_disable_interrupts(dev); /* paranoia */
2184 out_free_irq:
2185 	rtnl_unlock();
2186 	free_irq(pci_dev->irq, ndev);
2187 out_disable:
2188 	if (dev->base)
2189 		iounmap(dev->base);
2190 	dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2191 			  dev->tx_descs, dev->tx_phy_descs);
2192 	dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2193 			  dev->rx_info.descs, dev->rx_info.phy_descs);
2194 	pci_disable_device(pci_dev);
2195 out_free:
2196 	free_netdev(ndev);
2197 out:
2198 	return err;
2199 }
2200 
2201 static void ns83820_remove_one(struct pci_dev *pci_dev)
2202 {
2203 	struct net_device *ndev = pci_get_drvdata(pci_dev);
2204 	struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2205 
2206 	if (!ndev)			/* paranoia */
2207 		return;
2208 
2209 	ns83820_disable_interrupts(dev); /* paranoia */
2210 
2211 	unregister_netdev(ndev);
2212 	free_irq(dev->pci_dev->irq, ndev);
2213 	iounmap(dev->base);
2214 	dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2215 			  dev->tx_descs, dev->tx_phy_descs);
2216 	dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2217 			  dev->rx_info.descs, dev->rx_info.phy_descs);
2218 	pci_disable_device(dev->pci_dev);
2219 	free_netdev(ndev);
2220 }
2221 
2222 static const struct pci_device_id ns83820_pci_tbl[] = {
2223 	{ 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2224 	{ 0, },
2225 };
2226 
2227 static struct pci_driver driver = {
2228 	.name		= "ns83820",
2229 	.id_table	= ns83820_pci_tbl,
2230 	.probe		= ns83820_init_one,
2231 	.remove		= ns83820_remove_one,
2232 #if 0	/* FIXME: implement */
2233 	.suspend	= ,
2234 	.resume		= ,
2235 #endif
2236 };
2237 
2238 
2239 static int __init ns83820_init(void)
2240 {
2241 	printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2242 	return pci_register_driver(&driver);
2243 }
2244 
2245 static void __exit ns83820_exit(void)
2246 {
2247 	pci_unregister_driver(&driver);
2248 }
2249 
2250 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2251 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2252 MODULE_LICENSE("GPL");
2253 
2254 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2255 
2256 module_param(lnksts, int, 0);
2257 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2258 
2259 module_param(ihr, int, 0);
2260 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2261 
2262 module_param(reset_phy, int, 0);
2263 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2264 
2265 module_init(ns83820_init);
2266 module_exit(ns83820_exit);
2267