1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2015 Google, Inc 4 * Copyright 2014 Rockchip Inc. 5 */ 6 7 #ifndef _ASM_ARCH_GRF_RK3288_H 8 #define _ASM_ARCH_GRF_RK3288_H 9 10 struct rk3288_grf_gpio_lh { 11 u32 l; 12 u32 h; 13 }; 14 15 struct rk3288_grf { 16 u32 reserved[3]; 17 u32 gpio1d_iomux; 18 u32 gpio2a_iomux; 19 u32 gpio2b_iomux; 20 21 u32 gpio2c_iomux; 22 u32 reserved2; 23 u32 gpio3a_iomux; 24 u32 gpio3b_iomux; 25 26 u32 gpio3c_iomux; 27 u32 gpio3dl_iomux; 28 u32 gpio3dh_iomux; 29 u32 gpio4al_iomux; 30 31 u32 gpio4ah_iomux; 32 u32 gpio4bl_iomux; 33 u32 reserved3; 34 u32 gpio4c_iomux; 35 36 u32 gpio4d_iomux; 37 u32 reserved4; 38 u32 gpio5b_iomux; 39 u32 gpio5c_iomux; 40 41 u32 reserved5; 42 u32 gpio6a_iomux; 43 u32 gpio6b_iomux; 44 u32 gpio6c_iomux; 45 u32 reserved6; 46 u32 gpio7a_iomux; 47 u32 gpio7b_iomux; 48 u32 gpio7cl_iomux; 49 u32 gpio7ch_iomux; 50 u32 reserved7; 51 u32 gpio8a_iomux; 52 u32 gpio8b_iomux; 53 u32 reserved8[30]; 54 struct rk3288_grf_gpio_lh gpio_sr[8]; 55 u32 gpio1_p[8][4]; 56 u32 gpio1_e[8][4]; 57 u32 gpio_smt; 58 u32 soc_con0; 59 u32 soc_con1; 60 u32 soc_con2; 61 u32 soc_con3; 62 u32 soc_con4; 63 u32 soc_con5; 64 u32 soc_con6; 65 u32 soc_con7; 66 u32 soc_con8; 67 u32 soc_con9; 68 u32 soc_con10; 69 u32 soc_con11; 70 u32 soc_con12; 71 u32 soc_con13; 72 u32 soc_con14; 73 u32 soc_status[22]; 74 u32 reserved9[2]; 75 u32 peridmac_con[4]; 76 u32 ddrc0_con0; 77 u32 ddrc1_con0; 78 u32 cpu_con[5]; 79 u32 reserved10[3]; 80 u32 cpu_status0; 81 u32 reserved11; 82 u32 uoc0_con[5]; 83 u32 uoc1_con[5]; 84 u32 uoc2_con[4]; 85 u32 uoc3_con[2]; 86 u32 uoc4_con[2]; 87 u32 pvtm_con[3]; 88 u32 pvtm_status[3]; 89 u32 io_vsel; 90 u32 saradc_testbit; 91 u32 tsadc_testbit_l; 92 u32 tsadc_testbit_h; 93 u32 os_reg[4]; 94 u32 reserved12; 95 u32 soc_con15; 96 u32 soc_con16; 97 }; 98 99 struct rk3288_sgrf { 100 u32 soc_con0; 101 u32 soc_con1; 102 u32 soc_con2; 103 u32 soc_con3; 104 u32 soc_con4; 105 u32 soc_con5; 106 u32 reserved1[(0x20-0x18)/4]; 107 u32 busdmac_con[2]; 108 u32 reserved2[(0x40-0x28)/4]; 109 u32 cpu_con[3]; 110 u32 reserved3[(0x50-0x4c)/4]; 111 u32 soc_con6; 112 u32 soc_con7; 113 u32 soc_con8; 114 u32 soc_con9; 115 u32 soc_con10; 116 u32 soc_con11; 117 u32 soc_con12; 118 u32 soc_con13; 119 u32 soc_con14; 120 u32 soc_con15; 121 u32 soc_con16; 122 u32 soc_con17; 123 u32 soc_con18; 124 u32 soc_con19; 125 u32 soc_con20; 126 u32 soc_con21; 127 u32 reserved4[(0x100-0x90)/4]; 128 u32 soc_status[2]; 129 u32 reserved5[(0x120-0x108)/4]; 130 u32 fast_boot_addr; 131 }; 132 133 /* GRF_GPIO1D_IOMUX */ 134 enum { 135 GPIO1D3_SHIFT = 6, 136 GPIO1D3_MASK = 1, 137 GPIO1D3_GPIO = 0, 138 GPIO1D3_LCDC0_DCLK, 139 140 GPIO1D2_SHIFT = 4, 141 GPIO1D2_MASK = 1, 142 GPIO1D2_GPIO = 0, 143 GPIO1D2_LCDC0_DEN, 144 145 GPIO1D1_SHIFT = 2, 146 GPIO1D1_MASK = 1, 147 GPIO1D1_GPIO = 0, 148 GPIO1D1_LCDC0_VSYNC, 149 150 GPIO1D0_SHIFT = 0, 151 GPIO1D0_MASK = 1, 152 GPIO1D0_GPIO = 0, 153 GPIO1D0_LCDC0_HSYNC, 154 }; 155 156 /* GRF_GPIO2C_IOMUX */ 157 enum { 158 GPIO2C1_SHIFT = 2, 159 GPIO2C1_MASK = 1, 160 GPIO2C1_GPIO = 0, 161 GPIO2C1_I2C3CAM_SDA, 162 163 GPIO2C0_SHIFT = 0, 164 GPIO2C0_MASK = 1, 165 GPIO2C0_GPIO = 0, 166 GPIO2C0_I2C3CAM_SCL, 167 }; 168 169 /* GRF_GPIO3A_IOMUX */ 170 enum { 171 GPIO3A7_SHIFT = 14, 172 GPIO3A7_MASK = 3, 173 GPIO3A7_GPIO = 0, 174 GPIO3A7_FLASH0_DATA7, 175 GPIO3A7_EMMC_DATA7, 176 177 GPIO3A6_SHIFT = 12, 178 GPIO3A6_MASK = 3, 179 GPIO3A6_GPIO = 0, 180 GPIO3A6_FLASH0_DATA6, 181 GPIO3A6_EMMC_DATA6, 182 183 GPIO3A5_SHIFT = 10, 184 GPIO3A5_MASK = 3, 185 GPIO3A5_GPIO = 0, 186 GPIO3A5_FLASH0_DATA5, 187 GPIO3A5_EMMC_DATA5, 188 189 GPIO3A4_SHIFT = 8, 190 GPIO3A4_MASK = 3, 191 GPIO3A4_GPIO = 0, 192 GPIO3A4_FLASH0_DATA4, 193 GPIO3A4_EMMC_DATA4, 194 195 GPIO3A3_SHIFT = 6, 196 GPIO3A3_MASK = 3, 197 GPIO3A3_GPIO = 0, 198 GPIO3A3_FLASH0_DATA3, 199 GPIO3A3_EMMC_DATA3, 200 201 GPIO3A2_SHIFT = 4, 202 GPIO3A2_MASK = 3, 203 GPIO3A2_GPIO = 0, 204 GPIO3A2_FLASH0_DATA2, 205 GPIO3A2_EMMC_DATA2, 206 207 GPIO3A1_SHIFT = 2, 208 GPIO3A1_MASK = 3, 209 GPIO3A1_GPIO = 0, 210 GPIO3A1_FLASH0_DATA1, 211 GPIO3A1_EMMC_DATA1, 212 213 GPIO3A0_SHIFT = 0, 214 GPIO3A0_MASK = 3, 215 GPIO3A0_GPIO = 0, 216 GPIO3A0_FLASH0_DATA0, 217 GPIO3A0_EMMC_DATA0, 218 }; 219 220 /* GRF_GPIO3B_IOMUX */ 221 enum { 222 GPIO3B7_SHIFT = 14, 223 GPIO3B7_MASK = 1, 224 GPIO3B7_GPIO = 0, 225 GPIO3B7_FLASH0_CSN1, 226 227 GPIO3B6_SHIFT = 12, 228 GPIO3B6_MASK = 1, 229 GPIO3B6_GPIO = 0, 230 GPIO3B6_FLASH0_CSN0, 231 232 GPIO3B5_SHIFT = 10, 233 GPIO3B5_MASK = 1, 234 GPIO3B5_GPIO = 0, 235 GPIO3B5_FLASH0_WRN, 236 237 GPIO3B4_SHIFT = 8, 238 GPIO3B4_MASK = 1, 239 GPIO3B4_GPIO = 0, 240 GPIO3B4_FLASH0_CLE, 241 242 GPIO3B3_SHIFT = 6, 243 GPIO3B3_MASK = 1, 244 GPIO3B3_GPIO = 0, 245 GPIO3B3_FLASH0_ALE, 246 247 GPIO3B2_SHIFT = 4, 248 GPIO3B2_MASK = 1, 249 GPIO3B2_GPIO = 0, 250 GPIO3B2_FLASH0_RDN, 251 252 GPIO3B1_SHIFT = 2, 253 GPIO3B1_MASK = 3, 254 GPIO3B1_GPIO = 0, 255 GPIO3B1_FLASH0_WP, 256 GPIO3B1_EMMC_PWREN, 257 258 GPIO3B0_SHIFT = 0, 259 GPIO3B0_MASK = 1, 260 GPIO3B0_GPIO = 0, 261 GPIO3B0_FLASH0_RDY, 262 }; 263 264 /* GRF_GPIO3C_IOMUX */ 265 enum { 266 GPIO3C2_SHIFT = 4, 267 GPIO3C2_MASK = 3, 268 GPIO3C2_GPIO = 0, 269 GPIO3C2_FLASH0_DQS, 270 GPIO3C2_EMMC_CLKOUT, 271 272 GPIO3C1_SHIFT = 2, 273 GPIO3C1_MASK = 3, 274 GPIO3C1_GPIO = 0, 275 GPIO3C1_FLASH0_CSN3, 276 GPIO3C1_EMMC_RSTNOUT, 277 278 GPIO3C0_SHIFT = 0, 279 GPIO3C0_MASK = 3, 280 GPIO3C0_GPIO = 0, 281 GPIO3C0_FLASH0_CSN2, 282 GPIO3C0_EMMC_CMD, 283 }; 284 285 /* GRF_GPIO3DL_IOMUX */ 286 enum { 287 GPIO3D3_SHIFT = 12, 288 GPIO3D3_MASK = 7, 289 GPIO3D3_GPIO = 0, 290 GPIO3D3_FLASH1_DATA3, 291 GPIO3D3_HOST_DOUT3, 292 GPIO3D3_MAC_RXD3, 293 GPIO3D3_SDIO1_DATA3, 294 295 GPIO3D2_SHIFT = 8, 296 GPIO3D2_MASK = 7, 297 GPIO3D2_GPIO = 0, 298 GPIO3D2_FLASH1_DATA2, 299 GPIO3D2_HOST_DOUT2, 300 GPIO3D2_MAC_RXD2, 301 GPIO3D2_SDIO1_DATA2, 302 303 GPIO3D1_SHIFT = 4, 304 GPIO3D1_MASK = 7, 305 GPIO3D1_GPIO = 0, 306 GPIO3DL1_FLASH1_DATA1, 307 GPIO3D1_HOST_DOUT1, 308 GPIO3D1_MAC_TXD3, 309 GPIO3D1_SDIO1_DATA1, 310 311 GPIO3D0_SHIFT = 0, 312 GPIO3D0_MASK = 7, 313 GPIO3D0_GPIO = 0, 314 GPIO3D0_FLASH1_DATA0, 315 GPIO3D0_HOST_DOUT0, 316 GPIO3D0_MAC_TXD2, 317 GPIO3D0_SDIO1_DATA0, 318 }; 319 320 /* GRF_GPIO3HL_IOMUX */ 321 enum { 322 GPIO3D7_SHIFT = 12, 323 GPIO3D7_MASK = 7, 324 GPIO3D7_GPIO = 0, 325 GPIO3D7_FLASH1_DATA7, 326 GPIO3D7_HOST_DOUT7, 327 GPIO3D7_MAC_RXD1, 328 GPIO3D7_SDIO1_INTN, 329 330 GPIO3D6_SHIFT = 8, 331 GPIO3D6_MASK = 7, 332 GPIO3D6_GPIO = 0, 333 GPIO3D6_FLASH1_DATA6, 334 GPIO3D6_HOST_DOUT6, 335 GPIO3D6_MAC_RXD0, 336 GPIO3D6_SDIO1_BKPWR, 337 338 GPIO3D5_SHIFT = 4, 339 GPIO3D5_MASK = 7, 340 GPIO3D5_GPIO = 0, 341 GPIO3D5_FLASH1_DATA5, 342 GPIO3D5_HOST_DOUT5, 343 GPIO3D5_MAC_TXD1, 344 GPIO3D5_SDIO1_WRPRT, 345 346 GPIO3D4_SHIFT = 0, 347 GPIO3D4_MASK = 7, 348 GPIO3D4_GPIO = 0, 349 GPIO3D4_FLASH1_DATA4, 350 GPIO3D4_HOST_DOUT4, 351 GPIO3D4_MAC_TXD0, 352 GPIO3D4_SDIO1_DETECTN, 353 }; 354 355 /* GRF_GPIO4AL_IOMUX */ 356 enum { 357 GPIO4A3_SHIFT = 12, 358 GPIO4A3_MASK = 7, 359 GPIO4A3_GPIO = 0, 360 GPIO4A3_FLASH1_ALE, 361 GPIO4A3_HOST_DOUT9, 362 GPIO4A3_MAC_CLK, 363 GPIO4A3_FLASH0_CSN6, 364 365 GPIO4A2_SHIFT = 8, 366 GPIO4A2_MASK = 7, 367 GPIO4A2_GPIO = 0, 368 GPIO4A2_FLASH1_RDN, 369 GPIO4A2_HOST_DOUT8, 370 GPIO4A2_MAC_RXER, 371 GPIO4A2_FLASH0_CSN5, 372 373 GPIO4A1_SHIFT = 4, 374 GPIO4A1_MASK = 7, 375 GPIO4A1_GPIO = 0, 376 GPIO4A1_FLASH1_WP, 377 GPIO4A1_HOST_CKOUTN, 378 GPIO4A1_MAC_TXDV, 379 GPIO4A1_FLASH0_CSN4, 380 381 GPIO4A0_SHIFT = 0, 382 GPIO4A0_MASK = 3, 383 GPIO4A0_GPIO = 0, 384 GPIO4A0_FLASH1_RDY, 385 GPIO4A0_HOST_CKOUTP, 386 GPIO4A0_MAC_MDC, 387 }; 388 389 /* GRF_GPIO4AH_IOMUX */ 390 enum { 391 GPIO4A7_SHIFT = 12, 392 GPIO4A7_MASK = 7, 393 GPIO4A7_GPIO = 0, 394 GPIO4A7_FLASH1_CSN1, 395 GPIO4A7_HOST_DOUT13, 396 GPIO4A7_MAC_CSR, 397 GPIO4A7_SDIO1_CLKOUT, 398 399 GPIO4A6_SHIFT = 8, 400 GPIO4A6_MASK = 7, 401 GPIO4A6_GPIO = 0, 402 GPIO4A6_FLASH1_CSN0, 403 GPIO4A6_HOST_DOUT12, 404 GPIO4A6_MAC_RXCLK, 405 GPIO4A6_SDIO1_CMD, 406 407 GPIO4A5_SHIFT = 4, 408 GPIO4A5_MASK = 3, 409 GPIO4A5_GPIO = 0, 410 GPIO4A5_FLASH1_WRN, 411 GPIO4A5_HOST_DOUT11, 412 GPIO4A5_MAC_MDIO, 413 414 GPIO4A4_SHIFT = 0, 415 GPIO4A4_MASK = 7, 416 GPIO4A4_GPIO = 0, 417 GPIO4A4_FLASH1_CLE, 418 GPIO4A4_HOST_DOUT10, 419 GPIO4A4_MAC_TXEN, 420 GPIO4A4_FLASH0_CSN7, 421 }; 422 423 /* GRF_GPIO4BL_IOMUX */ 424 enum { 425 GPIO4B1_SHIFT = 4, 426 GPIO4B1_MASK = 7, 427 GPIO4B1_GPIO = 0, 428 GPIO4B1_FLASH1_CSN2, 429 GPIO4B1_HOST_DOUT15, 430 GPIO4B1_MAC_TXCLK, 431 GPIO4B1_SDIO1_PWREN, 432 433 GPIO4B0_SHIFT = 0, 434 GPIO4B0_MASK = 7, 435 GPIO4B0_GPIO = 0, 436 GPIO4B0_FLASH1_DQS, 437 GPIO4B0_HOST_DOUT14, 438 GPIO4B0_MAC_COL, 439 GPIO4B0_FLASH1_CSN3, 440 }; 441 442 /* GRF_GPIO4C_IOMUX */ 443 enum { 444 GPIO4C7_SHIFT = 14, 445 GPIO4C7_MASK = 1, 446 GPIO4C7_GPIO = 0, 447 GPIO4C7_SDIO0_DATA3, 448 449 GPIO4C6_SHIFT = 12, 450 GPIO4C6_MASK = 1, 451 GPIO4C6_GPIO = 0, 452 GPIO4C6_SDIO0_DATA2, 453 454 GPIO4C5_SHIFT = 10, 455 GPIO4C5_MASK = 1, 456 GPIO4C5_GPIO = 0, 457 GPIO4C5_SDIO0_DATA1, 458 459 GPIO4C4_SHIFT = 8, 460 GPIO4C4_MASK = 1, 461 GPIO4C4_GPIO = 0, 462 GPIO4C4_SDIO0_DATA0, 463 464 GPIO4C3_SHIFT = 6, 465 GPIO4C3_MASK = 1, 466 GPIO4C3_GPIO = 0, 467 GPIO4C3_UART0BT_RTSN, 468 469 GPIO4C2_SHIFT = 4, 470 GPIO4C2_MASK = 1, 471 GPIO4C2_GPIO = 0, 472 GPIO4C2_UART0BT_CTSN, 473 474 GPIO4C1_SHIFT = 2, 475 GPIO4C1_MASK = 1, 476 GPIO4C1_GPIO = 0, 477 GPIO4C1_UART0BT_SOUT, 478 479 GPIO4C0_SHIFT = 0, 480 GPIO4C0_MASK = 1, 481 GPIO4C0_GPIO = 0, 482 GPIO4C0_UART0BT_SIN, 483 }; 484 485 /* GRF_GPIO5B_IOMUX */ 486 enum { 487 GPIO5B7_SHIFT = 14, 488 GPIO5B7_MASK = 3, 489 GPIO5B7_GPIO = 0, 490 GPIO5B7_SPI0_RXD, 491 GPIO5B7_TS0_DATA7, 492 GPIO5B7_UART4EXP_SIN, 493 494 GPIO5B6_SHIFT = 12, 495 GPIO5B6_MASK = 3, 496 GPIO5B6_GPIO = 0, 497 GPIO5B6_SPI0_TXD, 498 GPIO5B6_TS0_DATA6, 499 GPIO5B6_UART4EXP_SOUT, 500 501 GPIO5B5_SHIFT = 10, 502 GPIO5B5_MASK = 3, 503 GPIO5B5_GPIO = 0, 504 GPIO5B5_SPI0_CSN0, 505 GPIO5B5_TS0_DATA5, 506 GPIO5B5_UART4EXP_RTSN, 507 508 GPIO5B4_SHIFT = 8, 509 GPIO5B4_MASK = 3, 510 GPIO5B4_GPIO = 0, 511 GPIO5B4_SPI0_CLK, 512 GPIO5B4_TS0_DATA4, 513 GPIO5B4_UART4EXP_CTSN, 514 515 GPIO5B3_SHIFT = 6, 516 GPIO5B3_MASK = 3, 517 GPIO5B3_GPIO = 0, 518 GPIO5B3_UART1BB_RTSN, 519 GPIO5B3_TS0_DATA3, 520 521 GPIO5B2_SHIFT = 4, 522 GPIO5B2_MASK = 3, 523 GPIO5B2_GPIO = 0, 524 GPIO5B2_UART1BB_CTSN, 525 GPIO5B2_TS0_DATA2, 526 527 GPIO5B1_SHIFT = 2, 528 GPIO5B1_MASK = 3, 529 GPIO5B1_GPIO = 0, 530 GPIO5B1_UART1BB_SOUT, 531 GPIO5B1_TS0_DATA1, 532 533 GPIO5B0_SHIFT = 0, 534 GPIO5B0_MASK = 3, 535 GPIO5B0_GPIO = 0, 536 GPIO5B0_UART1BB_SIN, 537 GPIO5B0_TS0_DATA0, 538 }; 539 540 /* GRF_GPIO5C_IOMUX */ 541 enum { 542 GPIO5C3_SHIFT = 6, 543 GPIO5C3_MASK = 1, 544 GPIO5C3_GPIO = 0, 545 GPIO5C3_TS0_ERR, 546 547 GPIO5C2_SHIFT = 4, 548 GPIO5C2_MASK = 1, 549 GPIO5C2_GPIO = 0, 550 GPIO5C2_TS0_CLK, 551 552 GPIO5C1_SHIFT = 2, 553 GPIO5C1_MASK = 1, 554 GPIO5C1_GPIO = 0, 555 GPIO5C1_TS0_VALID, 556 557 GPIO5C0_SHIFT = 0, 558 GPIO5C0_MASK = 3, 559 GPIO5C0_GPIO = 0, 560 GPIO5C0_SPI0_CSN1, 561 GPIO5C0_TS0_SYNC, 562 }; 563 564 /* GRF_GPIO6A_IOMUX */ 565 enum { 566 GPIO6A7_SHIFT = 0xe, 567 GPIO6A7_MASK = 1, 568 GPIO6A7_GPIO = 0, 569 GPIO6A7_I2S_SDO3, 570 571 GPIO6A6_SHIFT = 0xc, 572 GPIO6A6_MASK = 1, 573 GPIO6A6_GPIO = 0, 574 GPIO6A6_I2S_SDO2, 575 576 GPIO6A5_SHIFT = 0xa, 577 GPIO6A5_MASK = 1, 578 GPIO6A5_GPIO = 0, 579 GPIO6A5_I2S_SDO1, 580 581 GPIO6A4_SHIFT = 8, 582 GPIO6A4_MASK = 1, 583 GPIO6A4_GPIO = 0, 584 GPIO6A4_I2S_SDO0, 585 586 GPIO6A3_SHIFT = 6, 587 GPIO6A3_MASK = 1, 588 GPIO6A3_GPIO = 0, 589 GPIO6A3_I2S_SDI, 590 591 GPIO6A2_SHIFT = 4, 592 GPIO6A2_MASK = 1, 593 GPIO6A2_GPIO = 0, 594 GPIO6A2_I2S_LRCKTX, 595 596 GPIO6A1_SHIFT = 2, 597 GPIO6A1_MASK = 1, 598 GPIO6A1_GPIO = 0, 599 GPIO6A1_I2S_LRCKRX, 600 601 GPIO6A0_SHIFT = 0, 602 GPIO6A0_MASK = 1, 603 GPIO6A0_GPIO = 0, 604 GPIO6A0_I2S_SCLK, 605 }; 606 607 /* GRF_GPIO6B_IOMUX */ 608 enum { 609 GPIO6B3_SHIFT = 6, 610 GPIO6B3_MASK = 1, 611 GPIO6B3_GPIO = 0, 612 GPIO6B3_SPDIF_TX, 613 614 GPIO6B2_SHIFT = 4, 615 GPIO6B2_MASK = 1, 616 GPIO6B2_GPIO = 0, 617 GPIO6B2_I2C1AUDIO_SCL, 618 619 GPIO6B1_SHIFT = 2, 620 GPIO6B1_MASK = 1, 621 GPIO6B1_GPIO = 0, 622 GPIO6B1_I2C1AUDIO_SDA, 623 624 GPIO6B0_SHIFT = 0, 625 GPIO6B0_MASK = 1, 626 GPIO6B0_GPIO = 0, 627 GPIO6B0_I2S_CLK, 628 }; 629 630 /* GRF_GPIO6C_IOMUX */ 631 enum { 632 GPIO6C6_SHIFT = 12, 633 GPIO6C6_MASK = 1, 634 GPIO6C6_GPIO = 0, 635 GPIO6C6_SDMMC0_DECTN, 636 637 GPIO6C5_SHIFT = 10, 638 GPIO6C5_MASK = 1, 639 GPIO6C5_GPIO = 0, 640 GPIO6C5_SDMMC0_CMD, 641 642 GPIO6C4_SHIFT = 8, 643 GPIO6C4_MASK = 3, 644 GPIO6C4_GPIO = 0, 645 GPIO6C4_SDMMC0_CLKOUT, 646 GPIO6C4_JTAG_TDO, 647 648 GPIO6C3_SHIFT = 6, 649 GPIO6C3_MASK = 3, 650 GPIO6C3_GPIO = 0, 651 GPIO6C3_SDMMC0_DATA3, 652 GPIO6C3_JTAG_TCK, 653 654 GPIO6C2_SHIFT = 4, 655 GPIO6C2_MASK = 3, 656 GPIO6C2_GPIO = 0, 657 GPIO6C2_SDMMC0_DATA2, 658 GPIO6C2_JTAG_TDI, 659 660 GPIO6C1_SHIFT = 2, 661 GPIO6C1_MASK = 3, 662 GPIO6C1_GPIO = 0, 663 GPIO6C1_SDMMC0_DATA1, 664 GPIO6C1_JTAG_TRSTN, 665 666 GPIO6C0_SHIFT = 0, 667 GPIO6C0_MASK = 3, 668 GPIO6C0_GPIO = 0, 669 GPIO6C0_SDMMC0_DATA0, 670 GPIO6C0_JTAG_TMS, 671 }; 672 673 /* GRF_GPIO7A_IOMUX */ 674 enum { 675 GPIO7A7_SHIFT = 14, 676 GPIO7A7_MASK = 3, 677 GPIO7A7_GPIO = 0, 678 GPIO7A7_UART3GPS_SIN, 679 GPIO7A7_GPS_MAG, 680 GPIO7A7_HSADCT1_DATA0, 681 682 GPIO7A1_SHIFT = 2, 683 GPIO7A1_MASK = 1, 684 GPIO7A1_GPIO = 0, 685 GPIO7A1_PWM_1, 686 687 GPIO7A0_SHIFT = 0, 688 GPIO7A0_MASK = 3, 689 GPIO7A0_GPIO = 0, 690 GPIO7A0_PWM_0, 691 GPIO7A0_VOP0_PWM, 692 GPIO7A0_VOP1_PWM, 693 }; 694 695 /* GRF_GPIO7B_IOMUX */ 696 enum { 697 GPIO7B7_SHIFT = 14, 698 GPIO7B7_MASK = 3, 699 GPIO7B7_GPIO = 0, 700 GPIO7B7_ISP_SHUTTERTRIG, 701 GPIO7B7_SPI1_TXD, 702 703 GPIO7B6_SHIFT = 12, 704 GPIO7B6_MASK = 3, 705 GPIO7B6_GPIO = 0, 706 GPIO7B6_ISP_PRELIGHTTRIG, 707 GPIO7B6_SPI1_RXD, 708 709 GPIO7B5_SHIFT = 10, 710 GPIO7B5_MASK = 3, 711 GPIO7B5_GPIO = 0, 712 GPIO7B5_ISP_FLASHTRIGOUT, 713 GPIO7B5_SPI1_CSN0, 714 715 GPIO7B4_SHIFT = 8, 716 GPIO7B4_MASK = 3, 717 GPIO7B4_GPIO = 0, 718 GPIO7B4_ISP_SHUTTEREN, 719 GPIO7B4_SPI1_CLK, 720 721 GPIO7B3_SHIFT = 6, 722 GPIO7B3_MASK = 3, 723 GPIO7B3_GPIO = 0, 724 GPIO7B3_USB_DRVVBUS1, 725 GPIO7B3_EDP_HOTPLUG, 726 727 GPIO7B2_SHIFT = 4, 728 GPIO7B2_MASK = 3, 729 GPIO7B2_GPIO = 0, 730 GPIO7B2_UART3GPS_RTSN, 731 GPIO7B2_USB_DRVVBUS0, 732 733 GPIO7B1_SHIFT = 2, 734 GPIO7B1_MASK = 3, 735 GPIO7B1_GPIO = 0, 736 GPIO7B1_UART3GPS_CTSN, 737 GPIO7B1_GPS_RFCLK, 738 GPIO7B1_GPST1_CLK, 739 740 GPIO7B0_SHIFT = 0, 741 GPIO7B0_MASK = 3, 742 GPIO7B0_GPIO = 0, 743 GPIO7B0_UART3GPS_SOUT, 744 GPIO7B0_GPS_SIG, 745 GPIO7B0_HSADCT1_DATA1, 746 }; 747 748 /* GRF_GPIO7CL_IOMUX */ 749 enum { 750 GPIO7C3_SHIFT = 12, 751 GPIO7C3_MASK = 3, 752 GPIO7C3_GPIO = 0, 753 GPIO7C3_I2C5HDMI_SDA, 754 GPIO7C3_EDPHDMII2C_SDA, 755 756 GPIO7C2_SHIFT = 8, 757 GPIO7C2_MASK = 1, 758 GPIO7C2_GPIO = 0, 759 GPIO7C2_I2C4TP_SCL, 760 761 GPIO7C1_SHIFT = 4, 762 GPIO7C1_MASK = 1, 763 GPIO7C1_GPIO = 0, 764 GPIO7C1_I2C4TP_SDA, 765 766 GPIO7C0_SHIFT = 0, 767 GPIO7C0_MASK = 3, 768 GPIO7C0_GPIO = 0, 769 GPIO7C0_ISP_FLASHTRIGIN, 770 GPIO7C0_EDPHDMI_CECINOUTT1, 771 }; 772 773 /* GRF_GPIO7CH_IOMUX */ 774 enum { 775 GPIO7C7_SHIFT = 12, 776 GPIO7C7_MASK = 7, 777 GPIO7C7_GPIO = 0, 778 GPIO7C7_UART2DBG_SOUT, 779 GPIO7C7_UART2DBG_SIROUT, 780 GPIO7C7_PWM_3, 781 GPIO7C7_EDPHDMI_CECINOUT, 782 783 GPIO7C6_SHIFT = 8, 784 GPIO7C6_MASK = 3, 785 GPIO7C6_GPIO = 0, 786 GPIO7C6_UART2DBG_SIN, 787 GPIO7C6_UART2DBG_SIRIN, 788 GPIO7C6_PWM_2, 789 790 GPIO7C4_SHIFT = 0, 791 GPIO7C4_MASK = 3, 792 GPIO7C4_GPIO = 0, 793 GPIO7C4_I2C5HDMI_SCL, 794 GPIO7C4_EDPHDMII2C_SCL, 795 }; 796 797 /* GRF_GPIO8A_IOMUX */ 798 enum { 799 GPIO8A7_SHIFT = 14, 800 GPIO8A7_MASK = 3, 801 GPIO8A7_GPIO = 0, 802 GPIO8A7_SPI2_CSN0, 803 GPIO8A7_SC_DETECT, 804 GPIO8A7_RESERVE, 805 806 GPIO8A6_SHIFT = 12, 807 GPIO8A6_MASK = 3, 808 GPIO8A6_GPIO = 0, 809 GPIO8A6_SPI2_CLK, 810 GPIO8A6_SC_IO, 811 GPIO8A6_RESERVE, 812 813 GPIO8A5_SHIFT = 10, 814 GPIO8A5_MASK = 3, 815 GPIO8A5_GPIO = 0, 816 GPIO8A5_I2C2SENSOR_SCL, 817 GPIO8A5_SC_CLK, 818 819 GPIO8A4_SHIFT = 8, 820 GPIO8A4_MASK = 3, 821 GPIO8A4_GPIO = 0, 822 GPIO8A4_I2C2SENSOR_SDA, 823 GPIO8A4_SC_RST, 824 825 GPIO8A3_SHIFT = 6, 826 GPIO8A3_MASK = 3, 827 GPIO8A3_GPIO = 0, 828 GPIO8A3_SPI2_CSN1, 829 GPIO8A3_SC_IOT1, 830 831 GPIO8A2_SHIFT = 4, 832 GPIO8A2_MASK = 1, 833 GPIO8A2_GPIO = 0, 834 GPIO8A2_SC_DETECTT1, 835 836 GPIO8A1_SHIFT = 2, 837 GPIO8A1_MASK = 3, 838 GPIO8A1_GPIO = 0, 839 GPIO8A1_PS2_DATA, 840 GPIO8A1_SC_VCC33V, 841 842 GPIO8A0_SHIFT = 0, 843 GPIO8A0_MASK = 3, 844 GPIO8A0_GPIO = 0, 845 GPIO8A0_PS2_CLK, 846 GPIO8A0_SC_VCC18V, 847 }; 848 849 /* GRF_GPIO8B_IOMUX */ 850 enum { 851 GPIO8B1_SHIFT = 2, 852 GPIO8B1_MASK = 3, 853 GPIO8B1_GPIO = 0, 854 GPIO8B1_SPI2_TXD, 855 GPIO8B1_SC_CLK, 856 857 GPIO8B0_SHIFT = 0, 858 GPIO8B0_MASK = 3, 859 GPIO8B0_GPIO = 0, 860 GPIO8B0_SPI2_RXD, 861 GPIO8B0_SC_RST, 862 }; 863 864 /* GRF_SOC_CON0 */ 865 enum { 866 PAUSE_MMC_PERI_SHIFT = 0xf, 867 PAUSE_MMC_PERI_MASK = 1, 868 869 PAUSE_EMEM_PERI_SHIFT = 0xe, 870 PAUSE_EMEM_PERI_MASK = 1, 871 872 PAUSE_USB_PERI_SHIFT = 0xd, 873 PAUSE_USB_PERI_MASK = 1, 874 875 GRF_FORCE_JTAG_SHIFT = 0xc, 876 GRF_FORCE_JTAG_MASK = 1, 877 878 GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb, 879 GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1, 880 881 GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa, 882 GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1, 883 884 DDR1_16BIT_EN_SHIFT = 9, 885 DDR1_16BIT_EN_MASK = 1, 886 887 DDR0_16BIT_EN_SHIFT = 8, 888 DDR0_16BIT_EN_MASK = 1, 889 890 VCODEC_SHIFT = 7, 891 VCODEC_MASK = 1, 892 VCODEC_SELECT_VEPU_ACLK = 0, 893 VCODEC_SELECT_VDPU_ACLK, 894 895 UPCTL1_C_ACTIVE_IN_SHIFT = 6, 896 UPCTL1_C_ACTIVE_IN_MASK = 1, 897 UPCTL1_C_ACTIVE_IN_MAY = 0, 898 UPCTL1_C_ACTIVE_IN_WILL, 899 900 UPCTL0_C_ACTIVE_IN_SHIFT = 5, 901 UPCTL0_C_ACTIVE_IN_MASK = 1, 902 UPCTL0_C_ACTIVE_IN_MAY = 0, 903 UPCTL0_C_ACTIVE_IN_WILL, 904 905 MSCH1_MAINDDR3_SHIFT = 4, 906 MSCH1_MAINDDR3_MASK = 1, 907 MSCH1_MAINDDR3_DDR3 = 1, 908 909 MSCH0_MAINDDR3_SHIFT = 3, 910 MSCH0_MAINDDR3_MASK = 1, 911 MSCH0_MAINDDR3_DDR3 = 1, 912 913 MSCH1_MAINPARTIALPOP_SHIFT = 2, 914 MSCH1_MAINPARTIALPOP_MASK = 1, 915 916 MSCH0_MAINPARTIALPOP_SHIFT = 1, 917 MSCH0_MAINPARTIALPOP_MASK = 1, 918 }; 919 920 /* GRF_SOC_CON1 */ 921 enum { 922 RK3288_RMII_MODE_SHIFT = 14, 923 RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), 924 RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT), 925 926 RK3288_GMAC_CLK_SEL_SHIFT = 12, 927 RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), 928 RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), 929 RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), 930 RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT), 931 932 RK3288_RMII_CLK_SEL_SHIFT = 11, 933 RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), 934 RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), 935 RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), 936 937 GMAC_SPEED_SHIFT = 0xa, 938 GMAC_SPEED_MASK = 1, 939 GMAC_SPEED_10M = 0, 940 GMAC_SPEED_100M, 941 942 GMAC_FLOWCTRL_SHIFT = 0x9, 943 GMAC_FLOWCTRL_MASK = 1, 944 945 RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, 946 RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 947 RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 948 RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), 949 950 HOST_REMAP_SHIFT = 0x5, 951 HOST_REMAP_MASK = 1 952 }; 953 954 /* GRF_SOC_CON2 */ 955 enum { 956 UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, 957 UPCTL1_LPDDR3_ODT_EN_MASK = 1, 958 UPCTL1_LPDDR3_ODT_EN_ODT = 1, 959 960 UPCTL1_BST_DIABLE_SHIFT = 0xc, 961 UPCTL1_BST_DIABLE_MASK = 1, 962 UPCTL1_BST_DIABLE_DISABLE = 1, 963 964 LPDDR3_EN1_SHIFT = 0xb, 965 LPDDR3_EN1_MASK = 1, 966 LPDDR3_EN1_LPDDR3 = 1, 967 968 UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa, 969 UPCTL0_LPDDR3_ODT_EN_MASK = 1, 970 UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1, 971 972 UPCTL0_BST_DIABLE_SHIFT = 9, 973 UPCTL0_BST_DIABLE_MASK = 1, 974 UPCTL0_BST_DIABLE_DISABLE = 1, 975 976 LPDDR3_EN0_SHIFT = 8, 977 LPDDR3_EN0_MASK = 1, 978 LPDDR3_EN0_LPDDR3 = 1, 979 980 GRF_POC_FLASH0_CTRL_SHIFT = 7, 981 GRF_POC_FLASH0_CTRL_MASK = 1, 982 GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0, 983 GRF_POC_FLASH0_CTRL_GRF_IO_VSEL, 984 985 SIMCARD_MUX_SHIFT = 6, 986 SIMCARD_MUX_MASK = 1, 987 SIMCARD_MUX_USE_A = 1, 988 SIMCARD_MUX_USE_B = 0, 989 990 GRF_SPDIF_2CH_EN_SHIFT = 1, 991 GRF_SPDIF_2CH_EN_MASK = 1, 992 GRF_SPDIF_2CH_EN_8CH = 0, 993 GRF_SPDIF_2CH_EN_2CH, 994 995 PWM_SHIFT = 0, 996 PWM_MASK = 1, 997 PWM_RK = 1, 998 PWM_PWM = 0, 999 }; 1000 1001 /* GRF_SOC_CON3 */ 1002 enum { 1003 RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, 1004 RK3288_RXCLK_DLY_ENA_GMAC_MASK = 1005 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), 1006 RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 1007 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = 1008 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), 1009 1010 RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, 1011 RK3288_TXCLK_DLY_ENA_GMAC_MASK = 1012 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), 1013 RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 1014 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = 1015 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), 1016 1017 RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 1018 RK3288_CLK_RX_DL_CFG_GMAC_MASK = 1019 (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), 1020 1021 RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 1022 RK3288_CLK_TX_DL_CFG_GMAC_MASK = 1023 (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), 1024 }; 1025 1026 /* GRF_SOC_CON6 */ 1027 enum GRF_SOC_CON6 { 1028 RK3288_HDMI_EDP_SEL_SHIFT = 0xf, 1029 RK3288_HDMI_EDP_SEL_MASK = 1030 1 << RK3288_HDMI_EDP_SEL_SHIFT, 1031 RK3288_HDMI_EDP_SEL_EDP = 0, 1032 RK3288_HDMI_EDP_SEL_HDMI, 1033 1034 RK3288_DSI0_DPICOLORM_SHIFT = 0x8, 1035 RK3288_DSI0_DPICOLORM_MASK = 1036 1 << RK3288_DSI0_DPICOLORM_SHIFT, 1037 1038 RK3288_DSI0_DPISHUTDN_SHIFT = 0x7, 1039 RK3288_DSI0_DPISHUTDN_MASK = 1040 1 << RK3288_DSI0_DPISHUTDN_SHIFT, 1041 1042 RK3288_DSI0_LCDC_SEL_SHIFT = 0x6, 1043 RK3288_DSI0_LCDC_SEL_MASK = 1044 1 << RK3288_DSI0_LCDC_SEL_SHIFT, 1045 RK3288_DSI0_LCDC_SEL_BIG = 0, 1046 RK3288_DSI0_LCDC_SEL_LIT = 1, 1047 1048 RK3288_EDP_LCDC_SEL_SHIFT = 0x5, 1049 RK3288_EDP_LCDC_SEL_MASK = 1050 1 << RK3288_EDP_LCDC_SEL_SHIFT, 1051 RK3288_EDP_LCDC_SEL_BIG = 0, 1052 RK3288_EDP_LCDC_SEL_LIT = 1, 1053 1054 RK3288_HDMI_LCDC_SEL_SHIFT = 0x4, 1055 RK3288_HDMI_LCDC_SEL_MASK = 1056 1 << RK3288_HDMI_LCDC_SEL_SHIFT, 1057 RK3288_HDMI_LCDC_SEL_BIG = 0, 1058 RK3288_HDMI_LCDC_SEL_LIT = 1, 1059 1060 RK3288_LVDS_LCDC_SEL_SHIFT = 0x3, 1061 RK3288_LVDS_LCDC_SEL_MASK = 1062 1 << RK3288_LVDS_LCDC_SEL_SHIFT, 1063 RK3288_LVDS_LCDC_SEL_BIG = 0, 1064 RK3288_LVDS_LCDC_SEL_LIT = 1, 1065 }; 1066 1067 /* RK3288_SOC_CON8 */ 1068 enum GRF_SOC_CON8 { 1069 RK3288_DPHY_TX0_RXMODE_SHIFT = 4, 1070 RK3288_DPHY_TX0_RXMODE_MASK = 1071 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT, 1072 RK3288_DPHY_TX0_RXMODE_EN = 0xf, 1073 RK3288_DPHY_TX0_RXMODE_DIS = 0, 1074 1075 RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8, 1076 RK3288_DPHY_TX0_TXSTOPMODE_MASK = 1077 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT, 1078 RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf, 1079 RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0, 1080 1081 RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0, 1082 RK3288_DPHY_TX0_TURNREQUEST_MASK = 1083 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT, 1084 RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf, 1085 RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, 1086 }; 1087 1088 /* GRF_IO_VSEL */ 1089 enum { 1090 GPIO1830_V18SEL_SHIFT = 9, 1091 GPIO1830_V18SEL_MASK = 1, 1092 GPIO1830_V18SEL_3_3V = 0, 1093 GPIO1830_V18SEL_1_8V, 1094 1095 GPIO30_V18SEL_SHIFT = 8, 1096 GPIO30_V18SEL_MASK = 1, 1097 GPIO30_V18SEL_3_3V = 0, 1098 GPIO30_V18SEL_1_8V, 1099 1100 SDCARD_V18SEL_SHIFT = 7, 1101 SDCARD_V18SEL_MASK = 1, 1102 SDCARD_V18SEL_3_3V = 0, 1103 SDCARD_V18SEL_1_8V, 1104 1105 AUDIO_V18SEL_SHIFT = 6, 1106 AUDIO_V18SEL_MASK = 1, 1107 AUDIO_V18SEL_3_3V = 0, 1108 AUDIO_V18SEL_1_8V, 1109 1110 BB_V18SEL_SHIFT = 5, 1111 BB_V18SEL_MASK = 1, 1112 BB_V18SEL_3_3V = 0, 1113 BB_V18SEL_1_8V, 1114 1115 WIFI_V18SEL_SHIFT = 4, 1116 WIFI_V18SEL_MASK = 1, 1117 WIFI_V18SEL_3_3V = 0, 1118 WIFI_V18SEL_1_8V, 1119 1120 FLASH1_V18SEL_SHIFT = 3, 1121 FLASH1_V18SEL_MASK = 1, 1122 FLASH1_V18SEL_3_3V = 0, 1123 FLASH1_V18SEL_1_8V, 1124 1125 FLASH0_V18SEL_SHIFT = 2, 1126 FLASH0_V18SEL_MASK = 1, 1127 FLASH0_V18SEL_3_3V = 0, 1128 FLASH0_V18SEL_1_8V, 1129 1130 DVP_V18SEL_SHIFT = 1, 1131 DVP_V18SEL_MASK = 1, 1132 DVP_V18SEL_3_3V = 0, 1133 DVP_V18SEL_1_8V, 1134 1135 LCDC_V18SEL_SHIFT = 0, 1136 LCDC_V18SEL_MASK = 1, 1137 LCDC_V18SEL_3_3V = 0, 1138 LCDC_V18SEL_1_8V, 1139 }; 1140 1141 /* GPIO Bias settings */ 1142 enum GPIO_BIAS { 1143 GPIO_BIAS_2MA = 0, 1144 GPIO_BIAS_4MA, 1145 GPIO_BIAS_8MA, 1146 GPIO_BIAS_12MA, 1147 }; 1148 1149 #define GPIO_BIAS_MASK 0x3 1150 #define GPIO_BIAS_SHIFT(x) ((x) * 2) 1151 1152 #define GPIO_PULL_MASK 0x3 1153 #define GPIO_PULL_SHIFT(x) ((x) * 2) 1154 1155 #endif 1156