1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * DWMAC4 Header file.
4 *
5 * Copyright (C) 2015 STMicroelectronics Ltd
6 *
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 */
9
10 #ifndef __DWMAC4_H__
11 #define __DWMAC4_H__
12
13 #include "common.h"
14
15 /* MAC registers */
16 #define GMAC_CONFIG 0x00000000
17 #define GMAC_EXT_CONFIG 0x00000004
18 #define GMAC_PACKET_FILTER 0x00000008
19 #define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
20 #define GMAC_VLAN_TAG 0x00000050
21 #define GMAC_VLAN_TAG_DATA 0x00000054
22 #define GMAC_VLAN_HASH_TABLE 0x00000058
23 #define GMAC_RX_FLOW_CTRL 0x00000090
24 #define GMAC_VLAN_INCL 0x00000060
25 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
26 #define GMAC_TXQ_PRTY_MAP0 0x98
27 #define GMAC_TXQ_PRTY_MAP1 0x9C
28 #define GMAC_RXQ_CTRL0 0x000000a0
29 #define GMAC_RXQ_CTRL1 0x000000a4
30 #define GMAC_RXQ_CTRL2 0x000000a8
31 #define GMAC_RXQ_CTRL3 0x000000ac
32 #define GMAC_INT_STATUS 0x000000b0
33 #define GMAC_INT_EN 0x000000b4
34 #define GMAC_1US_TIC_COUNTER 0x000000dc
35 #define GMAC_PCS_BASE 0x000000e0
36 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
37 #define GMAC_PMT 0x000000c0
38 #define GMAC_DEBUG 0x00000114
39 #define GMAC_HW_FEATURE0 0x0000011c
40 #define GMAC_HW_FEATURE1 0x00000120
41 #define GMAC_HW_FEATURE2 0x00000124
42 #define GMAC_HW_FEATURE3 0x00000128
43 #define GMAC_MDIO_ADDR 0x00000200
44 #define GMAC_MDIO_DATA 0x00000204
45 #define GMAC_GPIO_STATUS 0x0000020C
46 #define GMAC_ARP_ADDR 0x00000210
47 #define GMAC_EXT_CFG1 0x00000238
48 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
49 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
50 #define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30)
51 #define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30)
52 #define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30)
53 #define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30)
54 #define GMAC_TIMESTAMP_STATUS 0x00000b20
55
56 /* RX Queues Routing */
57 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
58 #define GMAC_RXQCTRL_AVCPQ_SHIFT 0
59 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
60 #define GMAC_RXQCTRL_PTPQ_SHIFT 4
61 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
62 #define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
63 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
64 #define GMAC_RXQCTRL_UPQ_SHIFT 12
65 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
66 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16
67 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
68 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
69 #define GMAC_RXQCTRL_TACPQE BIT(21)
70 #define GMAC_RXQCTRL_TACPQE_SHIFT 21
71 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
72 #define GMAC_RXQCTRL_FPRQ_SHIFT 24
73
74 /* MAC Packet Filtering */
75 #define GMAC_PACKET_FILTER_PR BIT(0)
76 #define GMAC_PACKET_FILTER_HMC BIT(2)
77 #define GMAC_PACKET_FILTER_PM BIT(4)
78 #define GMAC_PACKET_FILTER_PCF BIT(7)
79 #define GMAC_PACKET_FILTER_HPF BIT(10)
80 #define GMAC_PACKET_FILTER_VTFE BIT(16)
81 #define GMAC_PACKET_FILTER_IPFE BIT(20)
82 #define GMAC_PACKET_FILTER_RA BIT(31)
83
84 #define GMAC_MAX_PERFECT_ADDRESSES 128
85
86 /* MAC VLAN */
87 #define GMAC_VLAN_EDVLP BIT(26)
88 #define GMAC_VLAN_VTHM BIT(25)
89 #define GMAC_VLAN_DOVLTC BIT(20)
90 #define GMAC_VLAN_ESVL BIT(18)
91 #define GMAC_VLAN_ETV BIT(16)
92 #define GMAC_VLAN_VID GENMASK(15, 0)
93 #define GMAC_VLAN_VLTI BIT(20)
94 #define GMAC_VLAN_CSVL BIT(19)
95 #define GMAC_VLAN_VLC GENMASK(17, 16)
96 #define GMAC_VLAN_VLC_SHIFT 16
97 #define GMAC_VLAN_VLHT GENMASK(15, 0)
98
99 /* MAC VLAN Tag */
100 #define GMAC_VLAN_TAG_VID GENMASK(15, 0)
101 #define GMAC_VLAN_TAG_ETV BIT(16)
102
103 /* MAC VLAN Tag Control */
104 #define GMAC_VLAN_TAG_CTRL_OB BIT(0)
105 #define GMAC_VLAN_TAG_CTRL_CT BIT(1)
106 #define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)
107 #define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2
108 #define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21)
109 #define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21
110 #define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24)
111
112 #define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
113 #define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
114 #define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
115 #define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
116
117 /* MAC VLAN Tag Data/Filter */
118 #define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0)
119 #define GMAC_VLAN_TAG_DATA_VEN BIT(16)
120 #define GMAC_VLAN_TAG_DATA_ETV BIT(17)
121
122 /* MAC RX Queue Enable */
123 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
124 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
125 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
126
127 /* MAC Flow Control RX */
128 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
129
130 /* RX Queues Priorities */
131 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
132 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
133
134 /* TX Queues Priorities */
135 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
136 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
137
138 /* MAC Flow Control TX */
139 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
140 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
141
142 /* MAC Interrupt bitmap*/
143 #define GMAC_INT_RGSMIIS BIT(0)
144 #define GMAC_INT_PCS_LINK BIT(1)
145 #define GMAC_INT_PCS_ANE BIT(2)
146 #define GMAC_INT_PCS_PHYIS BIT(3)
147 #define GMAC_INT_PMT_EN BIT(4)
148 #define GMAC_INT_LPI_EN BIT(5)
149 #define GMAC_INT_TSIE BIT(12)
150
151 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
152 GMAC_INT_PCS_ANE)
153
154 #define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \
155 GMAC_INT_TSIE)
156
157 enum dwmac4_irq_status {
158 time_stamp_irq = 0x00001000,
159 mmc_rx_csum_offload_irq = 0x00000800,
160 mmc_tx_irq = 0x00000400,
161 mmc_rx_irq = 0x00000200,
162 mmc_irq = 0x00000100,
163 lpi_irq = 0x00000020,
164 pmt_irq = 0x00000010,
165 };
166
167 /* MAC PMT bitmap */
168 enum power_event {
169 pointer_reset = 0x80000000,
170 global_unicast = 0x00000200,
171 wake_up_rx_frame = 0x00000040,
172 magic_frame = 0x00000020,
173 wake_up_frame_en = 0x00000004,
174 magic_pkt_en = 0x00000002,
175 power_down = 0x00000001,
176 };
177
178 /* Energy Efficient Ethernet (EEE) for GMAC4
179 *
180 * LPI status, timer and control register offset
181 */
182 #define GMAC4_LPI_CTRL_STATUS 0xd0
183 #define GMAC4_LPI_TIMER_CTRL 0xd4
184 #define GMAC4_LPI_ENTRY_TIMER 0xd8
185 #define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc
186
187 /* LPI control and status defines */
188 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
189 #define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
190 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
191 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
192 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
193 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
194 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
195 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
196 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
197
198 /* MAC Debug bitmap */
199 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
200 #define GMAC_DEBUG_TFCSTS_SHIFT 17
201 #define GMAC_DEBUG_TFCSTS_IDLE 0
202 #define GMAC_DEBUG_TFCSTS_WAIT 1
203 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
204 #define GMAC_DEBUG_TFCSTS_XFER 3
205 #define GMAC_DEBUG_TPESTS BIT(16)
206 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
207 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1
208 #define GMAC_DEBUG_RPESTS BIT(0)
209
210 /* MAC config */
211 #define GMAC_CONFIG_ARPEN BIT(31)
212 #define GMAC_CONFIG_SARC GENMASK(30, 28)
213 #define GMAC_CONFIG_SARC_SHIFT 28
214 #define GMAC_CONFIG_IPC BIT(27)
215 #define GMAC_CONFIG_IPG GENMASK(26, 24)
216 #define GMAC_CONFIG_IPG_SHIFT 24
217 #define GMAC_CONFIG_2K BIT(22)
218 #define GMAC_CONFIG_ACS BIT(20)
219 #define GMAC_CONFIG_BE BIT(18)
220 #define GMAC_CONFIG_JD BIT(17)
221 #define GMAC_CONFIG_JE BIT(16)
222 #define GMAC_CONFIG_PS BIT(15)
223 #define GMAC_CONFIG_FES BIT(14)
224 #define GMAC_CONFIG_FES_SHIFT 14
225 #define GMAC_CONFIG_DM BIT(13)
226 #define GMAC_CONFIG_LM BIT(12)
227 #define GMAC_CONFIG_DCRS BIT(9)
228 #define GMAC_CONFIG_TE BIT(1)
229 #define GMAC_CONFIG_RE BIT(0)
230
231 /* MAC extended config */
232 #define GMAC_CONFIG_EIPG GENMASK(29, 25)
233 #define GMAC_CONFIG_EIPG_SHIFT 25
234 #define GMAC_CONFIG_EIPG_EN BIT(24)
235 #define GMAC_CONFIG_HDSMS GENMASK(22, 20)
236 #define GMAC_CONFIG_HDSMS_SHIFT 20
237 #define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
238
239 /* MAC HW features0 bitmap */
240 #define GMAC_HW_FEAT_SAVLANINS BIT(27)
241 #define GMAC_HW_FEAT_ADDMAC BIT(18)
242 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
243 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
244 #define GMAC_HW_FEAT_EEESEL BIT(13)
245 #define GMAC_HW_FEAT_TSSEL BIT(12)
246 #define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
247 #define GMAC_HW_FEAT_MMCSEL BIT(8)
248 #define GMAC_HW_FEAT_MGKSEL BIT(7)
249 #define GMAC_HW_FEAT_RWKSEL BIT(6)
250 #define GMAC_HW_FEAT_SMASEL BIT(5)
251 #define GMAC_HW_FEAT_VLHASH BIT(4)
252 #define GMAC_HW_FEAT_PCSSEL BIT(3)
253 #define GMAC_HW_FEAT_HDSEL BIT(2)
254 #define GMAC_HW_FEAT_GMIISEL BIT(1)
255 #define GMAC_HW_FEAT_MIISEL BIT(0)
256
257 /* MAC HW features1 bitmap */
258 #define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27)
259 #define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
260 #define GMAC_HW_FEAT_AVSEL BIT(20)
261 #define GMAC_HW_TSOEN BIT(18)
262 #define GMAC_HW_FEAT_SPHEN BIT(17)
263 #define GMAC_HW_ADDR64 GENMASK(15, 14)
264 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
265 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
266
267 /* MAC HW features2 bitmap */
268 #define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28)
269 #define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)
270 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
271 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
272 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
273 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
274
275 /* MAC HW features3 bitmap */
276 #define GMAC_HW_FEAT_ASP GENMASK(29, 28)
277 #define GMAC_HW_FEAT_TBSSEL BIT(27)
278 #define GMAC_HW_FEAT_FPESEL BIT(26)
279 #define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
280 #define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)
281 #define GMAC_HW_FEAT_ESTSEL BIT(16)
282 #define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
283 #define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
284 #define GMAC_HW_FEAT_FRPSEL BIT(10)
285 #define GMAC_HW_FEAT_DVLAN BIT(5)
286 #define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
287
288 /* MAC extended config 1 */
289 #define GMAC_CONFIG1_SAVE_EN BIT(24)
290 #define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v)
291
292 /* GMAC GPIO Status reg */
293 #define GMAC_GPO0 BIT(16)
294 #define GMAC_GPO1 BIT(17)
295 #define GMAC_GPO2 BIT(18)
296 #define GMAC_GPO3 BIT(19)
297
298 /* MAC HW ADDR regs */
299 #define GMAC_HI_DCS GENMASK(18, 16)
300 #define GMAC_HI_DCS_SHIFT 16
301 #define GMAC_HI_REG_AE BIT(31)
302
303 /* L3/L4 Filters regs */
304 #define GMAC_L4DPIM0 BIT(21)
305 #define GMAC_L4DPM0 BIT(20)
306 #define GMAC_L4SPIM0 BIT(19)
307 #define GMAC_L4SPM0 BIT(18)
308 #define GMAC_L4PEN0 BIT(16)
309 #define GMAC_L3DAIM0 BIT(5)
310 #define GMAC_L3DAM0 BIT(4)
311 #define GMAC_L3SAIM0 BIT(3)
312 #define GMAC_L3SAM0 BIT(2)
313 #define GMAC_L3PEN0 BIT(0)
314 #define GMAC_L4DP0 GENMASK(31, 16)
315 #define GMAC_L4DP0_SHIFT 16
316 #define GMAC_L4SP0 GENMASK(15, 0)
317
318 /* MAC Timestamp Status */
319 #define GMAC_TIMESTAMP_AUXTSTRIG BIT(2)
320 #define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
321 #define GMAC_TIMESTAMP_ATSNS_SHIFT 25
322
323 /* MTL registers */
324 #define MTL_OPERATION_MODE 0x00000c00
325 #define MTL_FRPE BIT(15)
326 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
327 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
328 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
329 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
330 #define MTL_OPERATION_SCHALG_SP (0x3 << 5)
331 #define MTL_OPERATION_RAA BIT(2)
332 #define MTL_OPERATION_RAA_SP (0x0 << 2)
333 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
334
335 #define MTL_INT_STATUS 0x00000c20
336 #define MTL_INT_QX(x) BIT(x)
337
338 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
339 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
340 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x))
341 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
342
343 #define MTL_CHAN_BASE_ADDR 0x00000d00
344 #define MTL_CHAN_BASE_OFFSET 0x40
345
mtl_chanx_base_addr(const struct dwmac4_addrs * addrs,const u32 x)346 static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs,
347 const u32 x)
348 {
349 u32 addr;
350
351 if (addrs)
352 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);
353 else
354 addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET);
355
356 return addr;
357 }
358
359 #define MTL_CHAN_TX_OP_MODE(addrs, x) mtl_chanx_base_addr(addrs, x)
360 #define MTL_CHAN_TX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x8)
361 #define MTL_CHAN_INT_CTRL(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x2c)
362 #define MTL_CHAN_RX_OP_MODE(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x30)
363 #define MTL_CHAN_RX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x38)
364
365 #define MTL_OP_MODE_RSF BIT(5)
366 #define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
367 #define MTL_OP_MODE_TXQEN_AV BIT(2)
368 #define MTL_OP_MODE_TXQEN BIT(3)
369 #define MTL_OP_MODE_TSF BIT(1)
370
371 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
372 #define MTL_OP_MODE_TQS_SHIFT 16
373
374 #define MTL_OP_MODE_TTC_MASK 0x70
375 #define MTL_OP_MODE_TTC_SHIFT 4
376
377 #define MTL_OP_MODE_TTC_32 0
378 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
379 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
380 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
381 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
382 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
383 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
384 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
385
386 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
387 #define MTL_OP_MODE_RQS_SHIFT 20
388
389 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
390 #define MTL_OP_MODE_RFD_SHIFT 14
391
392 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
393 #define MTL_OP_MODE_RFA_SHIFT 8
394
395 #define MTL_OP_MODE_EHFC BIT(7)
396
397 #define MTL_OP_MODE_RTC_MASK 0x18
398 #define MTL_OP_MODE_RTC_SHIFT 3
399
400 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
401 #define MTL_OP_MODE_RTC_64 0
402 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
403 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
404
405 /* MTL ETS Control register */
406 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
407 #define MTL_ETS_CTRL_BASE_OFFSET 0x40
408
mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs * addrs,const u32 x)409 static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs,
410 const u32 x)
411 {
412 u32 addr;
413
414 if (addrs)
415 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);
416 else
417 addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET);
418
419 return addr;
420 }
421
422 #define MTL_ETS_CTRL_CC BIT(3)
423 #define MTL_ETS_CTRL_AVALG BIT(2)
424
425 /* MTL Queue Quantum Weight */
426 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
427 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
428
mtl_txqx_weight_base_addr(const struct dwmac4_addrs * addrs,const u32 x)429 static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs,
430 const u32 x)
431 {
432 u32 addr;
433
434 if (addrs)
435 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);
436 else
437 addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET);
438
439 return addr;
440 }
441
442 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
443
444 /* MTL sendSlopeCredit register */
445 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
446 #define MTL_SEND_SLP_CRED_OFFSET 0x40
447
mtl_send_slp_credx_base_addr(const struct dwmac4_addrs * addrs,const u32 x)448 static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs,
449 const u32 x)
450 {
451 u32 addr;
452
453 if (addrs)
454 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);
455 else
456 addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET);
457
458 return addr;
459 }
460
461 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
462
463 /* MTL hiCredit register */
464 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
465 #define MTL_HIGH_CRED_OFFSET 0x40
466
mtl_high_credx_base_addr(const struct dwmac4_addrs * addrs,const u32 x)467 static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs,
468 const u32 x)
469 {
470 u32 addr;
471
472 if (addrs)
473 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);
474 else
475 addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET);
476
477 return addr;
478 }
479
480 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
481
482 /* MTL loCredit register */
483 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24
484 #define MTL_LOW_CRED_OFFSET 0x40
485
mtl_low_credx_base_addr(const struct dwmac4_addrs * addrs,const u32 x)486 static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
487 const u32 x)
488 {
489 u32 addr;
490
491 if (addrs)
492 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);
493 else
494 addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET);
495
496 return addr;
497 }
498
499 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
500
501 /* MTL debug */
502 #define MTL_DEBUG_TXSTSFSTS BIT(5)
503 #define MTL_DEBUG_TXFSTS BIT(4)
504 #define MTL_DEBUG_TWCSTS BIT(3)
505
506 /* MTL debug: Tx FIFO Read Controller Status */
507 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
508 #define MTL_DEBUG_TRCSTS_SHIFT 1
509 #define MTL_DEBUG_TRCSTS_IDLE 0
510 #define MTL_DEBUG_TRCSTS_READ 1
511 #define MTL_DEBUG_TRCSTS_TXW 2
512 #define MTL_DEBUG_TRCSTS_WRITE 3
513 #define MTL_DEBUG_TXPAUSED BIT(0)
514
515 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
516 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
517 #define MTL_DEBUG_RXFSTS_SHIFT 4
518 #define MTL_DEBUG_RXFSTS_EMPTY 0
519 #define MTL_DEBUG_RXFSTS_BT 1
520 #define MTL_DEBUG_RXFSTS_AT 2
521 #define MTL_DEBUG_RXFSTS_FULL 3
522 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
523 #define MTL_DEBUG_RRCSTS_SHIFT 1
524 #define MTL_DEBUG_RRCSTS_IDLE 0
525 #define MTL_DEBUG_RRCSTS_RDATA 1
526 #define MTL_DEBUG_RRCSTS_RSTAT 2
527 #define MTL_DEBUG_RRCSTS_FLUSH 3
528 #define MTL_DEBUG_RWCSTS BIT(0)
529
530 /* MTL interrupt */
531 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
532 #define MTL_RX_OVERFLOW_INT BIT(16)
533
534 /* Default operating mode of the MAC */
535 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
536 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
537 GMAC_CONFIG_JE)
538
539 /* To dump the core regs excluding the Address Registers */
540 #define GMAC_REG_NUM 132
541
542 /* MTL debug */
543 #define MTL_DEBUG_TXSTSFSTS BIT(5)
544 #define MTL_DEBUG_TXFSTS BIT(4)
545 #define MTL_DEBUG_TWCSTS BIT(3)
546
547 /* MTL debug: Tx FIFO Read Controller Status */
548 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
549 #define MTL_DEBUG_TRCSTS_SHIFT 1
550 #define MTL_DEBUG_TRCSTS_IDLE 0
551 #define MTL_DEBUG_TRCSTS_READ 1
552 #define MTL_DEBUG_TRCSTS_TXW 2
553 #define MTL_DEBUG_TRCSTS_WRITE 3
554 #define MTL_DEBUG_TXPAUSED BIT(0)
555
556 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
557 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
558 #define MTL_DEBUG_RXFSTS_SHIFT 4
559 #define MTL_DEBUG_RXFSTS_EMPTY 0
560 #define MTL_DEBUG_RXFSTS_BT 1
561 #define MTL_DEBUG_RXFSTS_AT 2
562 #define MTL_DEBUG_RXFSTS_FULL 3
563 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
564 #define MTL_DEBUG_RRCSTS_SHIFT 1
565 #define MTL_DEBUG_RRCSTS_IDLE 0
566 #define MTL_DEBUG_RRCSTS_RDATA 1
567 #define MTL_DEBUG_RRCSTS_RSTAT 2
568 #define MTL_DEBUG_RRCSTS_FLUSH 3
569 #define MTL_DEBUG_RWCSTS BIT(0)
570
571 /* SGMII/RGMII status register */
572 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
573 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
574 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
575 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
576 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
577 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
578 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
579 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
580 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
581 /* LNKMOD */
582 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
583 /* LNKSPEED */
584 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
585 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
586 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
587
588 extern const struct stmmac_dma_ops dwmac4_dma_ops;
589 extern const struct stmmac_dma_ops dwmac410_dma_ops;
590 #endif /* __DWMAC4_H__ */
591