1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016-2018 NXP 4 * Copyright 2015, Freescale Semiconductor 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ 20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 21 22 #ifdef CONFIG_ARCH_LS2080A 23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 24 #define SRDS_MAX_LANES 8 25 #define CONFIG_SYS_PAGE_SIZE 0x10000 26 #ifndef L1_CACHE_BYTES 27 #define L1_CACHE_SHIFT 6 28 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 29 #endif 30 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 34 35 /* DDR */ 36 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 38 39 #define CONFIG_SYS_FSL_CCSR_GUR_LE 40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 41 #define CONFIG_SYS_FSL_ESDHC_LE 42 #define CONFIG_SYS_FSL_IFC_LE 43 #define CONFIG_SYS_FSL_PEX_LUT_LE 44 45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 46 47 /* Generic Interrupt Controller Definitions */ 48 #define GICD_BASE 0x06000000 49 #define GICR_BASE 0x06100000 50 51 /* SMMU Defintions */ 52 #define SMMU_BASE 0x05000000 /* GR0 Base */ 53 54 /* SFP */ 55 #define CONFIG_SYS_FSL_SFP_VER_3_4 56 #define CONFIG_SYS_FSL_SFP_LE 57 #define CONFIG_SYS_FSL_SRK_LE 58 59 /* Security Monitor */ 60 #define CONFIG_SYS_FSL_SEC_MON_LE 61 62 /* Secure Boot */ 63 #define CONFIG_ESBC_HDR_LS 64 65 /* DCFG - GUR */ 66 #define CONFIG_SYS_FSL_CCSR_GUR_LE 67 68 /* Cache Coherent Interconnect */ 69 #define CCI_MN_BASE 0x04000000 70 #define CCI_MN_RNF_NODEID_LIST 0x180 71 #define CCI_MN_DVM_DOMAIN_CTL 0x200 72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 73 74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 80 81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 87 88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 91 92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 93 94 /* TZ Protection Controller Definitions */ 95 #define TZPC_BASE 0x02200000 96 #define TZPCR0SIZE_BASE (TZPC_BASE) 97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 106 107 #define DCSR_CGACRE5 0x700070914ULL 108 #define EPU_EPCMPR5 0x700060914ULL 109 #define EPU_EPCCR5 0x700060814ULL 110 #define EPU_EPSMCR5 0x700060228ULL 111 #define EPU_EPECR5 0x700060314ULL 112 #define EPU_EPCTR5 0x700060a14ULL 113 #define EPU_EPGCR 0x700060000ULL 114 115 #define CONFIG_SYS_FSL_ERRATUM_A008751 116 117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 118 119 #elif defined(CONFIG_ARCH_LS1088A) 120 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 122 #define CONFIG_GICV3 123 #define CONFIG_SYS_PAGE_SIZE 0x10000 124 125 #define SRDS_MAX_LANES 4 126 127 /* TZ Protection Controller Definitions */ 128 #define TZPC_BASE 0x02200000 129 #define TZPCR0SIZE_BASE (TZPC_BASE) 130 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 131 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 132 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 133 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 134 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 135 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 136 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 137 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 138 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 139 140 /* Generic Interrupt Controller Definitions */ 141 #define GICD_BASE 0x06000000 142 #define GICR_BASE 0x06100000 143 144 /* SMMU Defintions */ 145 #define SMMU_BASE 0x05000000 /* GR0 Base */ 146 147 /* DDR */ 148 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 149 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 150 151 #define CONFIG_SYS_FSL_CCSR_GUR_LE 152 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 153 #define CONFIG_SYS_FSL_ESDHC_LE 154 #define CONFIG_SYS_FSL_IFC_LE 155 #define CONFIG_SYS_FSL_PEX_LUT_LE 156 157 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 158 159 /* SFP */ 160 #define CONFIG_SYS_FSL_SFP_VER_3_4 161 #define CONFIG_SYS_FSL_SFP_LE 162 #define CONFIG_SYS_FSL_SRK_LE 163 164 /* Security Monitor */ 165 #define CONFIG_SYS_FSL_SEC_MON_LE 166 167 /* Secure Boot */ 168 #define CONFIG_ESBC_HDR_LS 169 170 /* DCFG - GUR */ 171 #define CONFIG_SYS_FSL_CCSR_GUR_LE 172 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 173 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 174 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 175 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 176 177 /* LX2160A Soc Support */ 178 #elif defined(CONFIG_ARCH_LX2160A) 179 #define TZPC_BASE 0x02200000 180 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 181 #define CONFIG_SYS_I2C 182 #define CONFIG_SYS_I2C_EARLY_INIT 183 #define SRDS_MAX_LANES 8 184 #ifndef L1_CACHE_BYTES 185 #define L1_CACHE_SHIFT 6 186 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 187 #endif 188 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 189 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } 190 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 191 192 #define CONFIG_SYS_PAGE_SIZE 0x10000 193 194 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 195 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 196 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 197 198 /* DDR */ 199 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 200 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 201 202 #define CONFIG_SYS_FSL_CCSR_GUR_LE 203 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 204 #define CONFIG_SYS_FSL_ESDHC_LE 205 #define CONFIG_SYS_FSL_PEX_LUT_LE 206 207 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 208 209 /* Generic Interrupt Controller Definitions */ 210 #define GICD_BASE 0x06000000 211 #define GICR_BASE 0x06200000 212 213 /* SMMU Definitions */ 214 #define SMMU_BASE 0x05000000 /* GR0 Base */ 215 216 /* SFP */ 217 #define CONFIG_SYS_FSL_SFP_VER_3_4 218 #define CONFIG_SYS_FSL_SFP_LE 219 #define CONFIG_SYS_FSL_SRK_LE 220 221 /* Security Monitor */ 222 #define CONFIG_SYS_FSL_SEC_MON_LE 223 224 /* Secure Boot */ 225 #define CONFIG_ESBC_HDR_LS 226 227 /* DCFG - GUR */ 228 #define CONFIG_SYS_FSL_CCSR_GUR_LE 229 230 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 231 232 #elif defined(CONFIG_FSL_LSCH2) 233 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 234 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 235 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 236 237 #define DCSR_DCFG_SBEESR2 0x20140534 238 #define DCSR_DCFG_MBEESR2 0x20140544 239 240 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 241 #define CONFIG_SYS_FSL_ESDHC_BE 242 #define CONFIG_SYS_FSL_WDOG_BE 243 #define CONFIG_SYS_FSL_DSPI_BE 244 #define CONFIG_SYS_FSL_QSPI_BE 245 #define CONFIG_SYS_FSL_CCSR_GUR_BE 246 #define CONFIG_SYS_FSL_PEX_LUT_BE 247 248 /* SoC related */ 249 #ifdef CONFIG_ARCH_LS1043A 250 #define CONFIG_SYS_FMAN_V3 251 #define CONFIG_SYS_FSL_QMAN_V3 252 #define CONFIG_SYS_NUM_FMAN 1 253 #define CONFIG_SYS_NUM_FM1_DTSEC 7 254 #define CONFIG_SYS_NUM_FM1_10GEC 1 255 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 256 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 257 258 #define QE_MURAM_SIZE 0x6000UL 259 #define MAX_QE_RISC 1 260 #define QE_NUM_OF_SNUM 28 261 262 #define CONFIG_SYS_FSL_IFC_BE 263 #define CONFIG_SYS_FSL_SFP_VER_3_2 264 #define CONFIG_SYS_FSL_SEC_MON_BE 265 #define CONFIG_SYS_FSL_SFP_BE 266 #define CONFIG_SYS_FSL_SRK_LE 267 #define CONFIG_KEY_REVOCATION 268 269 /* SMMU Defintions */ 270 #define SMMU_BASE 0x09000000 271 272 /* Generic Interrupt Controller Definitions */ 273 #define GICD_BASE 0x01401000 274 #define GICC_BASE 0x01402000 275 #define GICH_BASE 0x01404000 276 #define GICV_BASE 0x01406000 277 #define GICD_SIZE 0x1000 278 #define GICC_SIZE 0x2000 279 #define GICH_SIZE 0x2000 280 #define GICV_SIZE 0x2000 281 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 282 #define GICD_BASE_64K 0x01410000 283 #define GICC_BASE_64K 0x01420000 284 #define GICH_BASE_64K 0x01440000 285 #define GICV_BASE_64K 0x01460000 286 #define GICD_SIZE_64K 0x10000 287 #define GICC_SIZE_64K 0x20000 288 #define GICH_SIZE_64K 0x20000 289 #define GICV_SIZE_64K 0x20000 290 #endif 291 292 #define DCFG_CCSR_SVR 0x1ee00a4 293 #define REV1_0 0x10 294 #define REV1_1 0x11 295 #define GIC_ADDR_BIT 31 296 #define SCFG_GIC400_ALIGN 0x1570188 297 298 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 299 300 #elif defined(CONFIG_ARCH_LS1012A) 301 #define GICD_BASE 0x01401000 302 #define GICC_BASE 0x01402000 303 #define CONFIG_SYS_FSL_SFP_VER_3_2 304 #define CONFIG_SYS_FSL_SEC_MON_BE 305 #define CONFIG_SYS_FSL_SFP_BE 306 #define CONFIG_SYS_FSL_SRK_LE 307 #define CONFIG_KEY_REVOCATION 308 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 309 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 310 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 311 312 #elif defined(CONFIG_ARCH_LS1046A) 313 #define CONFIG_SYS_FMAN_V3 314 #define CONFIG_SYS_FSL_QMAN_V3 315 #define CONFIG_SYS_NUM_FMAN 1 316 #define CONFIG_SYS_NUM_FM1_DTSEC 8 317 #define CONFIG_SYS_NUM_FM1_10GEC 2 318 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 319 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 320 321 #define CONFIG_SYS_FSL_IFC_BE 322 #define CONFIG_SYS_FSL_SFP_VER_3_2 323 #define CONFIG_SYS_FSL_SEC_MON_BE 324 #define CONFIG_SYS_FSL_SFP_BE 325 #define CONFIG_SYS_FSL_SRK_LE 326 #define CONFIG_KEY_REVOCATION 327 328 /* SMMU Defintions */ 329 #define SMMU_BASE 0x09000000 330 331 /* Generic Interrupt Controller Definitions */ 332 #define GICD_BASE 0x01410000 333 #define GICC_BASE 0x01420000 334 335 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 336 #else 337 #error SoC not defined 338 #endif 339 #endif 340 341 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 342