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Searched defs:GICC_BASE (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dsun50i.h15 #define GICC_BASE 0x1c82000 macro
18 #define GICC_BASE 0x3022000 macro
H A Dmeson64.h13 #define GICC_BASE 0xffc02000 macro
16 #define GICC_BASE 0xc4302000 macro
H A Dvexpress_aemv8a.h90 #define GICC_BASE (0x2c000000) macro
93 #define GICC_BASE (0x2C02f000) macro
H A Dhikey.h45 #define GICC_BASE 0xf6802000 macro
H A Drcar-gen3-common.h29 #define GICC_BASE 0xF1020000 macro
H A Ds32v234evb.h18 #define GICC_BASE 0x7D002000 macro
H A Dxilinx_zynqmp.h20 #define GICC_BASE 0xF9020000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-tegra186/
H A Dtegra.h10 #define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ macro
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dtegra.h11 #define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ macro
/openbmc/u-boot/arch/arm/mach-snapdragon/include/mach/
H A Dsysmap-apq8016.h11 #define GICC_BASE (0x0a20c000) macro
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_s10.h41 #define GICC_BASE 0xfffc2000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h274 #define GICC_BASE 0x01402000 macro
302 #define GICC_BASE 0x01402000 macro
333 #define GICC_BASE 0x01420000 macro
/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c27 #define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15) macro