1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
7
8 #include <asm/hyperv-tlfs.h>
9
10 /*
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
13 */
14
15 enum intercept_words {
16 INTERCEPT_CR = 0,
17 INTERCEPT_DR,
18 INTERCEPT_EXCEPTION,
19 INTERCEPT_WORD3,
20 INTERCEPT_WORD4,
21 INTERCEPT_WORD5,
22 MAX_INTERCEPT,
23 };
24
25 enum {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
37 INTERCEPT_DR1_READ,
38 INTERCEPT_DR2_READ,
39 INTERCEPT_DR3_READ,
40 INTERCEPT_DR4_READ,
41 INTERCEPT_DR5_READ,
42 INTERCEPT_DR6_READ,
43 INTERCEPT_DR7_READ,
44 INTERCEPT_DR0_WRITE = 48,
45 INTERCEPT_DR1_WRITE,
46 INTERCEPT_DR2_WRITE,
47 INTERCEPT_DR3_WRITE,
48 INTERCEPT_DR4_WRITE,
49 INTERCEPT_DR5_WRITE,
50 INTERCEPT_DR6_WRITE,
51 INTERCEPT_DR7_WRITE,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
55 INTERCEPT_INTR = 96,
56 INTERCEPT_NMI,
57 INTERCEPT_SMI,
58 INTERCEPT_INIT,
59 INTERCEPT_VINTR,
60 INTERCEPT_SELECTIVE_CR0,
61 INTERCEPT_STORE_IDTR,
62 INTERCEPT_STORE_GDTR,
63 INTERCEPT_STORE_LDTR,
64 INTERCEPT_STORE_TR,
65 INTERCEPT_LOAD_IDTR,
66 INTERCEPT_LOAD_GDTR,
67 INTERCEPT_LOAD_LDTR,
68 INTERCEPT_LOAD_TR,
69 INTERCEPT_RDTSC,
70 INTERCEPT_RDPMC,
71 INTERCEPT_PUSHF,
72 INTERCEPT_POPF,
73 INTERCEPT_CPUID,
74 INTERCEPT_RSM,
75 INTERCEPT_IRET,
76 INTERCEPT_INTn,
77 INTERCEPT_INVD,
78 INTERCEPT_PAUSE,
79 INTERCEPT_HLT,
80 INTERCEPT_INVLPG,
81 INTERCEPT_INVLPGA,
82 INTERCEPT_IOIO_PROT,
83 INTERCEPT_MSR_PROT,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
86 INTERCEPT_SHUTDOWN,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
89 INTERCEPT_VMMCALL,
90 INTERCEPT_VMLOAD,
91 INTERCEPT_VMSAVE,
92 INTERCEPT_STGI,
93 INTERCEPT_CLGI,
94 INTERCEPT_SKINIT,
95 INTERCEPT_RDTSCP,
96 INTERCEPT_ICEBP,
97 INTERCEPT_WBINVD,
98 INTERCEPT_MONITOR,
99 INTERCEPT_MWAIT,
100 INTERCEPT_MWAIT_COND,
101 INTERCEPT_XSETBV,
102 INTERCEPT_RDPRU,
103 TRAP_EFER_WRITE,
104 TRAP_CR0_WRITE,
105 TRAP_CR1_WRITE,
106 TRAP_CR2_WRITE,
107 TRAP_CR3_WRITE,
108 TRAP_CR4_WRITE,
109 TRAP_CR5_WRITE,
110 TRAP_CR6_WRITE,
111 TRAP_CR7_WRITE,
112 TRAP_CR8_WRITE,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
116 INTERCEPT_INVPCID,
117 INTERCEPT_MCOMMIT,
118 INTERCEPT_TLBSYNC,
119 };
120
121
122 struct __attribute__ ((__packed__)) vmcb_control_area {
123 u32 intercepts[MAX_INTERCEPT];
124 u32 reserved_1[15 - MAX_INTERCEPT];
125 u16 pause_filter_thresh;
126 u16 pause_filter_count;
127 u64 iopm_base_pa;
128 u64 msrpm_base_pa;
129 u64 tsc_offset;
130 u32 asid;
131 u8 tlb_ctl;
132 u8 reserved_2[3];
133 u32 int_ctl;
134 u32 int_vector;
135 u32 int_state;
136 u8 reserved_3[4];
137 u32 exit_code;
138 u32 exit_code_hi;
139 u64 exit_info_1;
140 u64 exit_info_2;
141 u32 exit_int_info;
142 u32 exit_int_info_err;
143 u64 nested_ctl;
144 u64 avic_vapic_bar;
145 u64 ghcb_gpa;
146 u32 event_inj;
147 u32 event_inj_err;
148 u64 nested_cr3;
149 u64 virt_ext;
150 u32 clean;
151 u32 reserved_5;
152 u64 next_rip;
153 u8 insn_len;
154 u8 insn_bytes[15];
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
159 u8 reserved_7[8];
160 u64 vmsa_pa; /* Used for an SEV-ES guest */
161 u8 reserved_8[720];
162 /*
163 * Offset 0x3e0, 32 bytes reserved
164 * for use by hypervisor/software.
165 */
166 union {
167 struct hv_vmcb_enlightenments hv_enlightenments;
168 u8 reserved_sw[32];
169 };
170 };
171
172
173 #define TLB_CONTROL_DO_NOTHING 0
174 #define TLB_CONTROL_FLUSH_ALL_ASID 1
175 #define TLB_CONTROL_FLUSH_ASID 3
176 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
177
178 #define V_TPR_MASK 0x0f
179
180 #define V_IRQ_SHIFT 8
181 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
182
183 #define V_GIF_SHIFT 9
184 #define V_GIF_MASK (1 << V_GIF_SHIFT)
185
186 #define V_NMI_PENDING_SHIFT 11
187 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
188
189 #define V_NMI_BLOCKING_SHIFT 12
190 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
191
192 #define V_INTR_PRIO_SHIFT 16
193 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
194
195 #define V_IGN_TPR_SHIFT 20
196 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
197
198 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
199
200 #define V_INTR_MASKING_SHIFT 24
201 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
202
203 #define V_GIF_ENABLE_SHIFT 25
204 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
205
206 #define V_NMI_ENABLE_SHIFT 26
207 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
208
209 #define AVIC_ENABLE_SHIFT 31
210 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
211
212 #define X2APIC_MODE_SHIFT 30
213 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
214
215 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
216 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
217
218 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
219 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
220
221 #define SVM_IOIO_STR_SHIFT 2
222 #define SVM_IOIO_REP_SHIFT 3
223 #define SVM_IOIO_SIZE_SHIFT 4
224 #define SVM_IOIO_ASIZE_SHIFT 7
225
226 #define SVM_IOIO_TYPE_MASK 1
227 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
228 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
229 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
230 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
231
232 #define SVM_VM_CR_VALID_MASK 0x001fULL
233 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
234 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
235
236 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
237 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
238 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
239
240
241 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
242 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
243 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
244 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
245
246
247 /* AVIC */
248 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
249 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
250 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
251
252 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
253 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
254 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
255 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
256 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
257
258 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
259
260 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
261
262 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
263 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
264 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
265
266 enum avic_ipi_failure_cause {
267 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
268 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
269 AVIC_IPI_FAILURE_INVALID_TARGET,
270 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
271 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR,
272 };
273
274 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0)
275
276 /*
277 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
278 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
279 */
280 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
281
282 /*
283 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
284 */
285 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
286
287 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
288 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
289
290 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
291
292 #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5)
293
294 struct vmcb_seg {
295 u16 selector;
296 u16 attrib;
297 u32 limit;
298 u64 base;
299 } __packed;
300
301 /* Save area definition for legacy and SEV-MEM guests */
302 struct vmcb_save_area {
303 struct vmcb_seg es;
304 struct vmcb_seg cs;
305 struct vmcb_seg ss;
306 struct vmcb_seg ds;
307 struct vmcb_seg fs;
308 struct vmcb_seg gs;
309 struct vmcb_seg gdtr;
310 struct vmcb_seg ldtr;
311 struct vmcb_seg idtr;
312 struct vmcb_seg tr;
313 /* Reserved fields are named following their struct offset */
314 u8 reserved_0xa0[42];
315 u8 vmpl;
316 u8 cpl;
317 u8 reserved_0xcc[4];
318 u64 efer;
319 u8 reserved_0xd8[112];
320 u64 cr4;
321 u64 cr3;
322 u64 cr0;
323 u64 dr7;
324 u64 dr6;
325 u64 rflags;
326 u64 rip;
327 u8 reserved_0x180[88];
328 u64 rsp;
329 u64 s_cet;
330 u64 ssp;
331 u64 isst_addr;
332 u64 rax;
333 u64 star;
334 u64 lstar;
335 u64 cstar;
336 u64 sfmask;
337 u64 kernel_gs_base;
338 u64 sysenter_cs;
339 u64 sysenter_esp;
340 u64 sysenter_eip;
341 u64 cr2;
342 u8 reserved_0x248[32];
343 u64 g_pat;
344 u64 dbgctl;
345 u64 br_from;
346 u64 br_to;
347 u64 last_excp_from;
348 u64 last_excp_to;
349 u8 reserved_0x298[72];
350 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
351 } __packed;
352
353 /* Save area definition for SEV-ES and SEV-SNP guests */
354 struct sev_es_save_area {
355 struct vmcb_seg es;
356 struct vmcb_seg cs;
357 struct vmcb_seg ss;
358 struct vmcb_seg ds;
359 struct vmcb_seg fs;
360 struct vmcb_seg gs;
361 struct vmcb_seg gdtr;
362 struct vmcb_seg ldtr;
363 struct vmcb_seg idtr;
364 struct vmcb_seg tr;
365 u64 vmpl0_ssp;
366 u64 vmpl1_ssp;
367 u64 vmpl2_ssp;
368 u64 vmpl3_ssp;
369 u64 u_cet;
370 u8 reserved_0xc8[2];
371 u8 vmpl;
372 u8 cpl;
373 u8 reserved_0xcc[4];
374 u64 efer;
375 u8 reserved_0xd8[104];
376 u64 xss;
377 u64 cr4;
378 u64 cr3;
379 u64 cr0;
380 u64 dr7;
381 u64 dr6;
382 u64 rflags;
383 u64 rip;
384 u64 dr0;
385 u64 dr1;
386 u64 dr2;
387 u64 dr3;
388 u64 dr0_addr_mask;
389 u64 dr1_addr_mask;
390 u64 dr2_addr_mask;
391 u64 dr3_addr_mask;
392 u8 reserved_0x1c0[24];
393 u64 rsp;
394 u64 s_cet;
395 u64 ssp;
396 u64 isst_addr;
397 u64 rax;
398 u64 star;
399 u64 lstar;
400 u64 cstar;
401 u64 sfmask;
402 u64 kernel_gs_base;
403 u64 sysenter_cs;
404 u64 sysenter_esp;
405 u64 sysenter_eip;
406 u64 cr2;
407 u8 reserved_0x248[32];
408 u64 g_pat;
409 u64 dbgctl;
410 u64 br_from;
411 u64 br_to;
412 u64 last_excp_from;
413 u64 last_excp_to;
414 u8 reserved_0x298[80];
415 u32 pkru;
416 u32 tsc_aux;
417 u8 reserved_0x2f0[24];
418 u64 rcx;
419 u64 rdx;
420 u64 rbx;
421 u64 reserved_0x320; /* rsp already available at 0x01d8 */
422 u64 rbp;
423 u64 rsi;
424 u64 rdi;
425 u64 r8;
426 u64 r9;
427 u64 r10;
428 u64 r11;
429 u64 r12;
430 u64 r13;
431 u64 r14;
432 u64 r15;
433 u8 reserved_0x380[16];
434 u64 guest_exit_info_1;
435 u64 guest_exit_info_2;
436 u64 guest_exit_int_info;
437 u64 guest_nrip;
438 u64 sev_features;
439 u64 vintr_ctrl;
440 u64 guest_exit_code;
441 u64 virtual_tom;
442 u64 tlb_id;
443 u64 pcpu_id;
444 u64 event_inj;
445 u64 xcr0;
446 u8 reserved_0x3f0[16];
447
448 /* Floating point area */
449 u64 x87_dp;
450 u32 mxcsr;
451 u16 x87_ftw;
452 u16 x87_fsw;
453 u16 x87_fcw;
454 u16 x87_fop;
455 u16 x87_ds;
456 u16 x87_cs;
457 u64 x87_rip;
458 u8 fpreg_x87[80];
459 u8 fpreg_xmm[256];
460 u8 fpreg_ymm[256];
461 } __packed;
462
463 struct ghcb_save_area {
464 u8 reserved_0x0[203];
465 u8 cpl;
466 u8 reserved_0xcc[116];
467 u64 xss;
468 u8 reserved_0x148[24];
469 u64 dr7;
470 u8 reserved_0x168[16];
471 u64 rip;
472 u8 reserved_0x180[88];
473 u64 rsp;
474 u8 reserved_0x1e0[24];
475 u64 rax;
476 u8 reserved_0x200[264];
477 u64 rcx;
478 u64 rdx;
479 u64 rbx;
480 u8 reserved_0x320[8];
481 u64 rbp;
482 u64 rsi;
483 u64 rdi;
484 u64 r8;
485 u64 r9;
486 u64 r10;
487 u64 r11;
488 u64 r12;
489 u64 r13;
490 u64 r14;
491 u64 r15;
492 u8 reserved_0x380[16];
493 u64 sw_exit_code;
494 u64 sw_exit_info_1;
495 u64 sw_exit_info_2;
496 u64 sw_scratch;
497 u8 reserved_0x3b0[56];
498 u64 xcr0;
499 u8 valid_bitmap[16];
500 u64 x87_state_gpa;
501 } __packed;
502
503 #define GHCB_SHARED_BUF_SIZE 2032
504
505 struct ghcb {
506 struct ghcb_save_area save;
507 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
508
509 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
510
511 u8 reserved_0xff0[10];
512 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
513 u32 ghcb_usage;
514 } __packed;
515
516
517 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744
518 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
519 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
520 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
521 #define EXPECTED_GHCB_SIZE PAGE_SIZE
522
523 #define BUILD_BUG_RESERVED_OFFSET(x, y) \
524 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
525
__unused_size_checks(void)526 static inline void __unused_size_checks(void)
527 {
528 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
529 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
530 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
531 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
532 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
533
534 /* Check offsets of reserved fields */
535
536 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
537 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
538 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
539 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
540 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
541 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
542
543 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
544 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
545 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
546 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
547 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
548 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
549 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x2f0);
550 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
551 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
552 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
553
554 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
555 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
556 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
557 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
558 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
559 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
560 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
561 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
562 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
563 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
564
565 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
566 }
567
568 struct vmcb {
569 struct vmcb_control_area control;
570 struct vmcb_save_area save;
571 } __packed;
572
573 #define SVM_CPUID_FUNC 0x8000000a
574
575 #define SVM_VM_CR_SVM_DISABLE 4
576
577 #define SVM_SELECTOR_S_SHIFT 4
578 #define SVM_SELECTOR_DPL_SHIFT 5
579 #define SVM_SELECTOR_P_SHIFT 7
580 #define SVM_SELECTOR_AVL_SHIFT 8
581 #define SVM_SELECTOR_L_SHIFT 9
582 #define SVM_SELECTOR_DB_SHIFT 10
583 #define SVM_SELECTOR_G_SHIFT 11
584
585 #define SVM_SELECTOR_TYPE_MASK (0xf)
586 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
587 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
588 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
589 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
590 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
591 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
592 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
593
594 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
595 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
596 #define SVM_SELECTOR_CODE_MASK (1 << 3)
597
598 #define SVM_EVTINJ_VEC_MASK 0xff
599
600 #define SVM_EVTINJ_TYPE_SHIFT 8
601 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
602
603 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
604 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
605 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
606 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
607
608 #define SVM_EVTINJ_VALID (1 << 31)
609 #define SVM_EVTINJ_VALID_ERR (1 << 11)
610
611 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
612 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
613
614 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
615 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
616 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
617 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
618
619 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
620 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
621
622 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
623 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
624 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
625
626 #define SVM_EXITINFO_REG_MASK 0x0F
627
628 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
629
630 /* GHCB Accessor functions */
631
632 #define GHCB_BITMAP_IDX(field) \
633 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
634
635 #define DEFINE_GHCB_ACCESSORS(field) \
636 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
637 { \
638 return test_bit(GHCB_BITMAP_IDX(field), \
639 (unsigned long *)&ghcb->save.valid_bitmap); \
640 } \
641 \
642 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
643 { \
644 return ghcb->save.field; \
645 } \
646 \
647 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
648 { \
649 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
650 } \
651 \
652 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
653 { \
654 __set_bit(GHCB_BITMAP_IDX(field), \
655 (unsigned long *)&ghcb->save.valid_bitmap); \
656 ghcb->save.field = value; \
657 }
658
659 DEFINE_GHCB_ACCESSORS(cpl)
660 DEFINE_GHCB_ACCESSORS(rip)
661 DEFINE_GHCB_ACCESSORS(rsp)
662 DEFINE_GHCB_ACCESSORS(rax)
663 DEFINE_GHCB_ACCESSORS(rcx)
664 DEFINE_GHCB_ACCESSORS(rdx)
665 DEFINE_GHCB_ACCESSORS(rbx)
666 DEFINE_GHCB_ACCESSORS(rbp)
667 DEFINE_GHCB_ACCESSORS(rsi)
668 DEFINE_GHCB_ACCESSORS(rdi)
669 DEFINE_GHCB_ACCESSORS(r8)
670 DEFINE_GHCB_ACCESSORS(r9)
671 DEFINE_GHCB_ACCESSORS(r10)
672 DEFINE_GHCB_ACCESSORS(r11)
673 DEFINE_GHCB_ACCESSORS(r12)
674 DEFINE_GHCB_ACCESSORS(r13)
675 DEFINE_GHCB_ACCESSORS(r14)
676 DEFINE_GHCB_ACCESSORS(r15)
677 DEFINE_GHCB_ACCESSORS(sw_exit_code)
678 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
679 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
680 DEFINE_GHCB_ACCESSORS(sw_scratch)
681 DEFINE_GHCB_ACCESSORS(xcr0)
682
683 #endif
684