xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/sid.h (revision 40111ec2)
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef SI_H
25 #define SI_H
26 
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH  2
28 
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001
32 
33 #define SI_MAX_SH_GPRS		 	256
34 #define SI_MAX_TEMP_GPRS         	16
35 #define SI_MAX_SH_THREADS        	256
36 #define SI_MAX_SH_STACK_ENTRIES  	4096
37 #define SI_MAX_FRC_EOV_CNT       	16384
38 #define SI_MAX_BACKENDS          	8
39 #define SI_MAX_BACKENDS_MASK     	0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
41 #define SI_MAX_SIMDS             	12
42 #define SI_MAX_SIMDS_MASK        	0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
44 #define SI_MAX_PIPES            	8
45 #define SI_MAX_PIPES_MASK        	0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
47 #define SI_MAX_LDS_NUM           	0xFFFF
48 #define SI_MAX_TCC               	16
49 #define SI_MAX_TCC_MASK          	0xFFFF
50 #define SI_MAX_CTLACKS_ASSERTION_WAIT   100
51 
52 /* SMC IND accessor regs */
53 #define SMC_IND_INDEX_0                              0x80
54 #define SMC_IND_DATA_0                               0x81
55 
56 #define SMC_IND_ACCESS_CNTL                          0x8A
57 #       define AUTO_INCREMENT_IND_0                  (1 << 0)
58 #define SMC_MESSAGE_0                                0x8B
59 #define SMC_RESP_0                                   0x8C
60 
61 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
62 #define SMC_CG_IND_START                    0xc0030000
63 #define SMC_CG_IND_END                      0xc0040000
64 
65 #define	CG_CGTT_LOCAL_0				0x400
66 #define	CG_CGTT_LOCAL_1				0x401
67 
68 /* SMC IND registers */
69 #define	SMC_SYSCON_RESET_CNTL				0x80000000
70 #       define RST_REG                                  (1 << 0)
71 #define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
72 #       define CK_DISABLE                               (1 << 0)
73 #       define CKEN                                     (1 << 24)
74 
75 #define VGA_HDP_CONTROL  				0xCA
76 #define		VGA_MEMORY_DISABLE				(1 << 4)
77 
78 #define DCCG_DISP_SLOW_SELECT_REG                       0x13F
79 #define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)
80 #define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)
81 #define		DCCG_DISP1_SLOW_SELECT_SHIFT		0
82 #define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)
83 #define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)
84 #define		DCCG_DISP2_SLOW_SELECT_SHIFT		4
85 
86 #define	CG_SPLL_FUNC_CNTL				0x180
87 #define		SPLL_RESET				(1 << 0)
88 #define		SPLL_SLEEP				(1 << 1)
89 #define		SPLL_BYPASS_EN				(1 << 3)
90 #define		SPLL_REF_DIV(x)				((x) << 4)
91 #define		SPLL_REF_DIV_MASK			(0x3f << 4)
92 #define		SPLL_PDIV_A(x)				((x) << 20)
93 #define		SPLL_PDIV_A_MASK			(0x7f << 20)
94 #define		SPLL_PDIV_A_SHIFT			20
95 #define	CG_SPLL_FUNC_CNTL_2				0x181
96 #define		SCLK_MUX_SEL(x)				((x) << 0)
97 #define		SCLK_MUX_SEL_MASK			(0x1ff << 0)
98 #define		SPLL_CTLREQ_CHG				(1 << 23)
99 #define		SCLK_MUX_UPDATE				(1 << 26)
100 #define	CG_SPLL_FUNC_CNTL_3				0x182
101 #define		SPLL_FB_DIV(x)				((x) << 0)
102 #define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)
103 #define		SPLL_FB_DIV_SHIFT			0
104 #define		SPLL_DITHEN				(1 << 28)
105 #define	CG_SPLL_FUNC_CNTL_4				0x183
106 
107 #define	SPLL_STATUS					0x185
108 #define		SPLL_CHG_STATUS				(1 << 1)
109 #define	SPLL_CNTL_MODE					0x186
110 #define		SPLL_SW_DIR_CONTROL			(1 << 0)
111 #	define SPLL_REFCLK_SEL(x)			((x) << 26)
112 #	define SPLL_REFCLK_SEL_MASK			(3 << 26)
113 
114 #define	CG_SPLL_SPREAD_SPECTRUM				0x188
115 #define		SSEN					(1 << 0)
116 #define		CLK_S(x)				((x) << 4)
117 #define		CLK_S_MASK				(0xfff << 4)
118 #define		CLK_S_SHIFT				4
119 #define	CG_SPLL_SPREAD_SPECTRUM_2			0x189
120 #define		CLK_V(x)				((x) << 0)
121 #define		CLK_V_MASK				(0x3ffffff << 0)
122 #define		CLK_V_SHIFT				0
123 
124 #define	CG_SPLL_AUTOSCALE_CNTL				0x18b
125 #       define AUTOSCALE_ON_SS_CLEAR                    (1 << 9)
126 
127 /* discrete uvd clocks */
128 #define	CG_UPLL_FUNC_CNTL				0x18d
129 #	define UPLL_RESET_MASK				0x00000001
130 #	define UPLL_SLEEP_MASK				0x00000002
131 #	define UPLL_BYPASS_EN_MASK			0x00000004
132 #	define UPLL_CTLREQ_MASK				0x00000008
133 #	define UPLL_VCO_MODE_MASK			0x00000600
134 #	define UPLL_REF_DIV_MASK			0x003F0000
135 #	define UPLL_CTLACK_MASK				0x40000000
136 #	define UPLL_CTLACK2_MASK			0x80000000
137 #define	CG_UPLL_FUNC_CNTL_2				0x18e
138 #	define UPLL_PDIV_A(x)				((x) << 0)
139 #	define UPLL_PDIV_A_MASK				0x0000007F
140 #	define UPLL_PDIV_B(x)				((x) << 8)
141 #	define UPLL_PDIV_B_MASK				0x00007F00
142 #	define VCLK_SRC_SEL(x)				((x) << 20)
143 #	define VCLK_SRC_SEL_MASK			0x01F00000
144 #	define DCLK_SRC_SEL(x)				((x) << 25)
145 #	define DCLK_SRC_SEL_MASK			0x3E000000
146 #define	CG_UPLL_FUNC_CNTL_3				0x18f
147 #	define UPLL_FB_DIV(x)				((x) << 0)
148 #	define UPLL_FB_DIV_MASK				0x01FFFFFF
149 #define	CG_UPLL_FUNC_CNTL_4                             0x191
150 #	define UPLL_SPARE_ISPARE9			0x00020000
151 #define	CG_UPLL_FUNC_CNTL_5				0x192
152 #	define RESET_ANTI_MUX_MASK			0x00000200
153 #define	CG_UPLL_SPREAD_SPECTRUM				0x194
154 #	define SSEN_MASK				0x00000001
155 
156 #define	MPLL_BYPASSCLK_SEL				0x197
157 #	define MPLL_CLKOUT_SEL(x)			((x) << 8)
158 #	define MPLL_CLKOUT_SEL_MASK			0xFF00
159 
160 #define CG_CLKPIN_CNTL                                    0x198
161 #       define XTALIN_DIVIDE                              (1 << 1)
162 #       define BCLK_AS_XCLK                               (1 << 2)
163 #define CG_CLKPIN_CNTL_2                                  0x199
164 #       define FORCE_BIF_REFCLK_EN                        (1 << 3)
165 #       define MUX_TCLK_TO_XCLK                           (1 << 8)
166 
167 #define	THM_CLK_CNTL					0x19b
168 #	define CMON_CLK_SEL(x)				((x) << 0)
169 #	define CMON_CLK_SEL_MASK			0xFF
170 #	define TMON_CLK_SEL(x)				((x) << 8)
171 #	define TMON_CLK_SEL_MASK			0xFF00
172 #define	MISC_CLK_CNTL					0x19c
173 #	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)
174 #	define DEEP_SLEEP_CLK_SEL_MASK			0xFF
175 #	define ZCLK_SEL(x)				((x) << 8)
176 #	define ZCLK_SEL_MASK				0xFF00
177 
178 #define	CG_THERMAL_CTRL					0x1c0
179 #define 	DPM_EVENT_SRC(x)			((x) << 0)
180 #define 	DPM_EVENT_SRC_MASK			(7 << 0)
181 #define		DIG_THERM_DPM(x)			((x) << 14)
182 #define		DIG_THERM_DPM_MASK			0x003FC000
183 #define		DIG_THERM_DPM_SHIFT			14
184 #define	CG_THERMAL_STATUS				0x1c1
185 #define		FDO_PWM_DUTY(x)				((x) << 9)
186 #define		FDO_PWM_DUTY_MASK			(0xff << 9)
187 #define		FDO_PWM_DUTY_SHIFT			9
188 #define	CG_THERMAL_INT					0x1c2
189 #define		DIG_THERM_INTH(x)			((x) << 8)
190 #define		DIG_THERM_INTH_MASK			0x0000FF00
191 #define		DIG_THERM_INTH_SHIFT			8
192 #define		DIG_THERM_INTL(x)			((x) << 16)
193 #define		DIG_THERM_INTL_MASK			0x00FF0000
194 #define		DIG_THERM_INTL_SHIFT			16
195 #define 	THERM_INT_MASK_HIGH			(1 << 24)
196 #define 	THERM_INT_MASK_LOW			(1 << 25)
197 
198 #define	CG_MULT_THERMAL_CTRL					0x1c4
199 #define		TEMP_SEL(x)					((x) << 20)
200 #define		TEMP_SEL_MASK					(0xff << 20)
201 #define		TEMP_SEL_SHIFT					20
202 #define	CG_MULT_THERMAL_STATUS					0x1c5
203 #define		ASIC_MAX_TEMP(x)				((x) << 0)
204 #define		ASIC_MAX_TEMP_MASK				0x000001ff
205 #define		ASIC_MAX_TEMP_SHIFT				0
206 #define		CTF_TEMP(x)					((x) << 9)
207 #define		CTF_TEMP_MASK					0x0003fe00
208 #define		CTF_TEMP_SHIFT					9
209 
210 #define	CG_FDO_CTRL0					0x1d5
211 #define		FDO_STATIC_DUTY(x)			((x) << 0)
212 #define		FDO_STATIC_DUTY_MASK			0x000000FF
213 #define		FDO_STATIC_DUTY_SHIFT			0
214 #define	CG_FDO_CTRL1					0x1d6
215 #define		FMAX_DUTY100(x)				((x) << 0)
216 #define		FMAX_DUTY100_MASK			0x000000FF
217 #define		FMAX_DUTY100_SHIFT			0
218 #define	CG_FDO_CTRL2					0x1d7
219 #define		TMIN(x)					((x) << 0)
220 #define		TMIN_MASK				0x000000FF
221 #define		TMIN_SHIFT				0
222 #define		FDO_PWM_MODE(x)				((x) << 11)
223 #define		FDO_PWM_MODE_MASK			(7 << 11)
224 #define		FDO_PWM_MODE_SHIFT			11
225 #define		TACH_PWM_RESP_RATE(x)			((x) << 25)
226 #define		TACH_PWM_RESP_RATE_MASK			(0x7f << 25)
227 #define		TACH_PWM_RESP_RATE_SHIFT		25
228 
229 #define CG_TACH_CTRL                                    0x1dc
230 #       define EDGE_PER_REV(x)                          ((x) << 0)
231 #       define EDGE_PER_REV_MASK                        (0x7 << 0)
232 #       define EDGE_PER_REV_SHIFT                       0
233 #       define TARGET_PERIOD(x)                         ((x) << 3)
234 #       define TARGET_PERIOD_MASK                       0xfffffff8
235 #       define TARGET_PERIOD_SHIFT                      3
236 #define CG_TACH_STATUS                                  0x1dd
237 #       define TACH_PERIOD(x)                           ((x) << 0)
238 #       define TACH_PERIOD_MASK                         0xffffffff
239 #       define TACH_PERIOD_SHIFT                        0
240 
241 #define GENERAL_PWRMGT                                  0x1e0
242 #       define GLOBAL_PWRMGT_EN                         (1 << 0)
243 #       define STATIC_PM_EN                             (1 << 1)
244 #       define THERMAL_PROTECTION_DIS                   (1 << 2)
245 #       define THERMAL_PROTECTION_TYPE                  (1 << 3)
246 #       define SW_SMIO_INDEX(x)                         ((x) << 6)
247 #       define SW_SMIO_INDEX_MASK                       (1 << 6)
248 #       define SW_SMIO_INDEX_SHIFT                      6
249 #       define VOLT_PWRMGT_EN                           (1 << 10)
250 #       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)
251 #define CG_TPC                                            0x1e1
252 #define SCLK_PWRMGT_CNTL                                  0x1e2
253 #       define SCLK_PWRMGT_OFF                            (1 << 0)
254 #       define SCLK_LOW_D1                                (1 << 1)
255 #       define FIR_RESET                                  (1 << 4)
256 #       define FIR_FORCE_TREND_SEL                        (1 << 5)
257 #       define FIR_TREND_MODE                             (1 << 6)
258 #       define DYN_GFX_CLK_OFF_EN                         (1 << 7)
259 #       define GFX_CLK_FORCE_ON                           (1 << 8)
260 #       define GFX_CLK_REQUEST_OFF                        (1 << 9)
261 #       define GFX_CLK_FORCE_OFF                          (1 << 10)
262 #       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)
263 #       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)
264 #       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)
265 #       define DYN_LIGHT_SLEEP_EN                         (1 << 14)
266 
267 #define TARGET_AND_CURRENT_PROFILE_INDEX                  0x1e6
268 #       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)
269 #       define CURRENT_STATE_INDEX_SHIFT                  4
270 
271 #define CG_FTV                                            0x1ef
272 
273 #define CG_FFCT_0                                         0x1f0
274 #       define UTC_0(x)                                   ((x) << 0)
275 #       define UTC_0_MASK                                 (0x3ff << 0)
276 #       define DTC_0(x)                                   ((x) << 10)
277 #       define DTC_0_MASK                                 (0x3ff << 10)
278 
279 #define CG_BSP                                          0x1ff
280 #       define BSP(x)					((x) << 0)
281 #       define BSP_MASK					(0xffff << 0)
282 #       define BSU(x)					((x) << 16)
283 #       define BSU_MASK					(0xf << 16)
284 #define CG_AT                                           0x200
285 #       define CG_R(x)					((x) << 0)
286 #       define CG_R_MASK				(0xffff << 0)
287 #       define CG_L(x)					((x) << 16)
288 #       define CG_L_MASK				(0xffff << 16)
289 
290 #define CG_GIT                                          0x201
291 #       define CG_GICST(x)                              ((x) << 0)
292 #       define CG_GICST_MASK                            (0xffff << 0)
293 #       define CG_GIPOT(x)                              ((x) << 16)
294 #       define CG_GIPOT_MASK                            (0xffff << 16)
295 
296 #define CG_SSP                                            0x203
297 #       define SST(x)                                     ((x) << 0)
298 #       define SST_MASK                                   (0xffff << 0)
299 #       define SSTU(x)                                    ((x) << 16)
300 #       define SSTU_MASK                                  (0xf << 16)
301 
302 #define CG_DISPLAY_GAP_CNTL                               0x20a
303 #       define DISP1_GAP(x)                               ((x) << 0)
304 #       define DISP1_GAP_MASK                             (3 << 0)
305 #       define DISP2_GAP(x)                               ((x) << 2)
306 #       define DISP2_GAP_MASK                             (3 << 2)
307 #       define VBI_TIMER_COUNT(x)                         ((x) << 4)
308 #       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
309 #       define VBI_TIMER_UNIT(x)                          ((x) << 20)
310 #       define VBI_TIMER_UNIT_MASK                        (7 << 20)
311 #       define DISP1_GAP_MCHG(x)                          ((x) << 24)
312 #       define DISP1_GAP_MCHG_MASK                        (3 << 24)
313 #       define DISP2_GAP_MCHG(x)                          ((x) << 26)
314 #       define DISP2_GAP_MCHG_MASK                        (3 << 26)
315 
316 #define	CG_ULV_CONTROL					0x21e
317 #define	CG_ULV_PARAMETER				0x21f
318 
319 #define	SMC_SCRATCH0					0x221
320 
321 #define	CG_CAC_CTRL					0x22e
322 #	define CAC_WINDOW(x)				((x) << 0)
323 #	define CAC_WINDOW_MASK				0x00ffffff
324 
325 #define DMIF_ADDR_CONFIG  				0x2F5
326 
327 #define DMIF_ADDR_CALC  				0x300
328 
329 #define	PIPE0_DMIF_BUFFER_CONTROL			  0x0328
330 #       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
331 #       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
332 
333 #define	SRBM_STATUS				        0x394
334 #define		GRBM_RQ_PENDING 			(1 << 5)
335 #define		VMC_BUSY 				(1 << 8)
336 #define		MCB_BUSY 				(1 << 9)
337 #define		MCB_NON_DISPLAY_BUSY 			(1 << 10)
338 #define		MCC_BUSY 				(1 << 11)
339 #define		MCD_BUSY 				(1 << 12)
340 #define		SEM_BUSY 				(1 << 14)
341 #define		IH_BUSY 				(1 << 17)
342 
343 #define	SRBM_SOFT_RESET				        0x398
344 #define		SOFT_RESET_BIF				(1 << 1)
345 #define		SOFT_RESET_DC				(1 << 5)
346 #define		SOFT_RESET_DMA1				(1 << 6)
347 #define		SOFT_RESET_GRBM				(1 << 8)
348 #define		SOFT_RESET_HDP				(1 << 9)
349 #define		SOFT_RESET_IH				(1 << 10)
350 #define		SOFT_RESET_MC				(1 << 11)
351 #define		SOFT_RESET_ROM				(1 << 14)
352 #define		SOFT_RESET_SEM				(1 << 15)
353 #define		SOFT_RESET_VMC				(1 << 17)
354 #define		SOFT_RESET_DMA				(1 << 20)
355 #define		SOFT_RESET_TST				(1 << 21)
356 #define		SOFT_RESET_REGBB			(1 << 22)
357 #define		SOFT_RESET_ORB				(1 << 23)
358 
359 #define	CC_SYS_RB_BACKEND_DISABLE			0x3A0
360 #define	GC_USER_SYS_RB_BACKEND_DISABLE			0x3A1
361 
362 #define SRBM_READ_ERROR					0x3A6
363 #define SRBM_INT_CNTL					0x3A8
364 #define SRBM_INT_ACK					0x3AA
365 
366 #define	SRBM_STATUS2				        0x3B1
367 #define		DMA_BUSY 				(1 << 5)
368 #define		DMA1_BUSY 				(1 << 6)
369 
370 #define VM_L2_CNTL					0x500
371 #define		ENABLE_L2_CACHE					(1 << 0)
372 #define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
373 #define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)
374 #define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)
375 #define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
376 #define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)
377 #define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)
378 #define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)
379 #define VM_L2_CNTL2					0x501
380 #define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
381 #define		INVALIDATE_L2_CACHE				(1 << 1)
382 #define		INVALIDATE_CACHE_MODE(x)			((x) << 26)
383 #define			INVALIDATE_PTE_AND_PDE_CACHES		0
384 #define			INVALIDATE_ONLY_PTE_CACHES		1
385 #define			INVALIDATE_ONLY_PDE_CACHES		2
386 #define VM_L2_CNTL3					0x502
387 #define		BANK_SELECT(x)					((x) << 0)
388 #define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)
389 #define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)
390 #define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)
391 #define	VM_L2_STATUS					0x503
392 #define		L2_BUSY						(1 << 0)
393 #define VM_CONTEXT0_CNTL				0x504
394 #define		ENABLE_CONTEXT					(1 << 0)
395 #define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
396 #define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)
397 #define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
398 #define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)
399 #define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)
400 #define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)
401 #define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)
402 #define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)
403 #define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)
404 #define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)
405 #define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)
406 #define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)
407 #define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)
408 #define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)
409 #define VM_CONTEXT1_CNTL				0x505
410 #define VM_CONTEXT0_CNTL2				0x50C
411 #define VM_CONTEXT1_CNTL2				0x50D
412 #define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x50E
413 #define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x50F
414 #define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x510
415 #define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x511
416 #define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x512
417 #define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x513
418 #define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x514
419 #define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x515
420 
421 #define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x53f
422 #define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x537
423 #define		PROTECTIONS_MASK			(0xf << 0)
424 #define		PROTECTIONS_SHIFT			0
425 		/* bit 0: range
426 		 * bit 1: pde0
427 		 * bit 2: valid
428 		 * bit 3: read
429 		 * bit 4: write
430 		 */
431 #define		MEMORY_CLIENT_ID_MASK			(0xff << 12)
432 #define		MEMORY_CLIENT_ID_SHIFT			12
433 #define		MEMORY_CLIENT_RW_MASK			(1 << 24)
434 #define		MEMORY_CLIENT_RW_SHIFT			24
435 #define		FAULT_VMID_MASK				(0xf << 25)
436 #define		FAULT_VMID_SHIFT			25
437 
438 #define VM_INVALIDATE_REQUEST				0x51E
439 #define VM_INVALIDATE_RESPONSE				0x51F
440 
441 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x546
442 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x547
443 
444 #define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x54F
445 #define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x550
446 #define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x551
447 #define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x552
448 #define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x553
449 #define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x554
450 #define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x555
451 #define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x556
452 #define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x557
453 #define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x558
454 
455 #define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x55F
456 #define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x560
457 
458 #define VM_L2_CG           				0x570
459 #define		MC_CG_ENABLE				(1 << 18)
460 #define		MC_LS_ENABLE				(1 << 19)
461 
462 #define MC_SHARED_CHMAP						0x801
463 #define		NOOFCHAN_SHIFT					12
464 #define		NOOFCHAN_MASK					0x0000f000
465 #define MC_SHARED_CHREMAP					0x802
466 
467 #define	MC_VM_FB_LOCATION				0x809
468 #define	MC_VM_AGP_TOP					0x80A
469 #define	MC_VM_AGP_BOT					0x80B
470 #define	MC_VM_AGP_BASE					0x80C
471 #define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x80D
472 #define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x80E
473 #define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x80F
474 
475 #define	MC_VM_MX_L1_TLB_CNTL				0x819
476 #define		ENABLE_L1_TLB					(1 << 0)
477 #define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
478 #define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
479 #define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
480 #define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
481 #define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
482 #define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
483 #define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)
484 
485 #define MC_SHARED_BLACKOUT_CNTL           		0x82B
486 
487 #define MC_HUB_MISC_HUB_CG           			0x82E
488 #define MC_HUB_MISC_VM_CG           			0x82F
489 
490 #define MC_HUB_MISC_SIP_CG           			0x830
491 
492 #define MC_XPB_CLK_GAT           			0x91E
493 
494 #define MC_CITF_MISC_RD_CG           			0x992
495 #define MC_CITF_MISC_WR_CG           			0x993
496 #define MC_CITF_MISC_VM_CG           			0x994
497 
498 #define	MC_ARB_RAMCFG					0x9D8
499 #define		NOOFBANK_SHIFT					0
500 #define		NOOFBANK_MASK					0x00000003
501 #define		NOOFRANK_SHIFT					2
502 #define		NOOFRANK_MASK					0x00000004
503 #define		NOOFROWS_SHIFT					3
504 #define		NOOFROWS_MASK					0x00000038
505 #define		NOOFCOLS_SHIFT					6
506 #define		NOOFCOLS_MASK					0x000000C0
507 #define		CHANSIZE_SHIFT					8
508 #define		CHANSIZE_MASK					0x00000100
509 #define		CHANSIZE_OVERRIDE				(1 << 11)
510 #define		NOOFGROUPS_SHIFT				12
511 #define		NOOFGROUPS_MASK					0x00001000
512 
513 #define	MC_ARB_DRAM_TIMING				0x9DD
514 #define	MC_ARB_DRAM_TIMING2				0x9DE
515 
516 #define MC_ARB_BURST_TIME                               0xA02
517 #define		STATE0(x)				((x) << 0)
518 #define		STATE0_MASK				(0x1f << 0)
519 #define		STATE0_SHIFT				0
520 #define		STATE1(x)				((x) << 5)
521 #define		STATE1_MASK				(0x1f << 5)
522 #define		STATE1_SHIFT				5
523 #define		STATE2(x)				((x) << 10)
524 #define		STATE2_MASK				(0x1f << 10)
525 #define		STATE2_SHIFT				10
526 #define		STATE3(x)				((x) << 15)
527 #define		STATE3_MASK				(0x1f << 15)
528 #define		STATE3_SHIFT				15
529 
530 #define	MC_SEQ_TRAIN_WAKEUP_CNTL			0xA3A
531 #define		TRAIN_DONE_D0      			(1 << 30)
532 #define		TRAIN_DONE_D1      			(1 << 31)
533 
534 #define MC_SEQ_SUP_CNTL           			0xA32
535 #define		RUN_MASK      				(1 << 0)
536 #define MC_SEQ_SUP_PGM           			0xA33
537 #define MC_PMG_AUTO_CMD           			0xA34
538 
539 #define MC_IO_PAD_CNTL_D0           			0xA74
540 #define		MEM_FALL_OUT_CMD      			(1 << 8)
541 
542 #define MC_SEQ_RAS_TIMING                               0xA28
543 #define MC_SEQ_CAS_TIMING                               0xA29
544 #define MC_SEQ_MISC_TIMING                              0xA2A
545 #define MC_SEQ_MISC_TIMING2                             0xA2B
546 #define MC_SEQ_PMG_TIMING                               0xA2C
547 #define MC_SEQ_RD_CTL_D0                                0xA2D
548 #define MC_SEQ_RD_CTL_D1                                0xA2E
549 #define MC_SEQ_WR_CTL_D0                                0xA2F
550 #define MC_SEQ_WR_CTL_D1                                0xA30
551 
552 #define MC_SEQ_MISC0           				0xA80
553 #define 	MC_SEQ_MISC0_VEN_ID_SHIFT               8
554 #define 	MC_SEQ_MISC0_VEN_ID_MASK                0x00000f00
555 #define 	MC_SEQ_MISC0_VEN_ID_VALUE               3
556 #define 	MC_SEQ_MISC0_REV_ID_SHIFT               12
557 #define 	MC_SEQ_MISC0_REV_ID_MASK                0x0000f000
558 #define 	MC_SEQ_MISC0_REV_ID_VALUE               1
559 #define 	MC_SEQ_MISC0_GDDR5_SHIFT                28
560 #define 	MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
561 #define 	MC_SEQ_MISC0_GDDR5_VALUE                5
562 #define MC_SEQ_MISC1                                    0xA81
563 #define MC_SEQ_RESERVE_M                                0xA82
564 #define MC_PMG_CMD_EMRS                                 0xA83
565 
566 #define MC_SEQ_IO_DEBUG_INDEX           		0xA91
567 #define MC_SEQ_IO_DEBUG_DATA           			0xA92
568 
569 #define MC_SEQ_MISC5                                    0xA95
570 #define MC_SEQ_MISC6                                    0xA96
571 
572 #define MC_SEQ_MISC7                                    0xA99
573 
574 #define MC_SEQ_RAS_TIMING_LP                            0xA9B
575 #define MC_SEQ_CAS_TIMING_LP                            0xA9C
576 #define MC_SEQ_MISC_TIMING_LP                           0xA9D
577 #define MC_SEQ_MISC_TIMING2_LP                          0xA9E
578 #define MC_SEQ_WR_CTL_D0_LP                             0xA9F
579 #define MC_SEQ_WR_CTL_D1_LP                             0xAA0
580 #define MC_SEQ_PMG_CMD_EMRS_LP                          0xAA1
581 #define MC_SEQ_PMG_CMD_MRS_LP                           0xAA2
582 
583 #define MC_PMG_CMD_MRS                                  0xAAB
584 
585 #define MC_SEQ_RD_CTL_D0_LP                             0xAC7
586 #define MC_SEQ_RD_CTL_D1_LP                             0xAC8
587 
588 #define MC_PMG_CMD_MRS1                                 0xAD1
589 #define MC_SEQ_PMG_CMD_MRS1_LP                          0xAD2
590 #define MC_SEQ_PMG_TIMING_LP                            0xAD3
591 
592 #define MC_SEQ_WR_CTL_2                                 0xAD5
593 #define MC_SEQ_WR_CTL_2_LP                              0xAD6
594 #define MC_PMG_CMD_MRS2                                 0xAD7
595 #define MC_SEQ_PMG_CMD_MRS2_LP                          0xAD8
596 
597 #define	MCLK_PWRMGT_CNTL				0xAE8
598 #       define DLL_SPEED(x)				((x) << 0)
599 #       define DLL_SPEED_MASK				(0x1f << 0)
600 #       define DLL_READY                                (1 << 6)
601 #       define MC_INT_CNTL                              (1 << 7)
602 #       define MRDCK0_PDNB                              (1 << 8)
603 #       define MRDCK1_PDNB                              (1 << 9)
604 #       define MRDCK0_RESET                             (1 << 16)
605 #       define MRDCK1_RESET                             (1 << 17)
606 #       define DLL_READY_READ                           (1 << 24)
607 #define	DLL_CNTL					0xAE9
608 #       define MRDCK0_BYPASS                            (1 << 24)
609 #       define MRDCK1_BYPASS                            (1 << 25)
610 
611 #define	MPLL_CNTL_MODE					0xAEC
612 #       define MPLL_MCLK_SEL                            (1 << 11)
613 #define	MPLL_FUNC_CNTL					0xAED
614 #define		BWCTRL(x)				((x) << 20)
615 #define		BWCTRL_MASK				(0xff << 20)
616 #define	MPLL_FUNC_CNTL_1				0xAEE
617 #define		VCO_MODE(x)				((x) << 0)
618 #define		VCO_MODE_MASK				(3 << 0)
619 #define		CLKFRAC(x)				((x) << 4)
620 #define		CLKFRAC_MASK				(0xfff << 4)
621 #define		CLKF(x)					((x) << 16)
622 #define		CLKF_MASK				(0xfff << 16)
623 #define	MPLL_FUNC_CNTL_2				0xAEF
624 #define	MPLL_AD_FUNC_CNTL				0xAF0
625 #define		YCLK_POST_DIV(x)			((x) << 0)
626 #define		YCLK_POST_DIV_MASK			(7 << 0)
627 #define	MPLL_DQ_FUNC_CNTL				0xAF1
628 #define		YCLK_SEL(x)				((x) << 4)
629 #define		YCLK_SEL_MASK				(1 << 4)
630 
631 #define	MPLL_SS1					0xAF3
632 #define		CLKV(x)					((x) << 0)
633 #define		CLKV_MASK				(0x3ffffff << 0)
634 #define	MPLL_SS2					0xAF4
635 #define		CLKS(x)					((x) << 0)
636 #define		CLKS_MASK				(0xfff << 0)
637 
638 #define	HDP_HOST_PATH_CNTL				0xB00
639 #define 	CLOCK_GATING_DIS			(1 << 23)
640 #define	HDP_NONSURFACE_BASE				0xB01
641 #define	HDP_NONSURFACE_INFO				0xB02
642 #define	HDP_NONSURFACE_SIZE				0xB03
643 
644 #define HDP_DEBUG0  					0xBCC
645 
646 #define HDP_ADDR_CONFIG  				0xBD2
647 #define HDP_MISC_CNTL					0xBD3
648 #define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)
649 #define HDP_MEM_POWER_LS				0xBD4
650 #define 	HDP_LS_ENABLE				(1 << 0)
651 
652 #define ATC_MISC_CG           				0xCD4
653 
654 #define IH_RB_CNTL                                        0xF80
655 #       define IH_RB_ENABLE                               (1 << 0)
656 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
657 #       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
658 #       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
659 #       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
660 #       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
661 #       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
662 #define IH_RB_BASE                                        0xF81
663 #define IH_RB_RPTR                                        0xF82
664 #define IH_RB_WPTR                                        0xF83
665 #       define RB_OVERFLOW                                (1 << 0)
666 #       define WPTR_OFFSET_MASK                           0x3fffc
667 #define IH_RB_WPTR_ADDR_HI                                0xF84
668 #define IH_RB_WPTR_ADDR_LO                                0xF85
669 #define IH_CNTL                                           0xF86
670 #       define ENABLE_INTR                                (1 << 0)
671 #       define IH_MC_SWAP(x)                              ((x) << 1)
672 #       define IH_MC_SWAP_NONE                            0
673 #       define IH_MC_SWAP_16BIT                           1
674 #       define IH_MC_SWAP_32BIT                           2
675 #       define IH_MC_SWAP_64BIT                           3
676 #       define RPTR_REARM                                 (1 << 4)
677 #       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
678 #       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
679 #       define MC_VMID(x)                                 ((x) << 25)
680 
681 #define	CONFIG_MEMSIZE					0x150A
682 
683 #define INTERRUPT_CNTL                                    0x151A
684 #       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)
685 #       define IH_DUMMY_RD_EN                             (1 << 1)
686 #       define IH_REQ_NONSNOOP_EN                         (1 << 3)
687 #       define GEN_IH_INT_EN                              (1 << 8)
688 #define INTERRUPT_CNTL2                                   0x151B
689 
690 #define HDP_MEM_COHERENCY_FLUSH_CNTL			0x1520
691 
692 #define	BIF_FB_EN						0x1524
693 #define		FB_READ_EN					(1 << 0)
694 #define		FB_WRITE_EN					(1 << 1)
695 
696 #define HDP_REG_COHERENCY_FLUSH_CNTL			0x1528
697 
698 /* DCE6 ELD audio interface */
699 #define AZ_F0_CODEC_ENDPOINT_INDEX                       0x1780
700 #       define AZ_ENDPOINT_REG_INDEX(x)                  (((x) & 0xff) << 0)
701 #       define AZ_ENDPOINT_REG_WRITE_EN                  (1 << 8)
702 #define AZ_F0_CODEC_ENDPOINT_DATA                        0x1781
703 
704 #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER          0x25
705 #define		SPEAKER_ALLOCATION(x)			(((x) & 0x7f) << 0)
706 #define		SPEAKER_ALLOCATION_MASK			(0x7f << 0)
707 #define		SPEAKER_ALLOCATION_SHIFT		0
708 #define		HDMI_CONNECTION				(1 << 16)
709 #define		DP_CONNECTION				(1 << 17)
710 
711 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0        0x28 /* LPCM */
712 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1        0x29 /* AC3 */
713 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2        0x2A /* MPEG1 */
714 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3        0x2B /* MP3 */
715 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4        0x2C /* MPEG2 */
716 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5        0x2D /* AAC */
717 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6        0x2E /* DTS */
718 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7        0x2F /* ATRAC */
719 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8        0x30 /* one bit audio - leave at 0 (default) */
720 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9        0x31 /* Dolby Digital */
721 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10       0x32 /* DTS-HD */
722 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11       0x33 /* MAT-MLP */
723 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12       0x34 /* DTS */
724 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13       0x35 /* WMA Pro */
725 #       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
726 /* max channels minus one.  7 = 8 channels */
727 #       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
728 #       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
729 #       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
730 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
731  * bit0 = 32 kHz
732  * bit1 = 44.1 kHz
733  * bit2 = 48 kHz
734  * bit3 = 88.2 kHz
735  * bit4 = 96 kHz
736  * bit5 = 176.4 kHz
737  * bit6 = 192 kHz
738  */
739 
740 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37
741 #       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)
742 #       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)
743 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC
744  * 0   = invalid
745  * x   = legal delay value
746  * 255 = sync not supported
747  */
748 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38
749 #       define HBR_CAPABLE                                (1 << 0) /* enabled by default */
750 
751 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a
752 #       define MANUFACTURER_ID(x)                        (((x) & 0xffff) << 0)
753 #       define PRODUCT_ID(x)                             (((x) & 0xffff) << 16)
754 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b
755 #       define SINK_DESCRIPTION_LEN(x)                   (((x) & 0xff) << 0)
756 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c
757 #       define PORT_ID0(x)                               (((x) & 0xffffffff) << 0)
758 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d
759 #       define PORT_ID1(x)                               (((x) & 0xffffffff) << 0)
760 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e
761 #       define DESCRIPTION0(x)                           (((x) & 0xff) << 0)
762 #       define DESCRIPTION1(x)                           (((x) & 0xff) << 8)
763 #       define DESCRIPTION2(x)                           (((x) & 0xff) << 16)
764 #       define DESCRIPTION3(x)                           (((x) & 0xff) << 24)
765 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f
766 #       define DESCRIPTION4(x)                           (((x) & 0xff) << 0)
767 #       define DESCRIPTION5(x)                           (((x) & 0xff) << 8)
768 #       define DESCRIPTION6(x)                           (((x) & 0xff) << 16)
769 #       define DESCRIPTION7(x)                           (((x) & 0xff) << 24)
770 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40
771 #       define DESCRIPTION8(x)                           (((x) & 0xff) << 0)
772 #       define DESCRIPTION9(x)                           (((x) & 0xff) << 8)
773 #       define DESCRIPTION10(x)                          (((x) & 0xff) << 16)
774 #       define DESCRIPTION11(x)                          (((x) & 0xff) << 24)
775 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41
776 #       define DESCRIPTION12(x)                          (((x) & 0xff) << 0)
777 #       define DESCRIPTION13(x)                          (((x) & 0xff) << 8)
778 #       define DESCRIPTION14(x)                          (((x) & 0xff) << 16)
779 #       define DESCRIPTION15(x)                          (((x) & 0xff) << 24)
780 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42
781 #       define DESCRIPTION16(x)                          (((x) & 0xff) << 0)
782 #       define DESCRIPTION17(x)                          (((x) & 0xff) << 8)
783 
784 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL         0x54
785 #       define AUDIO_ENABLED                             (1 << 31)
786 
787 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT  0x56
788 #define		PORT_CONNECTIVITY_MASK				(3 << 30)
789 #define		PORT_CONNECTIVITY_SHIFT				30
790 
791 #define	DC_LB_MEMORY_SPLIT					0x1AC3
792 #define		DC_LB_MEMORY_CONFIG(x)				((x) << 20)
793 
794 #define	PRIORITY_A_CNT						0x1AC6
795 #define		PRIORITY_MARK_MASK				0x7fff
796 #define		PRIORITY_OFF					(1 << 16)
797 #define		PRIORITY_ALWAYS_ON				(1 << 20)
798 #define	PRIORITY_B_CNT						0x1AC7
799 
800 #define	DPG_PIPE_ARBITRATION_CONTROL3				0x1B32
801 #       define LATENCY_WATERMARK_MASK(x)			((x) << 16)
802 #define	DPG_PIPE_LATENCY_CONTROL				0x1B33
803 #       define LATENCY_LOW_WATERMARK(x)				((x) << 0)
804 #       define LATENCY_HIGH_WATERMARK(x)			((x) << 16)
805 
806 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
807 #define VLINE_STATUS                                    0x1AEE
808 #       define VLINE_OCCURRED                           (1 << 0)
809 #       define VLINE_ACK                                (1 << 4)
810 #       define VLINE_STAT                               (1 << 12)
811 #       define VLINE_INTERRUPT                          (1 << 16)
812 #       define VLINE_INTERRUPT_TYPE                     (1 << 17)
813 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
814 #define VBLANK_STATUS                                   0x1AEF
815 #       define VBLANK_OCCURRED                          (1 << 0)
816 #       define VBLANK_ACK                               (1 << 4)
817 #       define VBLANK_STAT                              (1 << 12)
818 #       define VBLANK_INTERRUPT                         (1 << 16)
819 #       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
820 
821 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
822 #define INT_MASK                                        0x1AD0
823 #       define VBLANK_INT_MASK                          (1 << 0)
824 #       define VLINE_INT_MASK                           (1 << 4)
825 
826 #define DISP_INTERRUPT_STATUS                           0x183D
827 #       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
828 #       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
829 #       define DC_HPD1_INTERRUPT                        (1 << 17)
830 #       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
831 #       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
832 #       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
833 #       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
834 #       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
835 #define DISP_INTERRUPT_STATUS_CONTINUE                  0x183E
836 #       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
837 #       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
838 #       define DC_HPD2_INTERRUPT                        (1 << 17)
839 #       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
840 #       define DISP_TIMER_INTERRUPT                     (1 << 24)
841 #define DISP_INTERRUPT_STATUS_CONTINUE2                 0x183F
842 #       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
843 #       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
844 #       define DC_HPD3_INTERRUPT                        (1 << 17)
845 #       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
846 #define DISP_INTERRUPT_STATUS_CONTINUE3                 0x1840
847 #       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
848 #       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
849 #       define DC_HPD4_INTERRUPT                        (1 << 17)
850 #       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
851 #define DISP_INTERRUPT_STATUS_CONTINUE4                 0x1853
852 #       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
853 #       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
854 #       define DC_HPD5_INTERRUPT                        (1 << 17)
855 #       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
856 #define DISP_INTERRUPT_STATUS_CONTINUE5                 0x1854
857 #       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
858 #       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
859 #       define DC_HPD6_INTERRUPT                        (1 << 17)
860 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
861 
862 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
863 #define GRPH_INT_STATUS                                 0x1A16
864 #       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
865 #       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
866 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
867 #define	GRPH_INT_CONTROL			        0x1A17
868 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
869 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
870 
871 #define	DAC_AUTODETECT_INT_CONTROL			0x19F2
872 
873 #define DC_HPD1_INT_STATUS                              0x1807
874 #define DC_HPD2_INT_STATUS                              0x180A
875 #define DC_HPD3_INT_STATUS                              0x180D
876 #define DC_HPD4_INT_STATUS                              0x1810
877 #define DC_HPD5_INT_STATUS                              0x1813
878 #define DC_HPD6_INT_STATUS                              0x1816
879 #       define DC_HPDx_INT_STATUS                       (1 << 0)
880 #       define DC_HPDx_SENSE                            (1 << 1)
881 #       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
882 
883 #define DC_HPD1_INT_CONTROL                             0x1808
884 #define DC_HPD2_INT_CONTROL                             0x180B
885 #define DC_HPD3_INT_CONTROL                             0x180E
886 #define DC_HPD4_INT_CONTROL                             0x1811
887 #define DC_HPD5_INT_CONTROL                             0x1814
888 #define DC_HPD6_INT_CONTROL                             0x1817
889 #       define DC_HPDx_INT_ACK                          (1 << 0)
890 #       define DC_HPDx_INT_POLARITY                     (1 << 8)
891 #       define DC_HPDx_INT_EN                           (1 << 16)
892 #       define DC_HPDx_RX_INT_ACK                       (1 << 20)
893 #       define DC_HPDx_RX_INT_EN                        (1 << 24)
894 
895 #define DC_HPD1_CONTROL                                   0x1809
896 #define DC_HPD2_CONTROL                                   0x180C
897 #define DC_HPD3_CONTROL                                   0x180F
898 #define DC_HPD4_CONTROL                                   0x1812
899 #define DC_HPD5_CONTROL                                   0x1815
900 #define DC_HPD6_CONTROL                                   0x1818
901 #       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
902 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
903 #       define DC_HPDx_EN                                 (1 << 28)
904 
905 #define DPG_PIPE_STUTTER_CONTROL                          0x1B35
906 #       define STUTTER_ENABLE                             (1 << 0)
907 
908 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
909 #define CRTC_STATUS_FRAME_COUNT                         0x1BA6
910 
911 /* Audio clocks */
912 #define DCCG_AUDIO_DTO_SOURCE                           0x05ac
913 #       define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
914 #       define DCCG_AUDIO_DTO_SEL            (1 << 4)   /* 0=dto0 1=dto1 */
915 
916 #define DCCG_AUDIO_DTO0_PHASE                           0x05b0
917 #define DCCG_AUDIO_DTO0_MODULE                          0x05b4
918 #define DCCG_AUDIO_DTO1_PHASE                           0x05c0
919 #define DCCG_AUDIO_DTO1_MODULE                          0x05c4
920 
921 #define AFMT_AUDIO_SRC_CONTROL                          0x1c4f
922 #define		AFMT_AUDIO_SRC_SELECT(x)		(((x) & 7) << 0)
923 /* AFMT_AUDIO_SRC_SELECT
924  * 0 = stream0
925  * 1 = stream1
926  * 2 = stream2
927  * 3 = stream3
928  * 4 = stream4
929  * 5 = stream5
930  */
931 
932 #define	GRBM_CNTL					0x2000
933 #define		GRBM_READ_TIMEOUT(x)				((x) << 0)
934 
935 #define	GRBM_STATUS2					0x2002
936 #define		RLC_RQ_PENDING 					(1 << 0)
937 #define		RLC_BUSY 					(1 << 8)
938 #define		TC_BUSY 					(1 << 9)
939 
940 #define	GRBM_STATUS					0x2004
941 #define		CMDFIFO_AVAIL_MASK				0x0000000F
942 #define		RING2_RQ_PENDING				(1 << 4)
943 #define		SRBM_RQ_PENDING					(1 << 5)
944 #define		RING1_RQ_PENDING				(1 << 6)
945 #define		CF_RQ_PENDING					(1 << 7)
946 #define		PF_RQ_PENDING					(1 << 8)
947 #define		GDS_DMA_RQ_PENDING				(1 << 9)
948 #define		GRBM_EE_BUSY					(1 << 10)
949 #define		DB_CLEAN					(1 << 12)
950 #define		CB_CLEAN					(1 << 13)
951 #define		TA_BUSY 					(1 << 14)
952 #define		GDS_BUSY 					(1 << 15)
953 #define		VGT_BUSY					(1 << 17)
954 #define		IA_BUSY_NO_DMA					(1 << 18)
955 #define		IA_BUSY						(1 << 19)
956 #define		SX_BUSY 					(1 << 20)
957 #define		SPI_BUSY					(1 << 22)
958 #define		BCI_BUSY					(1 << 23)
959 #define		SC_BUSY 					(1 << 24)
960 #define		PA_BUSY 					(1 << 25)
961 #define		DB_BUSY 					(1 << 26)
962 #define		CP_COHERENCY_BUSY      				(1 << 28)
963 #define		CP_BUSY 					(1 << 29)
964 #define		CB_BUSY 					(1 << 30)
965 #define		GUI_ACTIVE					(1 << 31)
966 #define	GRBM_STATUS_SE0					0x2005
967 #define	GRBM_STATUS_SE1					0x2006
968 #define		SE_DB_CLEAN					(1 << 1)
969 #define		SE_CB_CLEAN					(1 << 2)
970 #define		SE_BCI_BUSY					(1 << 22)
971 #define		SE_VGT_BUSY					(1 << 23)
972 #define		SE_PA_BUSY					(1 << 24)
973 #define		SE_TA_BUSY					(1 << 25)
974 #define		SE_SX_BUSY					(1 << 26)
975 #define		SE_SPI_BUSY					(1 << 27)
976 #define		SE_SC_BUSY					(1 << 29)
977 #define		SE_DB_BUSY					(1 << 30)
978 #define		SE_CB_BUSY					(1 << 31)
979 
980 #define	GRBM_SOFT_RESET					0x2008
981 #define		SOFT_RESET_CP					(1 << 0)
982 #define		SOFT_RESET_CB					(1 << 1)
983 #define		SOFT_RESET_RLC					(1 << 2)
984 #define		SOFT_RESET_DB					(1 << 3)
985 #define		SOFT_RESET_GDS					(1 << 4)
986 #define		SOFT_RESET_PA					(1 << 5)
987 #define		SOFT_RESET_SC					(1 << 6)
988 #define		SOFT_RESET_BCI					(1 << 7)
989 #define		SOFT_RESET_SPI					(1 << 8)
990 #define		SOFT_RESET_SX					(1 << 10)
991 #define		SOFT_RESET_TC					(1 << 11)
992 #define		SOFT_RESET_TA					(1 << 12)
993 #define		SOFT_RESET_VGT					(1 << 14)
994 #define		SOFT_RESET_IA					(1 << 15)
995 
996 #define GRBM_GFX_INDEX          			0x200B
997 #define		INSTANCE_INDEX(x)			((x) << 0)
998 #define		SH_INDEX(x)     			((x) << 8)
999 #define		SE_INDEX(x)     			((x) << 16)
1000 #define		SH_BROADCAST_WRITES      		(1 << 29)
1001 #define		INSTANCE_BROADCAST_WRITES      		(1 << 30)
1002 #define		SE_BROADCAST_WRITES      		(1 << 31)
1003 
1004 #define GRBM_INT_CNTL                                   0x2018
1005 #       define RDERR_INT_ENABLE                         (1 << 0)
1006 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
1007 
1008 #define	CP_STRMOUT_CNTL					0x213F
1009 #define	SCRATCH_REG0					0x2140
1010 #define	SCRATCH_REG1					0x2141
1011 #define	SCRATCH_REG2					0x2142
1012 #define	SCRATCH_REG3					0x2143
1013 #define	SCRATCH_REG4					0x2144
1014 #define	SCRATCH_REG5					0x2145
1015 #define	SCRATCH_REG6					0x2146
1016 #define	SCRATCH_REG7					0x2147
1017 
1018 #define	SCRATCH_UMSK					0x2150
1019 #define	SCRATCH_ADDR					0x2151
1020 
1021 #define	CP_SEM_WAIT_TIMER				0x216F
1022 
1023 #define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x2172
1024 
1025 #define CP_ME_CNTL					0x21B6
1026 #define		CP_CE_HALT					(1 << 24)
1027 #define		CP_PFP_HALT					(1 << 26)
1028 #define		CP_ME_HALT					(1 << 28)
1029 
1030 #define	CP_COHER_CNTL2					0x217A
1031 
1032 #define	CP_RB2_RPTR					0x21BE
1033 #define	CP_RB1_RPTR					0x21BF
1034 #define	CP_RB0_RPTR					0x21C0
1035 #define	CP_RB_WPTR_DELAY				0x21C1
1036 
1037 #define	CP_QUEUE_THRESHOLDS				0x21D8
1038 #define		ROQ_IB1_START(x)				((x) << 0)
1039 #define		ROQ_IB2_START(x)				((x) << 8)
1040 #define CP_MEQ_THRESHOLDS				0x21D9
1041 #define		MEQ1_START(x)				((x) << 0)
1042 #define		MEQ2_START(x)				((x) << 8)
1043 
1044 #define	CP_PERFMON_CNTL					0x21FF
1045 
1046 #define	VGT_VTX_VECT_EJECT_REG				0x222C
1047 
1048 #define	VGT_CACHE_INVALIDATION				0x2231
1049 #define		CACHE_INVALIDATION(x)				((x) << 0)
1050 #define			VC_ONLY						0
1051 #define			TC_ONLY						1
1052 #define			VC_AND_TC					2
1053 #define		AUTO_INVLD_EN(x)				((x) << 6)
1054 #define			NO_AUTO						0
1055 #define			ES_AUTO						1
1056 #define			GS_AUTO						2
1057 #define			ES_AND_GS_AUTO					3
1058 #define	VGT_ESGS_RING_SIZE				0x2232
1059 #define	VGT_GSVS_RING_SIZE				0x2233
1060 
1061 #define	VGT_GS_VERTEX_REUSE				0x2235
1062 
1063 #define	VGT_PRIMITIVE_TYPE				0x2256
1064 #define	VGT_INDEX_TYPE					0x2257
1065 
1066 #define	VGT_NUM_INDICES					0x225C
1067 #define	VGT_NUM_INSTANCES				0x225D
1068 
1069 #define	VGT_TF_RING_SIZE				0x2262
1070 
1071 #define	VGT_HS_OFFCHIP_PARAM				0x226C
1072 
1073 #define	VGT_TF_MEMORY_BASE				0x226E
1074 
1075 #define CC_GC_SHADER_ARRAY_CONFIG			0x226F
1076 #define		INACTIVE_CUS_MASK			0xFFFF0000
1077 #define		INACTIVE_CUS_SHIFT			16
1078 #define GC_USER_SHADER_ARRAY_CONFIG			0x2270
1079 
1080 #define	PA_CL_ENHANCE					0x2285
1081 #define		CLIP_VTX_REORDER_ENA				(1 << 0)
1082 #define		NUM_CLIP_SEQ(x)					((x) << 1)
1083 
1084 #define	PA_SU_LINE_STIPPLE_VALUE			0x2298
1085 
1086 #define	PA_SC_LINE_STIPPLE_STATE			0x22C4
1087 
1088 #define	PA_SC_FORCE_EOV_MAX_CNTS			0x22C9
1089 #define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
1090 #define		FORCE_EOV_MAX_REZ_CNT(x)			((x) << 16)
1091 
1092 #define	PA_SC_FIFO_SIZE					0x22F3
1093 #define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) << 0)
1094 #define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) << 6)
1095 #define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 15)
1096 #define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 23)
1097 
1098 #define	PA_SC_ENHANCE					0x22FC
1099 
1100 #define	SQ_CONFIG					0x2300
1101 
1102 #define	SQC_CACHES					0x2302
1103 
1104 #define SQ_POWER_THROTTLE                               0x2396
1105 #define		MIN_POWER(x)				((x) << 0)
1106 #define		MIN_POWER_MASK				(0x3fff << 0)
1107 #define		MIN_POWER_SHIFT				0
1108 #define		MAX_POWER(x)				((x) << 16)
1109 #define		MAX_POWER_MASK				(0x3fff << 16)
1110 #define		MAX_POWER_SHIFT				0
1111 #define SQ_POWER_THROTTLE2                              0x2397
1112 #define		MAX_POWER_DELTA(x)			((x) << 0)
1113 #define		MAX_POWER_DELTA_MASK			(0x3fff << 0)
1114 #define		MAX_POWER_DELTA_SHIFT			0
1115 #define		STI_SIZE(x)				((x) << 16)
1116 #define		STI_SIZE_MASK				(0x3ff << 16)
1117 #define		STI_SIZE_SHIFT				16
1118 #define		LTI_RATIO(x)				((x) << 27)
1119 #define		LTI_RATIO_MASK				(0xf << 27)
1120 #define		LTI_RATIO_SHIFT				27
1121 
1122 #define	SX_DEBUG_1					0x2418
1123 
1124 #define	SPI_STATIC_THREAD_MGMT_1			0x2438
1125 #define	SPI_STATIC_THREAD_MGMT_2			0x2439
1126 #define	SPI_STATIC_THREAD_MGMT_3			0x243A
1127 #define	SPI_PS_MAX_WAVE_ID				0x243B
1128 
1129 #define	SPI_CONFIG_CNTL					0x2440
1130 
1131 #define	SPI_CONFIG_CNTL_1				0x244F
1132 #define		VTX_DONE_DELAY(x)				((x) << 0)
1133 #define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
1134 
1135 #define	CGTS_TCC_DISABLE				0x2452
1136 #define	CGTS_USER_TCC_DISABLE				0x2453
1137 #define		TCC_DISABLE_MASK				0xFFFF0000
1138 #define		TCC_DISABLE_SHIFT				16
1139 #define	CGTS_SM_CTRL_REG				0x2454
1140 #define		OVERRIDE				(1 << 21)
1141 #define		LS_OVERRIDE				(1 << 22)
1142 
1143 #define	SPI_LB_CU_MASK					0x24D5
1144 
1145 #define	TA_CNTL_AUX					0x2542
1146 
1147 #define CC_RB_BACKEND_DISABLE				0x263D
1148 #define		BACKEND_DISABLE(x)     			((x) << 16)
1149 #define GB_ADDR_CONFIG  				0x263E
1150 #define		NUM_PIPES(x)				((x) << 0)
1151 #define		NUM_PIPES_MASK				0x00000007
1152 #define		NUM_PIPES_SHIFT				0
1153 #define		PIPE_INTERLEAVE_SIZE(x)			((x) << 4)
1154 #define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070
1155 #define		PIPE_INTERLEAVE_SIZE_SHIFT		4
1156 #define		NUM_SHADER_ENGINES(x)			((x) << 12)
1157 #define		NUM_SHADER_ENGINES_MASK			0x00003000
1158 #define		NUM_SHADER_ENGINES_SHIFT		12
1159 #define		SHADER_ENGINE_TILE_SIZE(x)     		((x) << 16)
1160 #define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000
1161 #define		SHADER_ENGINE_TILE_SIZE_SHIFT		16
1162 #define		NUM_GPUS(x)     			((x) << 20)
1163 #define		NUM_GPUS_MASK				0x00700000
1164 #define		NUM_GPUS_SHIFT				20
1165 #define		MULTI_GPU_TILE_SIZE(x)     		((x) << 24)
1166 #define		MULTI_GPU_TILE_SIZE_MASK		0x03000000
1167 #define		MULTI_GPU_TILE_SIZE_SHIFT		24
1168 #define		ROW_SIZE(x)             		((x) << 28)
1169 #define		ROW_SIZE_MASK				0x30000000
1170 #define		ROW_SIZE_SHIFT				28
1171 
1172 #define	GB_TILE_MODE0					0x2644
1173 #       define MICRO_TILE_MODE(x)				((x) << 0)
1174 #              define	ADDR_SURF_DISPLAY_MICRO_TILING		0
1175 #              define	ADDR_SURF_THIN_MICRO_TILING		1
1176 #              define	ADDR_SURF_DEPTH_MICRO_TILING		2
1177 #       define ARRAY_MODE(x)					((x) << 2)
1178 #              define	ARRAY_LINEAR_GENERAL			0
1179 #              define	ARRAY_LINEAR_ALIGNED			1
1180 #              define	ARRAY_1D_TILED_THIN1			2
1181 #              define	ARRAY_2D_TILED_THIN1			4
1182 #       define PIPE_CONFIG(x)					((x) << 6)
1183 #              define	ADDR_SURF_P2				0
1184 #              define	ADDR_SURF_P4_8x16			4
1185 #              define	ADDR_SURF_P4_16x16			5
1186 #              define	ADDR_SURF_P4_16x32			6
1187 #              define	ADDR_SURF_P4_32x32			7
1188 #              define	ADDR_SURF_P8_16x16_8x16			8
1189 #              define	ADDR_SURF_P8_16x32_8x16			9
1190 #              define	ADDR_SURF_P8_32x32_8x16			10
1191 #              define	ADDR_SURF_P8_16x32_16x16		11
1192 #              define	ADDR_SURF_P8_32x32_16x16		12
1193 #              define	ADDR_SURF_P8_32x32_16x32		13
1194 #              define	ADDR_SURF_P8_32x64_32x32		14
1195 #       define TILE_SPLIT(x)					((x) << 11)
1196 #              define	ADDR_SURF_TILE_SPLIT_64B		0
1197 #              define	ADDR_SURF_TILE_SPLIT_128B		1
1198 #              define	ADDR_SURF_TILE_SPLIT_256B		2
1199 #              define	ADDR_SURF_TILE_SPLIT_512B		3
1200 #              define	ADDR_SURF_TILE_SPLIT_1KB		4
1201 #              define	ADDR_SURF_TILE_SPLIT_2KB		5
1202 #              define	ADDR_SURF_TILE_SPLIT_4KB		6
1203 #       define BANK_WIDTH(x)					((x) << 14)
1204 #              define	ADDR_SURF_BANK_WIDTH_1			0
1205 #              define	ADDR_SURF_BANK_WIDTH_2			1
1206 #              define	ADDR_SURF_BANK_WIDTH_4			2
1207 #              define	ADDR_SURF_BANK_WIDTH_8			3
1208 #       define BANK_HEIGHT(x)					((x) << 16)
1209 #              define	ADDR_SURF_BANK_HEIGHT_1			0
1210 #              define	ADDR_SURF_BANK_HEIGHT_2			1
1211 #              define	ADDR_SURF_BANK_HEIGHT_4			2
1212 #              define	ADDR_SURF_BANK_HEIGHT_8			3
1213 #       define MACRO_TILE_ASPECT(x)				((x) << 18)
1214 #              define	ADDR_SURF_MACRO_ASPECT_1		0
1215 #              define	ADDR_SURF_MACRO_ASPECT_2		1
1216 #              define	ADDR_SURF_MACRO_ASPECT_4		2
1217 #              define	ADDR_SURF_MACRO_ASPECT_8		3
1218 #       define NUM_BANKS(x)					((x) << 20)
1219 #              define	ADDR_SURF_2_BANK			0
1220 #              define	ADDR_SURF_4_BANK			1
1221 #              define	ADDR_SURF_8_BANK			2
1222 #              define	ADDR_SURF_16_BANK			3
1223 #define	GB_TILE_MODE1					0x2645
1224 #define	GB_TILE_MODE2					0x2646
1225 #define	GB_TILE_MODE3					0x2647
1226 #define	GB_TILE_MODE4					0x2648
1227 #define	GB_TILE_MODE5					0x2649
1228 #define	GB_TILE_MODE6					0x264a
1229 #define	GB_TILE_MODE7					0x264b
1230 #define	GB_TILE_MODE8					0x264c
1231 #define	GB_TILE_MODE9					0x264d
1232 #define	GB_TILE_MODE10					0x264e
1233 #define	GB_TILE_MODE11					0x264f
1234 #define	GB_TILE_MODE12					0x2650
1235 #define	GB_TILE_MODE13					0x2651
1236 #define	GB_TILE_MODE14					0x2652
1237 #define	GB_TILE_MODE15					0x2653
1238 #define	GB_TILE_MODE16					0x2654
1239 #define	GB_TILE_MODE17					0x2655
1240 #define	GB_TILE_MODE18					0x2656
1241 #define	GB_TILE_MODE19					0x2657
1242 #define	GB_TILE_MODE20					0x2658
1243 #define	GB_TILE_MODE21					0x2659
1244 #define	GB_TILE_MODE22					0x265a
1245 #define	GB_TILE_MODE23					0x265b
1246 #define	GB_TILE_MODE24					0x265c
1247 #define	GB_TILE_MODE25					0x265d
1248 #define	GB_TILE_MODE26					0x265e
1249 #define	GB_TILE_MODE27					0x265f
1250 #define	GB_TILE_MODE28					0x2660
1251 #define	GB_TILE_MODE29					0x2661
1252 #define	GB_TILE_MODE30					0x2662
1253 #define	GB_TILE_MODE31					0x2663
1254 
1255 #define	CB_PERFCOUNTER0_SELECT0				0x2688
1256 #define	CB_PERFCOUNTER0_SELECT1				0x2689
1257 #define	CB_PERFCOUNTER1_SELECT0				0x268A
1258 #define	CB_PERFCOUNTER1_SELECT1				0x268B
1259 #define	CB_PERFCOUNTER2_SELECT0				0x268C
1260 #define	CB_PERFCOUNTER2_SELECT1				0x268D
1261 #define	CB_PERFCOUNTER3_SELECT0				0x268E
1262 #define	CB_PERFCOUNTER3_SELECT1				0x268F
1263 
1264 #define	CB_CGTT_SCLK_CTRL				0x2698
1265 
1266 #define	GC_USER_RB_BACKEND_DISABLE			0x26DF
1267 #define		BACKEND_DISABLE_MASK			0x00FF0000
1268 #define		BACKEND_DISABLE_SHIFT			16
1269 
1270 #define	TCP_CHAN_STEER_LO				0x2B03
1271 #define	TCP_CHAN_STEER_HI				0x2B94
1272 
1273 #define	CP_RB0_BASE					0x3040
1274 #define	CP_RB0_CNTL					0x3041
1275 #define		RB_BUFSZ(x)					((x) << 0)
1276 #define		RB_BLKSZ(x)					((x) << 8)
1277 #define		BUF_SWAP_32BIT					(2 << 16)
1278 #define		RB_NO_UPDATE					(1 << 27)
1279 #define		RB_RPTR_WR_ENA					(1 << 31)
1280 
1281 #define	CP_RB0_RPTR_ADDR				0x3043
1282 #define	CP_RB0_RPTR_ADDR_HI				0x3044
1283 #define	CP_RB0_WPTR					0x3045
1284 
1285 #define	CP_PFP_UCODE_ADDR				0x3054
1286 #define	CP_PFP_UCODE_DATA				0x3055
1287 #define	CP_ME_RAM_RADDR					0x3056
1288 #define	CP_ME_RAM_WADDR					0x3057
1289 #define	CP_ME_RAM_DATA					0x3058
1290 
1291 #define	CP_CE_UCODE_ADDR				0x305A
1292 #define	CP_CE_UCODE_DATA				0x305B
1293 
1294 #define	CP_RB1_BASE					0x3060
1295 #define	CP_RB1_CNTL					0x3061
1296 #define	CP_RB1_RPTR_ADDR				0x3062
1297 #define	CP_RB1_RPTR_ADDR_HI				0x3063
1298 #define	CP_RB1_WPTR					0x3064
1299 #define	CP_RB2_BASE					0x3065
1300 #define	CP_RB2_CNTL					0x3066
1301 #define	CP_RB2_RPTR_ADDR				0x3067
1302 #define	CP_RB2_RPTR_ADDR_HI				0x3068
1303 #define	CP_RB2_WPTR					0x3069
1304 #define CP_INT_CNTL_RING0                               0x306A
1305 #define CP_INT_CNTL_RING1                               0x306B
1306 #define CP_INT_CNTL_RING2                               0x306C
1307 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
1308 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
1309 #       define WAIT_MEM_SEM_INT_ENABLE                  (1 << 21)
1310 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
1311 #       define CP_RINGID2_INT_ENABLE                    (1 << 29)
1312 #       define CP_RINGID1_INT_ENABLE                    (1 << 30)
1313 #       define CP_RINGID0_INT_ENABLE                    (1 << 31)
1314 #define CP_INT_STATUS_RING0                             0x306D
1315 #define CP_INT_STATUS_RING1                             0x306E
1316 #define CP_INT_STATUS_RING2                             0x306F
1317 #       define WAIT_MEM_SEM_INT_STAT                    (1 << 21)
1318 #       define TIME_STAMP_INT_STAT                      (1 << 26)
1319 #       define CP_RINGID2_INT_STAT                      (1 << 29)
1320 #       define CP_RINGID1_INT_STAT                      (1 << 30)
1321 #       define CP_RINGID0_INT_STAT                      (1 << 31)
1322 
1323 #define	CP_MEM_SLP_CNTL					0x3079
1324 #       define CP_MEM_LS_EN                             (1 << 0)
1325 
1326 #define	CP_DEBUG					0x307F
1327 
1328 #define RLC_CNTL                                          0x30C0
1329 #       define RLC_ENABLE                                 (1 << 0)
1330 #define RLC_RL_BASE                                       0x30C1
1331 #define RLC_RL_SIZE                                       0x30C2
1332 #define RLC_LB_CNTL                                       0x30C3
1333 #       define LOAD_BALANCE_ENABLE                        (1 << 0)
1334 #define RLC_SAVE_AND_RESTORE_BASE                         0x30C4
1335 #define RLC_LB_CNTR_MAX                                   0x30C5
1336 #define RLC_LB_CNTR_INIT                                  0x30C6
1337 
1338 #define RLC_CLEAR_STATE_RESTORE_BASE                      0x30C8
1339 
1340 #define RLC_UCODE_ADDR                                    0x30CB
1341 #define RLC_UCODE_DATA                                    0x30CC
1342 
1343 #define RLC_GPU_CLOCK_COUNT_LSB                           0x30CE
1344 #define RLC_GPU_CLOCK_COUNT_MSB                           0x30CF
1345 #define RLC_CAPTURE_GPU_CLOCK_COUNT                       0x30D0
1346 #define RLC_MC_CNTL                                       0x30D1
1347 #define RLC_UCODE_CNTL                                    0x30D2
1348 #define RLC_STAT                                          0x30D3
1349 #       define RLC_BUSY_STATUS                            (1 << 0)
1350 #       define GFX_POWER_STATUS                           (1 << 1)
1351 #       define GFX_CLOCK_STATUS                           (1 << 2)
1352 #       define GFX_LS_STATUS                              (1 << 3)
1353 
1354 #define	RLC_PG_CNTL					0x30D7
1355 #	define GFX_PG_ENABLE				(1 << 0)
1356 #	define GFX_PG_SRC				(1 << 1)
1357 
1358 #define	RLC_CGTT_MGCG_OVERRIDE				0x3100
1359 #define	RLC_CGCG_CGLS_CTRL				0x3101
1360 #	define CGCG_EN					(1 << 0)
1361 #	define CGLS_EN					(1 << 1)
1362 
1363 #define	RLC_TTOP_D					0x3105
1364 #	define RLC_PUD(x)				((x) << 0)
1365 #	define RLC_PUD_MASK				(0xff << 0)
1366 #	define RLC_PDD(x)				((x) << 8)
1367 #	define RLC_PDD_MASK				(0xff << 8)
1368 #	define RLC_TTPD(x)				((x) << 16)
1369 #	define RLC_TTPD_MASK				(0xff << 16)
1370 #	define RLC_MSD(x)				((x) << 24)
1371 #	define RLC_MSD_MASK				(0xff << 24)
1372 
1373 #define RLC_LB_INIT_CU_MASK                               0x3107
1374 
1375 #define	RLC_PG_AO_CU_MASK				0x310B
1376 #define	RLC_MAX_PG_CU					0x310C
1377 #	define MAX_PU_CU(x)				((x) << 0)
1378 #	define MAX_PU_CU_MASK				(0xff << 0)
1379 #define	RLC_AUTO_PG_CTRL				0x310C
1380 #	define AUTO_PG_EN				(1 << 0)
1381 #	define GRBM_REG_SGIT(x)				((x) << 3)
1382 #	define GRBM_REG_SGIT_MASK			(0xffff << 3)
1383 #	define PG_AFTER_GRBM_REG_ST(x)			((x) << 19)
1384 #	define PG_AFTER_GRBM_REG_ST_MASK		(0x1fff << 19)
1385 
1386 #define RLC_SERDES_WR_MASTER_MASK_0                       0x3115
1387 #define RLC_SERDES_WR_MASTER_MASK_1                       0x3116
1388 #define RLC_SERDES_WR_CTRL                                0x3117
1389 
1390 #define RLC_SERDES_MASTER_BUSY_0                          0x3119
1391 #define RLC_SERDES_MASTER_BUSY_1                          0x311A
1392 
1393 #define RLC_GCPM_GENERAL_3                                0x311E
1394 
1395 #define	DB_RENDER_CONTROL				0xA000
1396 
1397 #define DB_DEPTH_INFO                                   0xA00F
1398 
1399 #define PA_SC_RASTER_CONFIG                             0xA0D4
1400 #	define RB_MAP_PKR0(x)				((x) << 0)
1401 #	define RB_MAP_PKR0_MASK				(0x3 << 0)
1402 #	define RB_MAP_PKR1(x)				((x) << 2)
1403 #	define RB_MAP_PKR1_MASK				(0x3 << 2)
1404 #       define RASTER_CONFIG_RB_MAP_0                   0
1405 #       define RASTER_CONFIG_RB_MAP_1                   1
1406 #       define RASTER_CONFIG_RB_MAP_2                   2
1407 #       define RASTER_CONFIG_RB_MAP_3                   3
1408 #	define RB_XSEL2(x)				((x) << 4)
1409 #	define RB_XSEL2_MASK				(0x3 << 4)
1410 #	define RB_XSEL					(1 << 6)
1411 #	define RB_YSEL					(1 << 7)
1412 #	define PKR_MAP(x)				((x) << 8)
1413 #	define PKR_MAP_MASK				(0x3 << 8)
1414 #       define RASTER_CONFIG_PKR_MAP_0			0
1415 #       define RASTER_CONFIG_PKR_MAP_1			1
1416 #       define RASTER_CONFIG_PKR_MAP_2			2
1417 #       define RASTER_CONFIG_PKR_MAP_3			3
1418 #	define PKR_XSEL(x)				((x) << 10)
1419 #	define PKR_XSEL_MASK				(0x3 << 10)
1420 #	define PKR_YSEL(x)				((x) << 12)
1421 #	define PKR_YSEL_MASK				(0x3 << 12)
1422 #	define SC_MAP(x)				((x) << 16)
1423 #	define SC_MAP_MASK				(0x3 << 16)
1424 #	define SC_XSEL(x)				((x) << 18)
1425 #	define SC_XSEL_MASK				(0x3 << 18)
1426 #	define SC_YSEL(x)				((x) << 20)
1427 #	define SC_YSEL_MASK				(0x3 << 20)
1428 #	define SE_MAP(x)				((x) << 24)
1429 #	define SE_MAP_MASK				(0x3 << 24)
1430 #       define RASTER_CONFIG_SE_MAP_0			0
1431 #       define RASTER_CONFIG_SE_MAP_1			1
1432 #       define RASTER_CONFIG_SE_MAP_2			2
1433 #       define RASTER_CONFIG_SE_MAP_3			3
1434 #	define SE_XSEL(x)				((x) << 26)
1435 #	define SE_XSEL_MASK				(0x3 << 26)
1436 #	define SE_YSEL(x)				((x) << 28)
1437 #	define SE_YSEL_MASK				(0x3 << 28)
1438 
1439 
1440 #define VGT_EVENT_INITIATOR                             0xA2A4
1441 #       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
1442 #       define SAMPLE_STREAMOUTSTATS2                   (2 << 0)
1443 #       define SAMPLE_STREAMOUTSTATS3                   (3 << 0)
1444 #       define CACHE_FLUSH_TS                           (4 << 0)
1445 #       define CACHE_FLUSH                              (6 << 0)
1446 #       define CS_PARTIAL_FLUSH                         (7 << 0)
1447 #       define VGT_STREAMOUT_RESET                      (10 << 0)
1448 #       define END_OF_PIPE_INCR_DE                      (11 << 0)
1449 #       define END_OF_PIPE_IB_END                       (12 << 0)
1450 #       define RST_PIX_CNT                              (13 << 0)
1451 #       define VS_PARTIAL_FLUSH                         (15 << 0)
1452 #       define PS_PARTIAL_FLUSH                         (16 << 0)
1453 #       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 << 0)
1454 #       define ZPASS_DONE                               (21 << 0)
1455 #       define CACHE_FLUSH_AND_INV_EVENT                (22 << 0)
1456 #       define PERFCOUNTER_START                        (23 << 0)
1457 #       define PERFCOUNTER_STOP                         (24 << 0)
1458 #       define PIPELINESTAT_START                       (25 << 0)
1459 #       define PIPELINESTAT_STOP                        (26 << 0)
1460 #       define PERFCOUNTER_SAMPLE                       (27 << 0)
1461 #       define SAMPLE_PIPELINESTAT                      (30 << 0)
1462 #       define SAMPLE_STREAMOUTSTATS                    (32 << 0)
1463 #       define RESET_VTX_CNT                            (33 << 0)
1464 #       define VGT_FLUSH                                (36 << 0)
1465 #       define BOTTOM_OF_PIPE_TS                        (40 << 0)
1466 #       define DB_CACHE_FLUSH_AND_INV                   (42 << 0)
1467 #       define FLUSH_AND_INV_DB_DATA_TS                 (43 << 0)
1468 #       define FLUSH_AND_INV_DB_META                    (44 << 0)
1469 #       define FLUSH_AND_INV_CB_DATA_TS                 (45 << 0)
1470 #       define FLUSH_AND_INV_CB_META                    (46 << 0)
1471 #       define CS_DONE                                  (47 << 0)
1472 #       define PS_DONE                                  (48 << 0)
1473 #       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 << 0)
1474 #       define THREAD_TRACE_START                       (51 << 0)
1475 #       define THREAD_TRACE_STOP                        (52 << 0)
1476 #       define THREAD_TRACE_FLUSH                       (54 << 0)
1477 #       define THREAD_TRACE_FINISH                      (55 << 0)
1478 
1479 /* PIF PHY0 registers idx/data 0x8/0xc */
1480 #define PB0_PIF_CNTL                                      0x10
1481 #       define LS2_EXIT_TIME(x)                           ((x) << 17)
1482 #       define LS2_EXIT_TIME_MASK                         (0x7 << 17)
1483 #       define LS2_EXIT_TIME_SHIFT                        17
1484 #define PB0_PIF_PAIRING                                   0x11
1485 #       define MULTI_PIF                                  (1 << 25)
1486 #define PB0_PIF_PWRDOWN_0                                 0x12
1487 #       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)
1488 #       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 << 7)
1489 #       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7
1490 #       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) << 10)
1491 #       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 << 10)
1492 #       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10
1493 #       define PLL_RAMP_UP_TIME_0(x)                      ((x) << 24)
1494 #       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 << 24)
1495 #       define PLL_RAMP_UP_TIME_0_SHIFT                   24
1496 #define PB0_PIF_PWRDOWN_1                                 0x13
1497 #       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) << 7)
1498 #       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 << 7)
1499 #       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7
1500 #       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) << 10)
1501 #       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 << 10)
1502 #       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10
1503 #       define PLL_RAMP_UP_TIME_1(x)                      ((x) << 24)
1504 #       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 << 24)
1505 #       define PLL_RAMP_UP_TIME_1_SHIFT                   24
1506 
1507 #define PB0_PIF_PWRDOWN_2                                 0x17
1508 #       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) << 7)
1509 #       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 << 7)
1510 #       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7
1511 #       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) << 10)
1512 #       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 << 10)
1513 #       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10
1514 #       define PLL_RAMP_UP_TIME_2(x)                      ((x) << 24)
1515 #       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 << 24)
1516 #       define PLL_RAMP_UP_TIME_2_SHIFT                   24
1517 #define PB0_PIF_PWRDOWN_3                                 0x18
1518 #       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) << 7)
1519 #       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 << 7)
1520 #       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7
1521 #       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) << 10)
1522 #       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 << 10)
1523 #       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10
1524 #       define PLL_RAMP_UP_TIME_3(x)                      ((x) << 24)
1525 #       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 << 24)
1526 #       define PLL_RAMP_UP_TIME_3_SHIFT                   24
1527 /* PIF PHY1 registers idx/data 0x10/0x14 */
1528 #define PB1_PIF_CNTL                                      0x10
1529 #define PB1_PIF_PAIRING                                   0x11
1530 #define PB1_PIF_PWRDOWN_0                                 0x12
1531 #define PB1_PIF_PWRDOWN_1                                 0x13
1532 
1533 #define PB1_PIF_PWRDOWN_2                                 0x17
1534 #define PB1_PIF_PWRDOWN_3                                 0x18
1535 /* PCIE registers idx/data 0x30/0x34 */
1536 #define PCIE_CNTL2                                        0x1c /* PCIE */
1537 #       define SLV_MEM_LS_EN                              (1 << 16)
1538 #       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 << 17)
1539 #       define MST_MEM_LS_EN                              (1 << 18)
1540 #       define REPLAY_MEM_LS_EN                           (1 << 19)
1541 #define PCIE_LC_STATUS1                                   0x28 /* PCIE */
1542 #       define LC_REVERSE_RCVR                            (1 << 0)
1543 #       define LC_REVERSE_XMIT                            (1 << 1)
1544 #       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 << 2)
1545 #       define LC_OPERATING_LINK_WIDTH_SHIFT              2
1546 #       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 << 5)
1547 #       define LC_DETECTED_LINK_WIDTH_SHIFT               5
1548 
1549 #define PCIE_P_CNTL                                       0x40 /* PCIE */
1550 #       define P_IGNORE_EDB_ERR                           (1 << 6)
1551 
1552 /* PCIE PORT registers idx/data 0x38/0x3c */
1553 #define PCIE_LC_CNTL                                      0xa0
1554 #       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
1555 #       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
1556 #       define LC_L0S_INACTIVITY_SHIFT                    8
1557 #       define LC_L1_INACTIVITY(x)                        ((x) << 12)
1558 #       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
1559 #       define LC_L1_INACTIVITY_SHIFT                     12
1560 #       define LC_PMI_TO_L1_DIS                           (1 << 16)
1561 #       define LC_ASPM_TO_L1_DIS                          (1 << 24)
1562 #define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
1563 #       define LC_LINK_WIDTH_SHIFT                        0
1564 #       define LC_LINK_WIDTH_MASK                         0x7
1565 #       define LC_LINK_WIDTH_X0                           0
1566 #       define LC_LINK_WIDTH_X1                           1
1567 #       define LC_LINK_WIDTH_X2                           2
1568 #       define LC_LINK_WIDTH_X4                           3
1569 #       define LC_LINK_WIDTH_X8                           4
1570 #       define LC_LINK_WIDTH_X16                          6
1571 #       define LC_LINK_WIDTH_RD_SHIFT                     4
1572 #       define LC_LINK_WIDTH_RD_MASK                      0x70
1573 #       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
1574 #       define LC_RECONFIG_NOW                            (1 << 8)
1575 #       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
1576 #       define LC_RENEGOTIATE_EN                          (1 << 10)
1577 #       define LC_SHORT_RECONFIG_EN                       (1 << 11)
1578 #       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
1579 #       define LC_UPCONFIGURE_DIS                         (1 << 13)
1580 #       define LC_DYN_LANES_PWR_STATE(x)                  ((x) << 21)
1581 #       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 << 21)
1582 #       define LC_DYN_LANES_PWR_STATE_SHIFT               21
1583 #define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */
1584 #       define LC_XMIT_N_FTS(x)                           ((x) << 0)
1585 #       define LC_XMIT_N_FTS_MASK                         (0xff << 0)
1586 #       define LC_XMIT_N_FTS_SHIFT                        0
1587 #       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 << 8)
1588 #       define LC_N_FTS_MASK                              (0xff << 24)
1589 #define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
1590 #       define LC_GEN2_EN_STRAP                           (1 << 0)
1591 #       define LC_GEN3_EN_STRAP                           (1 << 1)
1592 #       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 2)
1593 #       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 << 3)
1594 #       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3
1595 #       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 << 5)
1596 #       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 << 6)
1597 #       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 7)
1598 #       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 8)
1599 #       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 9)
1600 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 10)
1601 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10
1602 #       define LC_CURRENT_DATA_RATE_MASK                  (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1603 #       define LC_CURRENT_DATA_RATE_SHIFT                 13
1604 #       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 16)
1605 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 18)
1606 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 19)
1607 #       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 << 20)
1608 #       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 << 21)
1609 
1610 #define PCIE_LC_CNTL2                                     0xb1
1611 #       define LC_ALLOW_PDWN_IN_L1                        (1 << 17)
1612 #       define LC_ALLOW_PDWN_IN_L23                       (1 << 18)
1613 
1614 #define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */
1615 #       define LC_GO_TO_RECOVERY                          (1 << 30)
1616 #define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */
1617 #       define LC_REDO_EQ                                 (1 << 5)
1618 #       define LC_SET_QUIESCE                             (1 << 13)
1619 
1620 /*
1621  * UVD
1622  */
1623 #define UVD_UDEC_ADDR_CONFIG				0x3bd3
1624 #define UVD_UDEC_DB_ADDR_CONFIG				0x3bd4
1625 #define UVD_UDEC_DBW_ADDR_CONFIG			0x3bd5
1626 #define UVD_RBC_RB_RPTR					0x3da4
1627 #define UVD_RBC_RB_WPTR					0x3da5
1628 #define UVD_STATUS					0x3daf
1629 
1630 #define	UVD_CGC_CTRL					0x3dc2
1631 #	define DCM					(1 << 0)
1632 #	define CG_DT(x)					((x) << 2)
1633 #	define CG_DT_MASK				(0xf << 2)
1634 #	define CLK_OD(x)				((x) << 6)
1635 #	define CLK_OD_MASK				(0x1f << 6)
1636 
1637  /* UVD CTX indirect */
1638 #define	UVD_CGC_MEM_CTRL				0xC0
1639 #define	UVD_CGC_CTRL2					0xC1
1640 #	define DYN_OR_EN				(1 << 0)
1641 #	define DYN_RR_EN				(1 << 1)
1642 #	define G_DIV_ID(x)				((x) << 2)
1643 #	define G_DIV_ID_MASK				(0x7 << 2)
1644 
1645 /*
1646  * PM4
1647  */
1648 #define PACKET_TYPE0    0
1649 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |				\
1650                          ((reg) & 0xFFFF) |				\
1651                          ((n) & 0x3FFF) << 16)
1652 #define CP_PACKET2			0x80000000
1653 #define		PACKET2_PAD_SHIFT		0
1654 #define		PACKET2_PAD_MASK		(0x3fffffff << 0)
1655 
1656 #define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1657 #define RADEON_PACKET_TYPE3 3
1658 #define PACKET3(op, n)	((RADEON_PACKET_TYPE3 << 30) |			\
1659 			 (((op) & 0xFF) << 8) |				\
1660 			 ((n) & 0x3FFF) << 16)
1661 
1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1663 
1664 /* Packet 3 types */
1665 #define	PACKET3_NOP					0x10
1666 #define	PACKET3_SET_BASE				0x11
1667 #define		PACKET3_BASE_INDEX(x)                  ((x) << 0)
1668 #define			GDS_PARTITION_BASE		2
1669 #define			CE_PARTITION_BASE		3
1670 #define	PACKET3_CLEAR_STATE				0x12
1671 #define	PACKET3_INDEX_BUFFER_SIZE			0x13
1672 #define	PACKET3_DISPATCH_DIRECT				0x15
1673 #define	PACKET3_DISPATCH_INDIRECT			0x16
1674 #define	PACKET3_ALLOC_GDS				0x1B
1675 #define	PACKET3_WRITE_GDS_RAM				0x1C
1676 #define	PACKET3_ATOMIC_GDS				0x1D
1677 #define	PACKET3_ATOMIC					0x1E
1678 #define	PACKET3_OCCLUSION_QUERY				0x1F
1679 #define	PACKET3_SET_PREDICATION				0x20
1680 #define	PACKET3_REG_RMW					0x21
1681 #define	PACKET3_COND_EXEC				0x22
1682 #define	PACKET3_PRED_EXEC				0x23
1683 #define	PACKET3_DRAW_INDIRECT				0x24
1684 #define	PACKET3_DRAW_INDEX_INDIRECT			0x25
1685 #define	PACKET3_INDEX_BASE				0x26
1686 #define	PACKET3_DRAW_INDEX_2				0x27
1687 #define	PACKET3_CONTEXT_CONTROL				0x28
1688 #define	PACKET3_INDEX_TYPE				0x2A
1689 #define	PACKET3_DRAW_INDIRECT_MULTI			0x2C
1690 #define	PACKET3_DRAW_INDEX_AUTO				0x2D
1691 #define	PACKET3_DRAW_INDEX_IMMD				0x2E
1692 #define	PACKET3_NUM_INSTANCES				0x2F
1693 #define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
1694 #define	PACKET3_INDIRECT_BUFFER_CONST			0x31
1695 #define	PACKET3_INDIRECT_BUFFER				0x3F
1696 #define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
1697 #define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
1698 #define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36
1699 #define	PACKET3_WRITE_DATA				0x37
1700 #define		WRITE_DATA_DST_SEL(x)                   ((x) << 8)
1701                 /* 0 - register
1702 		 * 1 - memory (sync - via GRBM)
1703 		 * 2 - tc/l2
1704 		 * 3 - gds
1705 		 * 4 - reserved
1706 		 * 5 - memory (async - direct)
1707 		 */
1708 #define		WR_ONE_ADDR                             (1 << 16)
1709 #define		WR_CONFIRM                              (1 << 20)
1710 #define		WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
1711                 /* 0 - me
1712 		 * 1 - pfp
1713 		 * 2 - ce
1714 		 */
1715 #define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
1716 #define	PACKET3_MEM_SEMAPHORE				0x39
1717 #define	PACKET3_MPEG_INDEX				0x3A
1718 #define	PACKET3_COPY_DW					0x3B
1719 #define	PACKET3_WAIT_REG_MEM				0x3C
1720 #define		WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
1721                 /* 0 - always
1722 		 * 1 - <
1723 		 * 2 - <=
1724 		 * 3 - ==
1725 		 * 4 - !=
1726 		 * 5 - >=
1727 		 * 6 - >
1728 		 */
1729 #define		WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
1730                 /* 0 - reg
1731 		 * 1 - mem
1732 		 */
1733 #define		WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
1734                 /* 0 - me
1735 		 * 1 - pfp
1736 		 */
1737 #define	PACKET3_MEM_WRITE				0x3D
1738 #define	PACKET3_COPY_DATA				0x40
1739 #define	PACKET3_CP_DMA					0x41
1740 /* 1. header
1741  * 2. SRC_ADDR_LO or DATA [31:0]
1742  * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1743  *    SRC_ADDR_HI [7:0]
1744  * 4. DST_ADDR_LO [31:0]
1745  * 5. DST_ADDR_HI [7:0]
1746  * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1747  */
1748 #              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)
1749                 /* 0 - DST_ADDR
1750 		 * 1 - GDS
1751 		 */
1752 #              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)
1753                 /* 0 - ME
1754 		 * 1 - PFP
1755 		 */
1756 #              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)
1757                 /* 0 - SRC_ADDR
1758 		 * 1 - GDS
1759 		 * 2 - DATA
1760 		 */
1761 #              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)
1762 /* COMMAND */
1763 #              define PACKET3_CP_DMA_DIS_WC        (1 << 21)
1764 #              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1765                 /* 0 - none
1766 		 * 1 - 8 in 16
1767 		 * 2 - 8 in 32
1768 		 * 3 - 8 in 64
1769 		 */
1770 #              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1771                 /* 0 - none
1772 		 * 1 - 8 in 16
1773 		 * 2 - 8 in 32
1774 		 * 3 - 8 in 64
1775 		 */
1776 #              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)
1777                 /* 0 - memory
1778 		 * 1 - register
1779 		 */
1780 #              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)
1781                 /* 0 - memory
1782 		 * 1 - register
1783 		 */
1784 #              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)
1785 #              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
1786 #              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)
1787 #define	PACKET3_PFP_SYNC_ME				0x42
1788 #define	PACKET3_SURFACE_SYNC				0x43
1789 #              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
1790 #              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
1791 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
1792 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
1793 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
1794 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
1795 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
1796 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
1797 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
1798 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
1799 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
1800 #              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
1801 #              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
1802 #              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
1803 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
1804 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
1805 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
1806 #              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1807 #              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1808 #define	PACKET3_ME_INITIALIZE				0x44
1809 #define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1810 #define	PACKET3_COND_WRITE				0x45
1811 #define	PACKET3_EVENT_WRITE				0x46
1812 #define		EVENT_TYPE(x)                           ((x) << 0)
1813 #define		EVENT_INDEX(x)                          ((x) << 8)
1814                 /* 0 - any non-TS event
1815 		 * 1 - ZPASS_DONE
1816 		 * 2 - SAMPLE_PIPELINESTAT
1817 		 * 3 - SAMPLE_STREAMOUTSTAT*
1818 		 * 4 - *S_PARTIAL_FLUSH
1819 		 * 5 - EOP events
1820 		 * 6 - EOS events
1821 		 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1822 		 */
1823 #define		INV_L2                                  (1 << 20)
1824                 /* INV TC L2 cache when EVENT_INDEX = 7 */
1825 #define	PACKET3_EVENT_WRITE_EOP				0x47
1826 #define		DATA_SEL(x)                             ((x) << 29)
1827                 /* 0 - discard
1828 		 * 1 - send low 32bit data
1829 		 * 2 - send 64bit data
1830 		 * 3 - send 64bit counter value
1831 		 */
1832 #define		INT_SEL(x)                              ((x) << 24)
1833                 /* 0 - none
1834 		 * 1 - interrupt only (DATA_SEL = 0)
1835 		 * 2 - interrupt when data write is confirmed
1836 		 */
1837 #define	PACKET3_EVENT_WRITE_EOS				0x48
1838 #define	PACKET3_PREAMBLE_CNTL				0x4A
1839 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
1840 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
1841 #define	PACKET3_ONE_REG_WRITE				0x57
1842 #define	PACKET3_LOAD_CONFIG_REG				0x5F
1843 #define	PACKET3_LOAD_CONTEXT_REG			0x60
1844 #define	PACKET3_LOAD_SH_REG				0x61
1845 #define	PACKET3_SET_CONFIG_REG				0x68
1846 #define		PACKET3_SET_CONFIG_REG_START			0x00002000
1847 #define		PACKET3_SET_CONFIG_REG_END			0x00002c00
1848 #define	PACKET3_SET_CONTEXT_REG				0x69
1849 #define		PACKET3_SET_CONTEXT_REG_START			0x000a000
1850 #define		PACKET3_SET_CONTEXT_REG_END			0x000a400
1851 #define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73
1852 #define	PACKET3_SET_RESOURCE_INDIRECT			0x74
1853 #define	PACKET3_SET_SH_REG				0x76
1854 #define		PACKET3_SET_SH_REG_START			0x00002c00
1855 #define		PACKET3_SET_SH_REG_END				0x00003000
1856 #define	PACKET3_SET_SH_REG_OFFSET			0x77
1857 #define	PACKET3_ME_WRITE				0x7A
1858 #define	PACKET3_SCRATCH_RAM_WRITE			0x7D
1859 #define	PACKET3_SCRATCH_RAM_READ			0x7E
1860 #define	PACKET3_CE_WRITE				0x7F
1861 #define	PACKET3_LOAD_CONST_RAM				0x80
1862 #define	PACKET3_WRITE_CONST_RAM				0x81
1863 #define	PACKET3_WRITE_CONST_RAM_OFFSET			0x82
1864 #define	PACKET3_DUMP_CONST_RAM				0x83
1865 #define	PACKET3_INCREMENT_CE_COUNTER			0x84
1866 #define	PACKET3_INCREMENT_DE_COUNTER			0x85
1867 #define	PACKET3_WAIT_ON_CE_COUNTER			0x86
1868 #define	PACKET3_WAIT_ON_DE_COUNTER			0x87
1869 #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
1870 #define	PACKET3_SET_CE_DE_COUNTERS			0x89
1871 #define	PACKET3_WAIT_ON_AVAIL_BUFFER			0x8A
1872 #define	PACKET3_SWITCH_BUFFER				0x8B
1873 
1874 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1875 #define DMA0_REGISTER_OFFSET                              0x0 /* not a register */
1876 #define DMA1_REGISTER_OFFSET                              0x200 /* not a register */
1877 
1878 #define DMA_RB_CNTL                                       0x3400
1879 #       define DMA_RB_ENABLE                              (1 << 0)
1880 #       define DMA_RB_SIZE(x)                             ((x) << 1) /* log2 */
1881 #       define DMA_RB_SWAP_ENABLE                         (1 << 9) /* 8IN32 */
1882 #       define DMA_RPTR_WRITEBACK_ENABLE                  (1 << 12)
1883 #       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 << 13)  /* 8IN32 */
1884 #       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) << 16) /* log2 */
1885 #define DMA_RB_BASE                                       0x3401
1886 #define DMA_RB_RPTR                                       0x3402
1887 #define DMA_RB_WPTR                                       0x3403
1888 
1889 #define DMA_RB_RPTR_ADDR_HI                               0x3407
1890 #define DMA_RB_RPTR_ADDR_LO                               0x3408
1891 
1892 #define DMA_IB_CNTL                                       0x3409
1893 #       define DMA_IB_ENABLE                              (1 << 0)
1894 #       define DMA_IB_SWAP_ENABLE                         (1 << 4)
1895 #       define CMD_VMID_FORCE                             (1 << 31)
1896 #define DMA_IB_RPTR                                       0x340a
1897 #define DMA_CNTL                                          0x340b
1898 #       define TRAP_ENABLE                                (1 << 0)
1899 #       define SEM_INCOMPLETE_INT_ENABLE                  (1 << 1)
1900 #       define SEM_WAIT_INT_ENABLE                        (1 << 2)
1901 #       define DATA_SWAP_ENABLE                           (1 << 3)
1902 #       define FENCE_SWAP_ENABLE                          (1 << 4)
1903 #       define CTXEMPTY_INT_ENABLE                        (1 << 28)
1904 #define DMA_STATUS_REG                                    0x340d
1905 #       define DMA_IDLE                                   (1 << 0)
1906 #define DMA_TILING_CONFIG  				  0x342e
1907 
1908 #define	DMA_POWER_CNTL					0x342f
1909 #       define MEM_POWER_OVERRIDE                       (1 << 8)
1910 #define	DMA_CLK_CTRL					0x3430
1911 
1912 #define	DMA_PG						0x3435
1913 #	define PG_CNTL_ENABLE				(1 << 0)
1914 #define	DMA_PGFSM_CONFIG				0x3436
1915 #define	DMA_PGFSM_WRITE					0x3437
1916 
1917 #define DMA_PACKET(cmd, b, t, s, n)	((((cmd) & 0xF) << 28) |	\
1918 					 (((b) & 0x1) << 26) |		\
1919 					 (((t) & 0x1) << 23) |		\
1920 					 (((s) & 0x1) << 22) |		\
1921 					 (((n) & 0xFFFFF) << 0))
1922 
1923 #define DMA_IB_PACKET(cmd, vmid, n)	((((cmd) & 0xF) << 28) |	\
1924 					 (((vmid) & 0xF) << 20) |	\
1925 					 (((n) & 0xFFFFF) << 0))
1926 
1927 #define DMA_PTE_PDE_PACKET(n)		((2 << 28) |			\
1928 					 (1 << 26) |			\
1929 					 (1 << 21) |			\
1930 					 (((n) & 0xFFFFF) << 0))
1931 
1932 /* async DMA Packet types */
1933 #define	DMA_PACKET_WRITE				  0x2
1934 #define	DMA_PACKET_COPY					  0x3
1935 #define	DMA_PACKET_INDIRECT_BUFFER			  0x4
1936 #define	DMA_PACKET_SEMAPHORE				  0x5
1937 #define	DMA_PACKET_FENCE				  0x6
1938 #define	DMA_PACKET_TRAP					  0x7
1939 #define	DMA_PACKET_SRBM_WRITE				  0x9
1940 #define	DMA_PACKET_CONSTANT_FILL			  0xd
1941 #define	DMA_PACKET_POLL_REG_MEM				  0xe
1942 #define	DMA_PACKET_NOP					  0xf
1943 
1944 #define VCE_STATUS					0x20004
1945 #define VCE_VCPU_CNTL					0x20014
1946 #define		VCE_CLK_EN				(1 << 0)
1947 #define VCE_VCPU_CACHE_OFFSET0				0x20024
1948 #define VCE_VCPU_CACHE_SIZE0				0x20028
1949 #define VCE_VCPU_CACHE_OFFSET1				0x2002c
1950 #define VCE_VCPU_CACHE_SIZE1				0x20030
1951 #define VCE_VCPU_CACHE_OFFSET2				0x20034
1952 #define VCE_VCPU_CACHE_SIZE2				0x20038
1953 #define VCE_SOFT_RESET					0x20120
1954 #define 	VCE_ECPU_SOFT_RESET			(1 << 0)
1955 #define 	VCE_FME_SOFT_RESET			(1 << 2)
1956 #define VCE_RB_BASE_LO2					0x2016c
1957 #define VCE_RB_BASE_HI2					0x20170
1958 #define VCE_RB_SIZE2					0x20174
1959 #define VCE_RB_RPTR2					0x20178
1960 #define VCE_RB_WPTR2					0x2017c
1961 #define VCE_RB_BASE_LO					0x20180
1962 #define VCE_RB_BASE_HI					0x20184
1963 #define VCE_RB_SIZE					0x20188
1964 #define VCE_RB_RPTR					0x2018c
1965 #define VCE_RB_WPTR					0x20190
1966 #define VCE_CLOCK_GATING_A				0x202f8
1967 #define VCE_CLOCK_GATING_B				0x202fc
1968 #define VCE_UENC_CLOCK_GATING				0x205bc
1969 #define VCE_UENC_REG_CLOCK_GATING			0x205c0
1970 #define VCE_FW_REG_STATUS				0x20e10
1971 #	define VCE_FW_REG_STATUS_BUSY			(1 << 0)
1972 #	define VCE_FW_REG_STATUS_PASS			(1 << 3)
1973 #	define VCE_FW_REG_STATUS_DONE			(1 << 11)
1974 #define VCE_LMI_FW_START_KEYSEL				0x20e18
1975 #define VCE_LMI_FW_PERIODIC_CTRL			0x20e20
1976 #define VCE_LMI_CTRL2					0x20e74
1977 #define VCE_LMI_CTRL					0x20e98
1978 #define VCE_LMI_VM_CTRL					0x20ea0
1979 #define VCE_LMI_SWAP_CNTL				0x20eb4
1980 #define VCE_LMI_SWAP_CNTL1				0x20eb8
1981 #define VCE_LMI_CACHE_CTRL				0x20ef4
1982 
1983 #define VCE_CMD_NO_OP					0x00000000
1984 #define VCE_CMD_END					0x00000001
1985 #define VCE_CMD_IB					0x00000002
1986 #define VCE_CMD_FENCE					0x00000003
1987 #define VCE_CMD_TRAP					0x00000004
1988 #define VCE_CMD_IB_AUTO					0x00000005
1989 #define VCE_CMD_SEMAPHORE				0x00000006
1990 
1991 
1992 //#dce stupp
1993 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
1994 #define SI_CRTC0_REGISTER_OFFSET                0 //(0x6df0 - 0x6df0)/4
1995 #define SI_CRTC1_REGISTER_OFFSET                0x300 //(0x79f0 - 0x6df0)/4
1996 #define SI_CRTC2_REGISTER_OFFSET                0x2600 //(0x105f0 - 0x6df0)/4
1997 #define SI_CRTC3_REGISTER_OFFSET                0x2900 //(0x111f0 - 0x6df0)/4
1998 #define SI_CRTC4_REGISTER_OFFSET                0x2c00 //(0x11df0 - 0x6df0)/4
1999 #define SI_CRTC5_REGISTER_OFFSET                0x2f00 //(0x129f0 - 0x6df0)/4
2000 
2001 #define CURSOR_WIDTH 64
2002 #define CURSOR_HEIGHT 64
2003 #define AMDGPU_MM_INDEX		        0x0000
2004 #define AMDGPU_MM_DATA		        0x0001
2005 
2006 #define VERDE_NUM_CRTC 6
2007 #define	BLACKOUT_MODE_MASK			0x00000007
2008 #define	VGA_RENDER_CONTROL			0xC0
2009 #define R_000300_VGA_RENDER_CONTROL             0xC0
2010 #define C_000300_VGA_VSTATUS_CNTL               0xFFFCFFFF
2011 #define EVERGREEN_CRTC_STATUS                   0x1BA3
2012 #define EVERGREEN_CRTC_V_BLANK                  (1 << 0)
2013 #define EVERGREEN_CRTC_STATUS_POSITION          0x1BA4
2014 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
2015 #define EVERGREEN_CRTC_V_BLANK_START_END                0x1b8d
2016 #define EVERGREEN_CRTC_CONTROL                          0x1b9c
2017 #define EVERGREEN_CRTC_MASTER_EN                 (1 << 0)
2018 #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2019 #define EVERGREEN_CRTC_BLANK_CONTROL                    0x1b9d
2020 #define EVERGREEN_CRTC_BLANK_DATA_EN             (1 << 8)
2021 #define EVERGREEN_CRTC_V_BLANK                   (1 << 0)
2022 #define EVERGREEN_CRTC_STATUS_HV_COUNT                  0x1ba8
2023 #define EVERGREEN_CRTC_UPDATE_LOCK                      0x1bb5
2024 #define EVERGREEN_MASTER_UPDATE_LOCK                    0x1bbd
2025 #define EVERGREEN_MASTER_UPDATE_MODE                    0x1bbe
2026 #define EVERGREEN_GRPH_UPDATE_LOCK               (1 << 16)
2027 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07
2028 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08
2029 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS          0x1a04
2030 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS        0x1a05
2031 #define EVERGREEN_GRPH_UPDATE                           0x1a11
2032 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0xc4
2033 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0xc9
2034 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 << 2)
2035 
2036 #define EVERGREEN_DATA_FORMAT                           0x1ac0
2037 #       define EVERGREEN_INTERLEAVE_EN                  (1 << 0)
2038 
2039 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
2040 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
2041 
2042 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL            (0 << 20)
2043 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED            (1 << 20)
2044 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)
2045 #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)
2046 
2047 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45
2048 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845
2049 
2050 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1847
2051 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1a47
2052 
2053 #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
2054 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
2055 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
2056 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
2057 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
2058 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
2059 
2060 #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
2061 #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
2062 #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
2063 #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
2064 #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
2065 #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
2066 
2067 #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
2068 #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
2069 #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
2070 #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
2071 #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
2072 #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
2073 
2074 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
2075 #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
2076 
2077 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1
2078 
2079 #define R600_D1GRPH_SWAP_CONTROL                               0x1843
2080 #define R600_D1GRPH_SWAP_ENDIAN_NONE                    (0 << 0)
2081 #define R600_D1GRPH_SWAP_ENDIAN_16BIT                   (1 << 0)
2082 #define R600_D1GRPH_SWAP_ENDIAN_32BIT                   (2 << 0)
2083 #define R600_D1GRPH_SWAP_ENDIAN_64BIT                   (3 << 0)
2084 
2085 #define AVIVO_D1VGA_CONTROL					0x00cc
2086 #       define AVIVO_DVGA_CONTROL_MODE_ENABLE            (1 << 0)
2087 #       define AVIVO_DVGA_CONTROL_TIMING_SELECT          (1 << 8)
2088 #       define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT   (1 << 9)
2089 #       define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
2090 #       define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN      (1 << 16)
2091 #       define AVIVO_DVGA_CONTROL_ROTATE                 (1 << 24)
2092 #define AVIVO_D2VGA_CONTROL					0x00ce
2093 
2094 #define R600_BUS_CNTL                                           0x1508
2095 #       define R600_BIOS_ROM_DIS                                (1 << 1)
2096 
2097 #define R600_ROM_CNTL                              0x580
2098 #       define R600_SCK_OVERWRITE                  (1 << 1)
2099 #       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
2100 #       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf << 28)
2101 
2102 #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
2103 
2104 #define FMT_BIT_DEPTH_CONTROL                0x1bf2
2105 #define FMT_TRUNCATE_EN               (1 << 0)
2106 #define FMT_TRUNCATE_DEPTH            (1 << 4)
2107 #define FMT_SPATIAL_DITHER_EN         (1 << 8)
2108 #define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)
2109 #define FMT_SPATIAL_DITHER_DEPTH      (1 << 12)
2110 #define FMT_FRAME_RANDOM_ENABLE       (1 << 13)
2111 #define FMT_RGB_RANDOM_ENABLE         (1 << 14)
2112 #define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)
2113 #define FMT_TEMPORAL_DITHER_EN        (1 << 16)
2114 #define FMT_TEMPORAL_DITHER_DEPTH     (1 << 20)
2115 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
2116 #define FMT_TEMPORAL_LEVEL            (1 << 24)
2117 #define FMT_TEMPORAL_DITHER_RESET     (1 << 25)
2118 #define FMT_25FRC_SEL(x)              ((x) << 26)
2119 #define FMT_50FRC_SEL(x)              ((x) << 28)
2120 #define FMT_75FRC_SEL(x)              ((x) << 30)
2121 
2122 #define EVERGREEN_DC_LUT_CONTROL                        0x1a80
2123 #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE              0x1a81
2124 #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN             0x1a82
2125 #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED               0x1a83
2126 #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE              0x1a84
2127 #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN             0x1a85
2128 #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED               0x1a86
2129 #define EVERGREEN_DC_LUT_30_COLOR                       0x1a7c
2130 #define EVERGREEN_DC_LUT_RW_INDEX                       0x1a79
2131 #define EVERGREEN_DC_LUT_WRITE_EN_MASK                  0x1a7e
2132 #define EVERGREEN_DC_LUT_RW_MODE                        0x1a78
2133 
2134 #define EVERGREEN_GRPH_ENABLE                           0x1a00
2135 #define EVERGREEN_GRPH_CONTROL                          0x1a01
2136 #define EVERGREEN_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
2137 #define EVERGREEN_GRPH_DEPTH_8BPP                0
2138 #define EVERGREEN_GRPH_DEPTH_16BPP               1
2139 #define EVERGREEN_GRPH_DEPTH_32BPP               2
2140 #define EVERGREEN_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
2141 #define EVERGREEN_ADDR_SURF_2_BANK               0
2142 #define EVERGREEN_ADDR_SURF_4_BANK               1
2143 #define EVERGREEN_ADDR_SURF_8_BANK               2
2144 #define EVERGREEN_ADDR_SURF_16_BANK              3
2145 #define EVERGREEN_GRPH_Z(x)                      (((x) & 0x3) << 4)
2146 #define EVERGREEN_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
2147 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_1         0
2148 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2         1
2149 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_4         2
2150 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_8         3
2151 #define EVERGREEN_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
2152 
2153 #define EVERGREEN_GRPH_FORMAT_INDEXED            0
2154 #define EVERGREEN_GRPH_FORMAT_ARGB1555           0
2155 #define EVERGREEN_GRPH_FORMAT_ARGB565            1
2156 #define EVERGREEN_GRPH_FORMAT_ARGB4444           2
2157 #define EVERGREEN_GRPH_FORMAT_AI88               3
2158 #define EVERGREEN_GRPH_FORMAT_MONO16             4
2159 #define EVERGREEN_GRPH_FORMAT_BGRA5551           5
2160 
2161 /* 32 BPP */
2162 #define EVERGREEN_GRPH_FORMAT_ARGB8888           0
2163 #define EVERGREEN_GRPH_FORMAT_ARGB2101010        1
2164 #define EVERGREEN_GRPH_FORMAT_32BPP_DIG          2
2165 #define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010     3
2166 #define EVERGREEN_GRPH_FORMAT_BGRA1010102        4
2167 #define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102     5
2168 #define EVERGREEN_GRPH_FORMAT_RGB111110          6
2169 #define EVERGREEN_GRPH_FORMAT_BGR101111          7
2170 #define EVERGREEN_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
2171 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1        0
2172 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2        1
2173 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4        2
2174 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8        3
2175 #define EVERGREEN_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
2176 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B       0
2177 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B      1
2178 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B      2
2179 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B      3
2180 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB       4
2181 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB       5
2182 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB       6
2183 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
2184 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1  0
2185 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2  1
2186 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2
2187 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3
2188 #define EVERGREEN_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
2189 #define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL      0
2190 #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED      1
2191 #define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1      2
2192 #define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1      4
2193 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1  0
2194 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2  1
2195 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2
2196 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3
2197 
2198 #define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03
2199 #define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
2200 #       define EVERGREEN_GRPH_ENDIAN_NONE               0
2201 #       define EVERGREEN_GRPH_ENDIAN_8IN16              1
2202 #       define EVERGREEN_GRPH_ENDIAN_8IN32              2
2203 #       define EVERGREEN_GRPH_ENDIAN_8IN64              3
2204 #define EVERGREEN_GRPH_RED_CROSSBAR(x)           (((x) & 0x3) << 4)
2205 #       define EVERGREEN_GRPH_RED_SEL_R                 0
2206 #       define EVERGREEN_GRPH_RED_SEL_G                 1
2207 #       define EVERGREEN_GRPH_RED_SEL_B                 2
2208 #       define EVERGREEN_GRPH_RED_SEL_A                 3
2209 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x)         (((x) & 0x3) << 6)
2210 #       define EVERGREEN_GRPH_GREEN_SEL_G               0
2211 #       define EVERGREEN_GRPH_GREEN_SEL_B               1
2212 #       define EVERGREEN_GRPH_GREEN_SEL_A               2
2213 #       define EVERGREEN_GRPH_GREEN_SEL_R               3
2214 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x)          (((x) & 0x3) << 8)
2215 #       define EVERGREEN_GRPH_BLUE_SEL_B                0
2216 #       define EVERGREEN_GRPH_BLUE_SEL_A                1
2217 #       define EVERGREEN_GRPH_BLUE_SEL_R                2
2218 #       define EVERGREEN_GRPH_BLUE_SEL_G                3
2219 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x)         (((x) & 0x3) << 10)
2220 #       define EVERGREEN_GRPH_ALPHA_SEL_A               0
2221 #       define EVERGREEN_GRPH_ALPHA_SEL_R               1
2222 #       define EVERGREEN_GRPH_ALPHA_SEL_G               2
2223 #       define EVERGREEN_GRPH_ALPHA_SEL_B               3
2224 
2225 #define EVERGREEN_D3VGA_CONTROL                         0xf8
2226 #define EVERGREEN_D4VGA_CONTROL                         0xf9
2227 #define EVERGREEN_D5VGA_CONTROL                         0xfa
2228 #define EVERGREEN_D6VGA_CONTROL                         0xfb
2229 
2230 #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK      0xffffff00
2231 
2232 #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL         0x1a02
2233 #define EVERGREEN_LUT_10BIT_BYPASS_EN            (1 << 8)
2234 
2235 #define EVERGREEN_GRPH_PITCH                            0x1a06
2236 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07
2237 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08
2238 #define EVERGREEN_GRPH_SURFACE_OFFSET_X                 0x1a09
2239 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y                 0x1a0a
2240 #define EVERGREEN_GRPH_X_START                          0x1a0b
2241 #define EVERGREEN_GRPH_Y_START                          0x1a0c
2242 #define EVERGREEN_GRPH_X_END                            0x1a0d
2243 #define EVERGREEN_GRPH_Y_END                            0x1a0e
2244 #define EVERGREEN_GRPH_UPDATE                           0x1a11
2245 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 << 2)
2246 #define EVERGREEN_GRPH_UPDATE_LOCK               (1 << 16)
2247 #define EVERGREEN_GRPH_FLIP_CONTROL                     0x1a12
2248 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
2249 
2250 #define EVERGREEN_VIEWPORT_START                        0x1b5c
2251 #define EVERGREEN_VIEWPORT_SIZE                         0x1b5d
2252 #define EVERGREEN_DESKTOP_HEIGHT                        0x1ac1
2253 
2254 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
2255 #define EVERGREEN_CUR_CONTROL                           0x1a66
2256 #       define EVERGREEN_CURSOR_EN                      (1 << 0)
2257 #       define EVERGREEN_CURSOR_MODE(x)                 (((x) & 0x3) << 8)
2258 #       define EVERGREEN_CURSOR_MONO                    0
2259 #       define EVERGREEN_CURSOR_24_1                    1
2260 #       define EVERGREEN_CURSOR_24_8_PRE_MULT           2
2261 #       define EVERGREEN_CURSOR_24_8_UNPRE_MULT         3
2262 #       define EVERGREEN_CURSOR_2X_MAGNIFY              (1 << 16)
2263 #       define EVERGREEN_CURSOR_FORCE_MC_ON             (1 << 20)
2264 #       define EVERGREEN_CURSOR_URGENT_CONTROL(x)       (((x) & 0x7) << 24)
2265 #       define EVERGREEN_CURSOR_URGENT_ALWAYS           0
2266 #       define EVERGREEN_CURSOR_URGENT_1_8              1
2267 #       define EVERGREEN_CURSOR_URGENT_1_4              2
2268 #       define EVERGREEN_CURSOR_URGENT_3_8              3
2269 #       define EVERGREEN_CURSOR_URGENT_1_2              4
2270 #define EVERGREEN_CUR_SURFACE_ADDRESS                   0x1a67
2271 #       define EVERGREEN_CUR_SURFACE_ADDRESS_MASK       0xfffff000
2272 #define EVERGREEN_CUR_SIZE                              0x1a68
2273 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH              0x1a69
2274 #define EVERGREEN_CUR_POSITION                          0x1a6a
2275 #define EVERGREEN_CUR_HOT_SPOT                          0x1a6b
2276 #define EVERGREEN_CUR_COLOR1                            0x1a6c
2277 #define EVERGREEN_CUR_COLOR2                            0x1a6d
2278 #define EVERGREEN_CUR_UPDATE                            0x1a6e
2279 #       define EVERGREEN_CURSOR_UPDATE_PENDING          (1 << 0)
2280 #       define EVERGREEN_CURSOR_UPDATE_TAKEN            (1 << 1)
2281 #       define EVERGREEN_CURSOR_UPDATE_LOCK             (1 << 16)
2282 #       define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
2283 
2284 
2285 #define NI_INPUT_CSC_CONTROL                           0x1a35
2286 #       define NI_INPUT_CSC_GRPH_MODE(x)               (((x) & 0x3) << 0)
2287 #       define NI_INPUT_CSC_BYPASS                     0
2288 #       define NI_INPUT_CSC_PROG_COEFF                 1
2289 #       define NI_INPUT_CSC_PROG_SHARED_MATRIXA        2
2290 #       define NI_INPUT_CSC_OVL_MODE(x)                (((x) & 0x3) << 4)
2291 
2292 #define NI_OUTPUT_CSC_CONTROL                          0x1a3c
2293 #       define NI_OUTPUT_CSC_GRPH_MODE(x)              (((x) & 0x7) << 0)
2294 #       define NI_OUTPUT_CSC_BYPASS                    0
2295 #       define NI_OUTPUT_CSC_TV_RGB                    1
2296 #       define NI_OUTPUT_CSC_YCBCR_601                 2
2297 #       define NI_OUTPUT_CSC_YCBCR_709                 3
2298 #       define NI_OUTPUT_CSC_PROG_COEFF                4
2299 #       define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB       5
2300 #       define NI_OUTPUT_CSC_OVL_MODE(x)               (((x) & 0x7) << 4)
2301 
2302 #define NI_DEGAMMA_CONTROL                             0x1a58
2303 #       define NI_GRPH_DEGAMMA_MODE(x)                 (((x) & 0x3) << 0)
2304 #       define NI_DEGAMMA_BYPASS                       0
2305 #       define NI_DEGAMMA_SRGB_24                      1
2306 #       define NI_DEGAMMA_XVYCC_222                    2
2307 #       define NI_OVL_DEGAMMA_MODE(x)                  (((x) & 0x3) << 4)
2308 #       define NI_ICON_DEGAMMA_MODE(x)                 (((x) & 0x3) << 8)
2309 #       define NI_CURSOR_DEGAMMA_MODE(x)               (((x) & 0x3) << 12)
2310 
2311 #define NI_GAMUT_REMAP_CONTROL                         0x1a59
2312 #       define NI_GRPH_GAMUT_REMAP_MODE(x)             (((x) & 0x3) << 0)
2313 #       define NI_GAMUT_REMAP_BYPASS                   0
2314 #       define NI_GAMUT_REMAP_PROG_COEFF               1
2315 #       define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA      2
2316 #       define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB      3
2317 #       define NI_OVL_GAMUT_REMAP_MODE(x)              (((x) & 0x3) << 4)
2318 
2319 #define NI_REGAMMA_CONTROL                             0x1aa0
2320 #       define NI_GRPH_REGAMMA_MODE(x)                 (((x) & 0x7) << 0)
2321 #       define NI_REGAMMA_BYPASS                       0
2322 #       define NI_REGAMMA_SRGB_24                      1
2323 #       define NI_REGAMMA_XVYCC_222                    2
2324 #       define NI_REGAMMA_PROG_A                       3
2325 #       define NI_REGAMMA_PROG_B                       4
2326 #       define NI_OVL_REGAMMA_MODE(x)                  (((x) & 0x7) << 4)
2327 
2328 
2329 #define NI_PRESCALE_GRPH_CONTROL                       0x1a2d
2330 #       define NI_GRPH_PRESCALE_BYPASS                 (1 << 4)
2331 
2332 #define NI_PRESCALE_OVL_CONTROL                        0x1a31
2333 #       define NI_OVL_PRESCALE_BYPASS                  (1 << 4)
2334 
2335 #define NI_INPUT_GAMMA_CONTROL                         0x1a10
2336 #       define NI_GRPH_INPUT_GAMMA_MODE(x)             (((x) & 0x3) << 0)
2337 #       define NI_INPUT_GAMMA_USE_LUT                  0
2338 #       define NI_INPUT_GAMMA_BYPASS                   1
2339 #       define NI_INPUT_GAMMA_SRGB_24                  2
2340 #       define NI_INPUT_GAMMA_XVYCC_222                3
2341 #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
2342 
2343 #define	BLACKOUT_MODE_MASK			0x00000007
2344 #define	VGA_RENDER_CONTROL			0xC0
2345 #define R_000300_VGA_RENDER_CONTROL             0xC0
2346 #define C_000300_VGA_VSTATUS_CNTL               0xFFFCFFFF
2347 #define EVERGREEN_CRTC_STATUS                   0x1BA3
2348 #define EVERGREEN_CRTC_V_BLANK                  (1 << 0)
2349 #define EVERGREEN_CRTC_STATUS_POSITION          0x1BA4
2350 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
2351 #define EVERGREEN_CRTC_V_BLANK_START_END                0x1b8d
2352 #define EVERGREEN_CRTC_CONTROL                          0x1b9c
2353 #       define EVERGREEN_CRTC_MASTER_EN                 (1 << 0)
2354 #       define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2355 #define EVERGREEN_CRTC_BLANK_CONTROL                    0x1b9d
2356 #       define EVERGREEN_CRTC_BLANK_DATA_EN             (1 << 8)
2357 #       define EVERGREEN_CRTC_V_BLANK                   (1 << 0)
2358 #define EVERGREEN_CRTC_STATUS_HV_COUNT                  0x1ba8
2359 #define EVERGREEN_CRTC_UPDATE_LOCK                      0x1bb5
2360 #define EVERGREEN_MASTER_UPDATE_LOCK                    0x1bbd
2361 #define EVERGREEN_MASTER_UPDATE_MODE                    0x1bbe
2362 #define EVERGREEN_GRPH_UPDATE_LOCK               (1 << 16)
2363 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07
2364 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08
2365 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS          0x1a04
2366 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS        0x1a05
2367 #define EVERGREEN_GRPH_UPDATE                           0x1a11
2368 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0xc4
2369 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0xc9
2370 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 << 2)
2371 
2372 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
2373 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
2374 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
2375 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
2376 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
2377 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
2378 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
2379 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
2380 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
2381 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
2382 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
2383 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
2384 
2385 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000
2386 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19
2387 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff
2388 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0
2389 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000
2390 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc
2391 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000
2392 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18
2393 
2394 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7
2395 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0
2396 
2397 #define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1
2398 #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0
2399 #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2
2400 #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1
2401 
2402 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000
2403 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11
2404 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800
2405 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb
2406 
2407 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
2408 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
2409 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
2410 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
2411 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
2412 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
2413 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
2414 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
2415 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
2416 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
2417 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
2418 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
2419 
2420 #define MC_SEQ_MISC0__MT__MASK	0xf0000000
2421 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
2422 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
2423 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
2424 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
2425 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
2426 #define MC_SEQ_MISC0__MT__HBM    0x60000000
2427 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
2428 
2429 #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
2430 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2431 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
2432 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
2433 #define PACKET3_SEM_WAIT_ON_SIGNAL    (0x1 << 12)
2434 #define PACKET3_SEM_SEL_SIGNAL	    (0x6 << 29)
2435 #define PACKET3_SEM_SEL_WAIT	    (0x7 << 29)
2436 
2437 #define CONFIG_CNTL	0x1509
2438 #define CC_DRM_ID_STRAPS	0X1559
2439 #define AMDGPU_PCIE_INDEX	0xc
2440 #define AMDGPU_PCIE_DATA	0xd
2441 
2442 #define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0x3411
2443 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0x3412
2444 #define DMA_MODE                                          0x342f
2445 #define DMA_RB_RPTR_ADDR_HI                               0x3407
2446 #define DMA_RB_RPTR_ADDR_LO                               0x3408
2447 #define DMA_BUSY_MASK 0x20
2448 #define DMA1_BUSY_MASK 0X40
2449 #define SDMA_MAX_INSTANCE 2
2450 
2451 #define PCIE_BUS_CLK    10000
2452 #define TCLK            (PCIE_BUS_CLK / 10)
2453 #define	PCIE_PORT_INDEX					0xe
2454 #define	PCIE_PORT_DATA					0xf
2455 #define EVERGREEN_PIF_PHY0_INDEX                        0x8
2456 #define EVERGREEN_PIF_PHY0_DATA                         0xc
2457 #define EVERGREEN_PIF_PHY1_INDEX                        0x10
2458 #define EVERGREEN_PIF_PHY1_DATA				0x14
2459 
2460 #define	MC_VM_FB_OFFSET					0x81a
2461 
2462 /* Discrete VCE clocks */
2463 #define CG_VCEPLL_FUNC_CNTL                             0xc0030600
2464 #define    VCEPLL_RESET_MASK                            0x00000001
2465 #define    VCEPLL_SLEEP_MASK                            0x00000002
2466 #define    VCEPLL_BYPASS_EN_MASK                        0x00000004
2467 #define    VCEPLL_CTLREQ_MASK                           0x00000008
2468 #define    VCEPLL_VCO_MODE_MASK                         0x00000600
2469 #define    VCEPLL_REF_DIV_MASK                          0x003F0000
2470 #define    VCEPLL_CTLACK_MASK                           0x40000000
2471 #define    VCEPLL_CTLACK2_MASK                          0x80000000
2472 
2473 #define CG_VCEPLL_FUNC_CNTL_2                           0xc0030601
2474 #define    VCEPLL_PDIV_A(x)                             ((x) << 0)
2475 #define    VCEPLL_PDIV_A_MASK                           0x0000007F
2476 #define    VCEPLL_PDIV_B(x)                             ((x) << 8)
2477 #define    VCEPLL_PDIV_B_MASK                           0x00007F00
2478 #define    EVCLK_SRC_SEL(x)                             ((x) << 20)
2479 #define    EVCLK_SRC_SEL_MASK                           0x01F00000
2480 #define    ECCLK_SRC_SEL(x)                             ((x) << 25)
2481 #define    ECCLK_SRC_SEL_MASK                           0x3E000000
2482 
2483 #define CG_VCEPLL_FUNC_CNTL_3                           0xc0030602
2484 #define    VCEPLL_FB_DIV(x)                             ((x) << 0)
2485 #define    VCEPLL_FB_DIV_MASK                           0x01FFFFFF
2486 
2487 #define CG_VCEPLL_FUNC_CNTL_4                           0xc0030603
2488 
2489 #define CG_VCEPLL_FUNC_CNTL_5                           0xc0030604
2490 #define CG_VCEPLL_SPREAD_SPECTRUM                       0xc0030606
2491 #define    VCEPLL_SSEN_MASK                             0x00000001
2492 
2493 
2494 #endif
2495