1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6  */
7 
8 #include <asm/unaligned.h>
9 #include <linux/bitfield.h>
10 #include <media/v4l2-mem2mem.h>
11 #include "hantro.h"
12 #include "hantro_hw.h"
13 #include "hantro_g1_regs.h"
14 
15 #define G1_SWREG(nr)			((nr) * 4)
16 
17 #define G1_REG_RLC_VLC_BASE		G1_SWREG(12)
18 #define G1_REG_DEC_OUT_BASE		G1_SWREG(13)
19 #define G1_REG_REFER0_BASE		G1_SWREG(14)
20 #define G1_REG_REFER1_BASE		G1_SWREG(15)
21 #define G1_REG_REFER2_BASE		G1_SWREG(16)
22 #define G1_REG_REFER3_BASE		G1_SWREG(17)
23 #define G1_REG_QTABLE_BASE		G1_SWREG(40)
24 
25 #define G1_REG_DEC_AXI_RD_ID(v)		(((v) << 24) & GENMASK(31, 24))
26 #define G1_REG_DEC_TIMEOUT_E(v)		((v) ? BIT(23) : 0)
27 #define G1_REG_DEC_STRSWAP32_E(v)	((v) ? BIT(22) : 0)
28 #define G1_REG_DEC_STRENDIAN_E(v)	((v) ? BIT(21) : 0)
29 #define G1_REG_DEC_INSWAP32_E(v)	((v) ? BIT(20) : 0)
30 #define G1_REG_DEC_OUTSWAP32_E(v)	((v) ? BIT(19) : 0)
31 #define G1_REG_DEC_DATA_DISC_E(v)	((v) ? BIT(18) : 0)
32 #define G1_REG_DEC_LATENCY(v)		(((v) << 11) & GENMASK(16, 11))
33 #define G1_REG_DEC_CLK_GATE_E(v)	((v) ? BIT(10) : 0)
34 #define G1_REG_DEC_IN_ENDIAN(v)		((v) ? BIT(9) : 0)
35 #define G1_REG_DEC_OUT_ENDIAN(v)	((v) ? BIT(8) : 0)
36 #define G1_REG_DEC_ADV_PRE_DIS(v)	((v) ? BIT(6) : 0)
37 #define G1_REG_DEC_SCMD_DIS(v)		((v) ? BIT(5) : 0)
38 #define G1_REG_DEC_MAX_BURST(v)		(((v) << 0) & GENMASK(4, 0))
39 
40 #define G1_REG_DEC_MODE(v)		(((v) << 28) & GENMASK(31, 28))
41 #define G1_REG_RLC_MODE_E(v)		((v) ? BIT(27) : 0)
42 #define G1_REG_PIC_INTERLACE_E(v)	((v) ? BIT(23) : 0)
43 #define G1_REG_PIC_FIELDMODE_E(v)	((v) ? BIT(22) : 0)
44 #define G1_REG_PIC_B_E(v)		((v) ? BIT(21) : 0)
45 #define G1_REG_PIC_INTER_E(v)		((v) ? BIT(20) : 0)
46 #define G1_REG_PIC_TOPFIELD_E(v)	((v) ? BIT(19) : 0)
47 #define G1_REG_FWD_INTERLACE_E(v)	((v) ? BIT(18) : 0)
48 #define G1_REG_FILTERING_DIS(v)		((v) ? BIT(14) : 0)
49 #define G1_REG_WRITE_MVS_E(v)		((v) ? BIT(12) : 0)
50 #define G1_REG_DEC_AXI_WR_ID(v)		(((v) << 0) & GENMASK(7, 0))
51 
52 #define G1_REG_PIC_MB_WIDTH(v)		(((v) << 23) & GENMASK(31, 23))
53 #define G1_REG_PIC_MB_HEIGHT_P(v)	(((v) << 11) & GENMASK(18, 11))
54 #define G1_REG_ALT_SCAN_E(v)		((v) ? BIT(6) : 0)
55 #define G1_REG_TOPFIELDFIRST_E(v)	((v) ? BIT(5) : 0)
56 
57 #define G1_REG_STRM_START_BIT(v)	(((v) << 26) & GENMASK(31, 26))
58 #define G1_REG_QSCALE_TYPE(v)		((v) ? BIT(24) : 0)
59 #define G1_REG_CON_MV_E(v)		((v) ? BIT(4) : 0)
60 #define G1_REG_INTRA_DC_PREC(v)		(((v) << 2) & GENMASK(3, 2))
61 #define G1_REG_INTRA_VLC_TAB(v)		((v) ? BIT(1) : 0)
62 #define G1_REG_FRAME_PRED_DCT(v)	((v) ? BIT(0) : 0)
63 
64 #define G1_REG_INIT_QP(v)		(((v) << 25) & GENMASK(30, 25))
65 #define G1_REG_STREAM_LEN(v)		(((v) << 0) & GENMASK(23, 0))
66 
67 #define G1_REG_ALT_SCAN_FLAG_E(v)	((v) ? BIT(19) : 0)
68 #define G1_REG_FCODE_FWD_HOR(v)		(((v) << 15) & GENMASK(18, 15))
69 #define G1_REG_FCODE_FWD_VER(v)		(((v) << 11) & GENMASK(14, 11))
70 #define G1_REG_FCODE_BWD_HOR(v)		(((v) << 7) & GENMASK(10, 7))
71 #define G1_REG_FCODE_BWD_VER(v)		(((v) << 3) & GENMASK(6, 3))
72 #define G1_REG_MV_ACCURACY_FWD(v)	((v) ? BIT(2) : 0)
73 #define G1_REG_MV_ACCURACY_BWD(v)	((v) ? BIT(1) : 0)
74 
75 #define G1_REG_STARTMB_X(v)		(((v) << 23) & GENMASK(31, 23))
76 #define G1_REG_STARTMB_Y(v)		(((v) << 15) & GENMASK(22, 15))
77 
78 #define G1_REG_APF_THRESHOLD(v)		(((v) << 0) & GENMASK(13, 0))
79 
80 static void
hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev * vpu,struct hantro_ctx * ctx)81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,
82 				     struct hantro_ctx *ctx)
83 {
84 	struct v4l2_ctrl_mpeg2_quantisation *q;
85 
86 	q = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_MPEG2_QUANTISATION);
87 	hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, q);
88 	vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE);
89 }
90 
91 static void
hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev * vpu,struct hantro_ctx * ctx,struct vb2_buffer * src_buf,struct vb2_buffer * dst_buf,const struct v4l2_ctrl_mpeg2_sequence * seq,const struct v4l2_ctrl_mpeg2_picture * pic)92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx,
93 				struct vb2_buffer *src_buf,
94 				struct vb2_buffer *dst_buf,
95 				const struct v4l2_ctrl_mpeg2_sequence *seq,
96 				const struct v4l2_ctrl_mpeg2_picture *pic)
97 {
98 	dma_addr_t forward_addr = 0, backward_addr = 0;
99 	dma_addr_t current_addr, addr;
100 
101 	switch (pic->picture_coding_type) {
102 	case V4L2_MPEG2_PIC_CODING_TYPE_B:
103 		backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts);
104 		fallthrough;
105 	case V4L2_MPEG2_PIC_CODING_TYPE_P:
106 		forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts);
107 	}
108 
109 	/* Source bitstream buffer */
110 	addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
111 	vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
112 
113 	/* Destination frame buffer */
114 	addr = hantro_get_dec_buf_addr(ctx, dst_buf);
115 	current_addr = addr;
116 
117 	if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD)
118 		addr += ALIGN(ctx->dst_fmt.width, 16);
119 	vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
120 
121 	if (!forward_addr)
122 		forward_addr = current_addr;
123 	if (!backward_addr)
124 		backward_addr = current_addr;
125 
126 	/* Set forward ref frame (top/bottom field) */
127 	if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME ||
128 	    pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B ||
129 	    (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD &&
130 	     pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST) ||
131 	    (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD &&
132 	     !(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST))) {
133 		vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
134 		vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
135 	} else if (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) {
136 		vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
137 		vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);
138 	} else if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) {
139 		vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);
140 		vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
141 	}
142 
143 	/* Set backward ref frame (top/bottom field) */
144 	vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);
145 	vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
146 }
147 
hantro_g1_mpeg2_dec_run(struct hantro_ctx * ctx)148 int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
149 {
150 	struct hantro_dev *vpu = ctx->dev;
151 	struct vb2_v4l2_buffer *src_buf, *dst_buf;
152 	const struct v4l2_ctrl_mpeg2_sequence *seq;
153 	const struct v4l2_ctrl_mpeg2_picture *pic;
154 	u32 reg;
155 
156 	src_buf = hantro_get_src_buf(ctx);
157 	dst_buf = hantro_get_dst_buf(ctx);
158 
159 	/* Apply request controls if any */
160 	hantro_start_prepare_run(ctx);
161 
162 	seq = hantro_get_ctrl(ctx,
163 			      V4L2_CID_STATELESS_MPEG2_SEQUENCE);
164 	pic = hantro_get_ctrl(ctx,
165 			      V4L2_CID_STATELESS_MPEG2_PICTURE);
166 
167 	reg = G1_REG_DEC_AXI_RD_ID(0) |
168 	      G1_REG_DEC_TIMEOUT_E(1) |
169 	      G1_REG_DEC_STRSWAP32_E(1) |
170 	      G1_REG_DEC_STRENDIAN_E(1) |
171 	      G1_REG_DEC_INSWAP32_E(1) |
172 	      G1_REG_DEC_OUTSWAP32_E(1) |
173 	      G1_REG_DEC_DATA_DISC_E(0) |
174 	      G1_REG_DEC_LATENCY(0) |
175 	      G1_REG_DEC_CLK_GATE_E(1) |
176 	      G1_REG_DEC_IN_ENDIAN(1) |
177 	      G1_REG_DEC_OUT_ENDIAN(1) |
178 	      G1_REG_DEC_ADV_PRE_DIS(0) |
179 	      G1_REG_DEC_SCMD_DIS(0) |
180 	      G1_REG_DEC_MAX_BURST(16);
181 	vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
182 
183 	reg = G1_REG_DEC_MODE(5) |
184 	      G1_REG_RLC_MODE_E(0) |
185 	      G1_REG_PIC_INTERLACE_E(!(seq->flags & V4L2_MPEG2_SEQ_FLAG_PROGRESSIVE)) |
186 	      G1_REG_PIC_FIELDMODE_E(pic->picture_structure != V4L2_MPEG2_PIC_FRAME) |
187 	      G1_REG_PIC_B_E(pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B) |
188 	      G1_REG_PIC_INTER_E(pic->picture_coding_type != V4L2_MPEG2_PIC_CODING_TYPE_I) |
189 	      G1_REG_PIC_TOPFIELD_E(pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD) |
190 	      G1_REG_FWD_INTERLACE_E(0) |
191 	      G1_REG_FILTERING_DIS(1) |
192 	      G1_REG_WRITE_MVS_E(0) |
193 	      G1_REG_DEC_AXI_WR_ID(0);
194 	vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
195 
196 	reg = G1_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) |
197 	      G1_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) |
198 	      G1_REG_ALT_SCAN_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) |
199 	      G1_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST);
200 	vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
201 
202 	reg = G1_REG_STRM_START_BIT(0) |
203 	      G1_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) |
204 	      G1_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) |
205 	      G1_REG_INTRA_DC_PREC(pic->intra_dc_precision) |
206 	      G1_REG_INTRA_VLC_TAB(pic->flags & V4L2_MPEG2_PIC_FLAG_INTRA_VLC) |
207 	      G1_REG_FRAME_PRED_DCT(pic->flags & V4L2_MPEG2_PIC_FLAG_FRAME_PRED_DCT);
208 	vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
209 
210 	reg = G1_REG_INIT_QP(1) |
211 	      G1_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
212 	vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
213 
214 	reg = G1_REG_ALT_SCAN_FLAG_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) |
215 	      G1_REG_FCODE_FWD_HOR(pic->f_code[0][0]) |
216 	      G1_REG_FCODE_FWD_VER(pic->f_code[0][1]) |
217 	      G1_REG_FCODE_BWD_HOR(pic->f_code[1][0]) |
218 	      G1_REG_FCODE_BWD_VER(pic->f_code[1][1]) |
219 	      G1_REG_MV_ACCURACY_FWD(1) |
220 	      G1_REG_MV_ACCURACY_BWD(1);
221 	vdpu_write_relaxed(vpu, reg, G1_SWREG(18));
222 
223 	reg = G1_REG_STARTMB_X(0) |
224 	      G1_REG_STARTMB_Y(0);
225 	vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
226 
227 	reg = G1_REG_APF_THRESHOLD(8);
228 	vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
229 
230 	hantro_g1_mpeg2_dec_set_quantisation(vpu, ctx);
231 	hantro_g1_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
232 					&dst_buf->vb2_buf,
233 					seq, pic);
234 
235 	hantro_end_prepare_run(ctx);
236 
237 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
238 
239 	return 0;
240 }
241