xref: /openbmc/linux/drivers/media/usb/dvb-usb/af9005.h (revision 577a7ad3)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header-file of the Linux driver for the Afatech 9005
3  * USB1.1 DVB-T receiver.
4  *
5  * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
6  *
7  * Thanks to Afatech who kindly provided information.
8  *
9  * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
10  */
11 #ifndef _DVB_USB_AF9005_H_
12 #define _DVB_USB_AF9005_H_
13 
14 #define DVB_USB_LOG_PREFIX "af9005"
15 #include "dvb-usb.h"
16 
17 extern int dvb_usb_af9005_debug;
18 #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
19 #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
20 #define deb_rc(args...)   dprintk(dvb_usb_af9005_debug,0x04,args)
21 #define deb_reg(args...)  dprintk(dvb_usb_af9005_debug,0x08,args)
22 #define deb_i2c(args...)  dprintk(dvb_usb_af9005_debug,0x10,args)
23 #define deb_fw(args...)   dprintk(dvb_usb_af9005_debug,0x20,args)
24 
25 extern bool dvb_usb_af9005_led;
26 
27 /* firmware */
28 #define FW_BULKOUT_SIZE 250
29 enum {
30 	FW_CONFIG,
31 	FW_CONFIRM,
32 	FW_BOOT
33 };
34 
35 /* af9005 commands */
36 #define AF9005_OFDM_REG  0
37 #define AF9005_TUNER_REG 1
38 
39 #define AF9005_REGISTER_RW     0x20
40 #define AF9005_REGISTER_RW_ACK 0x21
41 
42 #define AF9005_CMD_OFDM_REG 0x00
43 #define AF9005_CMD_TUNER    0x80
44 #define AF9005_CMD_BURST    0x02
45 #define AF9005_CMD_AUTOINC  0x04
46 #define AF9005_CMD_READ     0x00
47 #define AF9005_CMD_WRITE    0x01
48 
49 /* af9005 registers */
50 #define APO_REG_RESET					0xAEFF
51 
52 #define APO_REG_I2C_RW_CAN_TUNER            0xF000
53 #define APO_REG_I2C_RW_SILICON_TUNER        0xF001
54 #define APO_REG_GPIO_RW_SILICON_TUNER       0xFFFE	/*  also for OFSM */
55 #define APO_REG_TRIGGER_OFSM                0xFFFF	/*  also for OFSM */
56 
57 /***********************************************************************
58  *  Apollo Registers from VLSI					       *
59  ***********************************************************************/
60 #define xd_p_reg_aagc_inverted_agc	0xA000
61 #define	reg_aagc_inverted_agc_pos 0
62 #define	reg_aagc_inverted_agc_len 1
63 #define	reg_aagc_inverted_agc_lsb 0
64 #define xd_p_reg_aagc_sign_only	0xA000
65 #define	reg_aagc_sign_only_pos 1
66 #define	reg_aagc_sign_only_len 1
67 #define	reg_aagc_sign_only_lsb 0
68 #define xd_p_reg_aagc_slow_adc_en	0xA000
69 #define	reg_aagc_slow_adc_en_pos 2
70 #define	reg_aagc_slow_adc_en_len 1
71 #define	reg_aagc_slow_adc_en_lsb 0
72 #define xd_p_reg_aagc_slow_adc_scale	0xA000
73 #define	reg_aagc_slow_adc_scale_pos 3
74 #define	reg_aagc_slow_adc_scale_len 5
75 #define	reg_aagc_slow_adc_scale_lsb 0
76 #define xd_p_reg_aagc_check_slow_adc_lock	0xA001
77 #define	reg_aagc_check_slow_adc_lock_pos 0
78 #define	reg_aagc_check_slow_adc_lock_len 1
79 #define	reg_aagc_check_slow_adc_lock_lsb 0
80 #define xd_p_reg_aagc_init_control	0xA001
81 #define	reg_aagc_init_control_pos 1
82 #define	reg_aagc_init_control_len 1
83 #define	reg_aagc_init_control_lsb 0
84 #define xd_p_reg_aagc_total_gain_sel	0xA001
85 #define	reg_aagc_total_gain_sel_pos 2
86 #define	reg_aagc_total_gain_sel_len 2
87 #define	reg_aagc_total_gain_sel_lsb 0
88 #define xd_p_reg_aagc_out_inv	0xA001
89 #define	reg_aagc_out_inv_pos 5
90 #define	reg_aagc_out_inv_len 1
91 #define	reg_aagc_out_inv_lsb 0
92 #define xd_p_reg_aagc_int_en	0xA001
93 #define	reg_aagc_int_en_pos 6
94 #define	reg_aagc_int_en_len 1
95 #define	reg_aagc_int_en_lsb 0
96 #define xd_p_reg_aagc_lock_change_flag	0xA001
97 #define	reg_aagc_lock_change_flag_pos 7
98 #define	reg_aagc_lock_change_flag_len 1
99 #define	reg_aagc_lock_change_flag_lsb 0
100 #define xd_p_reg_aagc_rf_loop_bw_scale_acquire	0xA002
101 #define	reg_aagc_rf_loop_bw_scale_acquire_pos 0
102 #define	reg_aagc_rf_loop_bw_scale_acquire_len 5
103 #define	reg_aagc_rf_loop_bw_scale_acquire_lsb 0
104 #define xd_p_reg_aagc_rf_loop_bw_scale_track	0xA003
105 #define	reg_aagc_rf_loop_bw_scale_track_pos 0
106 #define	reg_aagc_rf_loop_bw_scale_track_len 5
107 #define	reg_aagc_rf_loop_bw_scale_track_lsb 0
108 #define xd_p_reg_aagc_if_loop_bw_scale_acquire	0xA004
109 #define	reg_aagc_if_loop_bw_scale_acquire_pos 0
110 #define	reg_aagc_if_loop_bw_scale_acquire_len 5
111 #define	reg_aagc_if_loop_bw_scale_acquire_lsb 0
112 #define xd_p_reg_aagc_if_loop_bw_scale_track	0xA005
113 #define	reg_aagc_if_loop_bw_scale_track_pos 0
114 #define	reg_aagc_if_loop_bw_scale_track_len 5
115 #define	reg_aagc_if_loop_bw_scale_track_lsb 0
116 #define xd_p_reg_aagc_max_rf_agc_7_0	0xA006
117 #define	reg_aagc_max_rf_agc_7_0_pos 0
118 #define	reg_aagc_max_rf_agc_7_0_len 8
119 #define	reg_aagc_max_rf_agc_7_0_lsb 0
120 #define xd_p_reg_aagc_max_rf_agc_9_8	0xA007
121 #define	reg_aagc_max_rf_agc_9_8_pos 0
122 #define	reg_aagc_max_rf_agc_9_8_len 2
123 #define	reg_aagc_max_rf_agc_9_8_lsb 8
124 #define xd_p_reg_aagc_min_rf_agc_7_0	0xA008
125 #define	reg_aagc_min_rf_agc_7_0_pos 0
126 #define	reg_aagc_min_rf_agc_7_0_len 8
127 #define	reg_aagc_min_rf_agc_7_0_lsb 0
128 #define xd_p_reg_aagc_min_rf_agc_9_8	0xA009
129 #define	reg_aagc_min_rf_agc_9_8_pos 0
130 #define	reg_aagc_min_rf_agc_9_8_len 2
131 #define	reg_aagc_min_rf_agc_9_8_lsb 8
132 #define xd_p_reg_aagc_max_if_agc_7_0	0xA00A
133 #define	reg_aagc_max_if_agc_7_0_pos 0
134 #define	reg_aagc_max_if_agc_7_0_len 8
135 #define	reg_aagc_max_if_agc_7_0_lsb 0
136 #define xd_p_reg_aagc_max_if_agc_9_8	0xA00B
137 #define	reg_aagc_max_if_agc_9_8_pos 0
138 #define	reg_aagc_max_if_agc_9_8_len 2
139 #define	reg_aagc_max_if_agc_9_8_lsb 8
140 #define xd_p_reg_aagc_min_if_agc_7_0	0xA00C
141 #define	reg_aagc_min_if_agc_7_0_pos 0
142 #define	reg_aagc_min_if_agc_7_0_len 8
143 #define	reg_aagc_min_if_agc_7_0_lsb 0
144 #define xd_p_reg_aagc_min_if_agc_9_8	0xA00D
145 #define	reg_aagc_min_if_agc_9_8_pos 0
146 #define	reg_aagc_min_if_agc_9_8_len 2
147 #define	reg_aagc_min_if_agc_9_8_lsb 8
148 #define xd_p_reg_aagc_lock_sample_scale	0xA00E
149 #define	reg_aagc_lock_sample_scale_pos 0
150 #define	reg_aagc_lock_sample_scale_len 5
151 #define	reg_aagc_lock_sample_scale_lsb 0
152 #define xd_p_reg_aagc_rf_agc_lock_scale_acquire	0xA00F
153 #define	reg_aagc_rf_agc_lock_scale_acquire_pos 0
154 #define	reg_aagc_rf_agc_lock_scale_acquire_len 3
155 #define	reg_aagc_rf_agc_lock_scale_acquire_lsb 0
156 #define xd_p_reg_aagc_rf_agc_lock_scale_track	0xA00F
157 #define	reg_aagc_rf_agc_lock_scale_track_pos 3
158 #define	reg_aagc_rf_agc_lock_scale_track_len 3
159 #define	reg_aagc_rf_agc_lock_scale_track_lsb 0
160 #define xd_p_reg_aagc_if_agc_lock_scale_acquire	0xA010
161 #define	reg_aagc_if_agc_lock_scale_acquire_pos 0
162 #define	reg_aagc_if_agc_lock_scale_acquire_len 3
163 #define	reg_aagc_if_agc_lock_scale_acquire_lsb 0
164 #define xd_p_reg_aagc_if_agc_lock_scale_track	0xA010
165 #define	reg_aagc_if_agc_lock_scale_track_pos 3
166 #define	reg_aagc_if_agc_lock_scale_track_len 3
167 #define	reg_aagc_if_agc_lock_scale_track_lsb 0
168 #define xd_p_reg_aagc_rf_top_numerator_7_0	0xA011
169 #define	reg_aagc_rf_top_numerator_7_0_pos 0
170 #define	reg_aagc_rf_top_numerator_7_0_len 8
171 #define	reg_aagc_rf_top_numerator_7_0_lsb 0
172 #define xd_p_reg_aagc_rf_top_numerator_9_8	0xA012
173 #define	reg_aagc_rf_top_numerator_9_8_pos 0
174 #define	reg_aagc_rf_top_numerator_9_8_len 2
175 #define	reg_aagc_rf_top_numerator_9_8_lsb 8
176 #define xd_p_reg_aagc_if_top_numerator_7_0	0xA013
177 #define	reg_aagc_if_top_numerator_7_0_pos 0
178 #define	reg_aagc_if_top_numerator_7_0_len 8
179 #define	reg_aagc_if_top_numerator_7_0_lsb 0
180 #define xd_p_reg_aagc_if_top_numerator_9_8	0xA014
181 #define	reg_aagc_if_top_numerator_9_8_pos 0
182 #define	reg_aagc_if_top_numerator_9_8_len 2
183 #define	reg_aagc_if_top_numerator_9_8_lsb 8
184 #define xd_p_reg_aagc_adc_out_desired_7_0	0xA015
185 #define	reg_aagc_adc_out_desired_7_0_pos 0
186 #define	reg_aagc_adc_out_desired_7_0_len 8
187 #define	reg_aagc_adc_out_desired_7_0_lsb 0
188 #define xd_p_reg_aagc_adc_out_desired_8	0xA016
189 #define	reg_aagc_adc_out_desired_8_pos 0
190 #define	reg_aagc_adc_out_desired_8_len 1
191 #define	reg_aagc_adc_out_desired_8_lsb 0
192 #define xd_p_reg_aagc_fixed_gain	0xA016
193 #define	reg_aagc_fixed_gain_pos 3
194 #define	reg_aagc_fixed_gain_len 1
195 #define	reg_aagc_fixed_gain_lsb 0
196 #define xd_p_reg_aagc_lock_count_th	0xA016
197 #define	reg_aagc_lock_count_th_pos 4
198 #define	reg_aagc_lock_count_th_len 4
199 #define	reg_aagc_lock_count_th_lsb 0
200 #define xd_p_reg_aagc_fixed_rf_agc_control_7_0	0xA017
201 #define	reg_aagc_fixed_rf_agc_control_7_0_pos 0
202 #define	reg_aagc_fixed_rf_agc_control_7_0_len 8
203 #define	reg_aagc_fixed_rf_agc_control_7_0_lsb 0
204 #define xd_p_reg_aagc_fixed_rf_agc_control_15_8	0xA018
205 #define	reg_aagc_fixed_rf_agc_control_15_8_pos 0
206 #define	reg_aagc_fixed_rf_agc_control_15_8_len 8
207 #define	reg_aagc_fixed_rf_agc_control_15_8_lsb 8
208 #define xd_p_reg_aagc_fixed_rf_agc_control_23_16	0xA019
209 #define	reg_aagc_fixed_rf_agc_control_23_16_pos 0
210 #define	reg_aagc_fixed_rf_agc_control_23_16_len 8
211 #define	reg_aagc_fixed_rf_agc_control_23_16_lsb 16
212 #define xd_p_reg_aagc_fixed_rf_agc_control_30_24	0xA01A
213 #define	reg_aagc_fixed_rf_agc_control_30_24_pos 0
214 #define	reg_aagc_fixed_rf_agc_control_30_24_len 7
215 #define	reg_aagc_fixed_rf_agc_control_30_24_lsb 24
216 #define xd_p_reg_aagc_fixed_if_agc_control_7_0	0xA01B
217 #define	reg_aagc_fixed_if_agc_control_7_0_pos 0
218 #define	reg_aagc_fixed_if_agc_control_7_0_len 8
219 #define	reg_aagc_fixed_if_agc_control_7_0_lsb 0
220 #define xd_p_reg_aagc_fixed_if_agc_control_15_8	0xA01C
221 #define	reg_aagc_fixed_if_agc_control_15_8_pos 0
222 #define	reg_aagc_fixed_if_agc_control_15_8_len 8
223 #define	reg_aagc_fixed_if_agc_control_15_8_lsb 8
224 #define xd_p_reg_aagc_fixed_if_agc_control_23_16	0xA01D
225 #define	reg_aagc_fixed_if_agc_control_23_16_pos 0
226 #define	reg_aagc_fixed_if_agc_control_23_16_len 8
227 #define	reg_aagc_fixed_if_agc_control_23_16_lsb 16
228 #define xd_p_reg_aagc_fixed_if_agc_control_30_24	0xA01E
229 #define	reg_aagc_fixed_if_agc_control_30_24_pos 0
230 #define	reg_aagc_fixed_if_agc_control_30_24_len 7
231 #define	reg_aagc_fixed_if_agc_control_30_24_lsb 24
232 #define xd_p_reg_aagc_rf_agc_unlock_numerator	0xA01F
233 #define	reg_aagc_rf_agc_unlock_numerator_pos 0
234 #define	reg_aagc_rf_agc_unlock_numerator_len 6
235 #define	reg_aagc_rf_agc_unlock_numerator_lsb 0
236 #define xd_p_reg_aagc_if_agc_unlock_numerator	0xA020
237 #define	reg_aagc_if_agc_unlock_numerator_pos 0
238 #define	reg_aagc_if_agc_unlock_numerator_len 6
239 #define	reg_aagc_if_agc_unlock_numerator_lsb 0
240 #define xd_p_reg_unplug_th	0xA021
241 #define	reg_unplug_th_pos 0
242 #define	reg_unplug_th_len 8
243 #define	reg_aagc_rf_x0_lsb 0
244 #define xd_p_reg_weak_signal_rfagc_thr 0xA022
245 #define	reg_weak_signal_rfagc_thr_pos 0
246 #define	reg_weak_signal_rfagc_thr_len 8
247 #define	reg_weak_signal_rfagc_thr_lsb 0
248 #define xd_p_reg_unplug_rf_gain_th 0xA023
249 #define	reg_unplug_rf_gain_th_pos 0
250 #define	reg_unplug_rf_gain_th_len 8
251 #define	reg_unplug_rf_gain_th_lsb 0
252 #define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
253 #define	reg_unplug_dtop_rf_gain_th_pos 0
254 #define	reg_unplug_dtop_rf_gain_th_len 8
255 #define	reg_unplug_dtop_rf_gain_th_lsb 0
256 #define xd_p_reg_unplug_dtop_if_gain_th 0xA025
257 #define	reg_unplug_dtop_if_gain_th_pos 0
258 #define	reg_unplug_dtop_if_gain_th_len 8
259 #define	reg_unplug_dtop_if_gain_th_lsb 0
260 #define xd_p_reg_top_recover_at_unplug_en 0xA026
261 #define	reg_top_recover_at_unplug_en_pos 0
262 #define	reg_top_recover_at_unplug_en_len 1
263 #define	reg_top_recover_at_unplug_en_lsb 0
264 #define xd_p_reg_aagc_rf_x6	0xA027
265 #define	reg_aagc_rf_x6_pos 0
266 #define	reg_aagc_rf_x6_len 8
267 #define	reg_aagc_rf_x6_lsb 0
268 #define xd_p_reg_aagc_rf_x7	0xA028
269 #define	reg_aagc_rf_x7_pos 0
270 #define	reg_aagc_rf_x7_len 8
271 #define	reg_aagc_rf_x7_lsb 0
272 #define xd_p_reg_aagc_rf_x8	0xA029
273 #define	reg_aagc_rf_x8_pos 0
274 #define	reg_aagc_rf_x8_len 8
275 #define	reg_aagc_rf_x8_lsb 0
276 #define xd_p_reg_aagc_rf_x9	0xA02A
277 #define	reg_aagc_rf_x9_pos 0
278 #define	reg_aagc_rf_x9_len 8
279 #define	reg_aagc_rf_x9_lsb 0
280 #define xd_p_reg_aagc_rf_x10	0xA02B
281 #define	reg_aagc_rf_x10_pos 0
282 #define	reg_aagc_rf_x10_len 8
283 #define	reg_aagc_rf_x10_lsb 0
284 #define xd_p_reg_aagc_rf_x11	0xA02C
285 #define	reg_aagc_rf_x11_pos 0
286 #define	reg_aagc_rf_x11_len 8
287 #define	reg_aagc_rf_x11_lsb 0
288 #define xd_p_reg_aagc_rf_x12	0xA02D
289 #define	reg_aagc_rf_x12_pos 0
290 #define	reg_aagc_rf_x12_len 8
291 #define	reg_aagc_rf_x12_lsb 0
292 #define xd_p_reg_aagc_rf_x13	0xA02E
293 #define	reg_aagc_rf_x13_pos 0
294 #define	reg_aagc_rf_x13_len 8
295 #define	reg_aagc_rf_x13_lsb 0
296 #define xd_p_reg_aagc_if_x0	0xA02F
297 #define	reg_aagc_if_x0_pos 0
298 #define	reg_aagc_if_x0_len 8
299 #define	reg_aagc_if_x0_lsb 0
300 #define xd_p_reg_aagc_if_x1	0xA030
301 #define	reg_aagc_if_x1_pos 0
302 #define	reg_aagc_if_x1_len 8
303 #define	reg_aagc_if_x1_lsb 0
304 #define xd_p_reg_aagc_if_x2	0xA031
305 #define	reg_aagc_if_x2_pos 0
306 #define	reg_aagc_if_x2_len 8
307 #define	reg_aagc_if_x2_lsb 0
308 #define xd_p_reg_aagc_if_x3	0xA032
309 #define	reg_aagc_if_x3_pos 0
310 #define	reg_aagc_if_x3_len 8
311 #define	reg_aagc_if_x3_lsb 0
312 #define xd_p_reg_aagc_if_x4	0xA033
313 #define	reg_aagc_if_x4_pos 0
314 #define	reg_aagc_if_x4_len 8
315 #define	reg_aagc_if_x4_lsb 0
316 #define xd_p_reg_aagc_if_x5	0xA034
317 #define	reg_aagc_if_x5_pos 0
318 #define	reg_aagc_if_x5_len 8
319 #define	reg_aagc_if_x5_lsb 0
320 #define xd_p_reg_aagc_if_x6	0xA035
321 #define	reg_aagc_if_x6_pos 0
322 #define	reg_aagc_if_x6_len 8
323 #define	reg_aagc_if_x6_lsb 0
324 #define xd_p_reg_aagc_if_x7	0xA036
325 #define	reg_aagc_if_x7_pos 0
326 #define	reg_aagc_if_x7_len 8
327 #define	reg_aagc_if_x7_lsb 0
328 #define xd_p_reg_aagc_if_x8	0xA037
329 #define	reg_aagc_if_x8_pos 0
330 #define	reg_aagc_if_x8_len 8
331 #define	reg_aagc_if_x8_lsb 0
332 #define xd_p_reg_aagc_if_x9	0xA038
333 #define	reg_aagc_if_x9_pos 0
334 #define	reg_aagc_if_x9_len 8
335 #define	reg_aagc_if_x9_lsb 0
336 #define xd_p_reg_aagc_if_x10	0xA039
337 #define	reg_aagc_if_x10_pos 0
338 #define	reg_aagc_if_x10_len 8
339 #define	reg_aagc_if_x10_lsb 0
340 #define xd_p_reg_aagc_if_x11	0xA03A
341 #define	reg_aagc_if_x11_pos 0
342 #define	reg_aagc_if_x11_len 8
343 #define	reg_aagc_if_x11_lsb 0
344 #define xd_p_reg_aagc_if_x12	0xA03B
345 #define	reg_aagc_if_x12_pos 0
346 #define	reg_aagc_if_x12_len 8
347 #define	reg_aagc_if_x12_lsb 0
348 #define xd_p_reg_aagc_if_x13	0xA03C
349 #define	reg_aagc_if_x13_pos 0
350 #define	reg_aagc_if_x13_len 8
351 #define	reg_aagc_if_x13_lsb 0
352 #define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca	0xA03D
353 #define	reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
354 #define	reg_aagc_min_rf_ctl_8bit_for_dca_len 8
355 #define	reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
356 #define xd_p_reg_aagc_min_if_ctl_8bit_for_dca	0xA03E
357 #define	reg_aagc_min_if_ctl_8bit_for_dca_pos 0
358 #define	reg_aagc_min_if_ctl_8bit_for_dca_len 8
359 #define	reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
360 #define xd_r_reg_aagc_total_gain_7_0	0xA070
361 #define	reg_aagc_total_gain_7_0_pos 0
362 #define	reg_aagc_total_gain_7_0_len 8
363 #define	reg_aagc_total_gain_7_0_lsb 0
364 #define xd_r_reg_aagc_total_gain_15_8	0xA071
365 #define	reg_aagc_total_gain_15_8_pos 0
366 #define	reg_aagc_total_gain_15_8_len 8
367 #define	reg_aagc_total_gain_15_8_lsb 8
368 #define xd_p_reg_aagc_in_sat_cnt_7_0	0xA074
369 #define	reg_aagc_in_sat_cnt_7_0_pos 0
370 #define	reg_aagc_in_sat_cnt_7_0_len 8
371 #define	reg_aagc_in_sat_cnt_7_0_lsb 0
372 #define xd_p_reg_aagc_in_sat_cnt_15_8	0xA075
373 #define	reg_aagc_in_sat_cnt_15_8_pos 0
374 #define	reg_aagc_in_sat_cnt_15_8_len 8
375 #define	reg_aagc_in_sat_cnt_15_8_lsb 8
376 #define xd_p_reg_aagc_in_sat_cnt_23_16	0xA076
377 #define	reg_aagc_in_sat_cnt_23_16_pos 0
378 #define	reg_aagc_in_sat_cnt_23_16_len 8
379 #define	reg_aagc_in_sat_cnt_23_16_lsb 16
380 #define xd_p_reg_aagc_in_sat_cnt_31_24	0xA077
381 #define	reg_aagc_in_sat_cnt_31_24_pos 0
382 #define	reg_aagc_in_sat_cnt_31_24_len 8
383 #define	reg_aagc_in_sat_cnt_31_24_lsb 24
384 #define xd_r_reg_aagc_digital_rf_volt_7_0	0xA078
385 #define	reg_aagc_digital_rf_volt_7_0_pos 0
386 #define	reg_aagc_digital_rf_volt_7_0_len 8
387 #define	reg_aagc_digital_rf_volt_7_0_lsb 0
388 #define xd_r_reg_aagc_digital_rf_volt_9_8	0xA079
389 #define	reg_aagc_digital_rf_volt_9_8_pos 0
390 #define	reg_aagc_digital_rf_volt_9_8_len 2
391 #define	reg_aagc_digital_rf_volt_9_8_lsb 8
392 #define xd_r_reg_aagc_digital_if_volt_7_0	0xA07A
393 #define	reg_aagc_digital_if_volt_7_0_pos 0
394 #define	reg_aagc_digital_if_volt_7_0_len 8
395 #define	reg_aagc_digital_if_volt_7_0_lsb 0
396 #define xd_r_reg_aagc_digital_if_volt_9_8	0xA07B
397 #define	reg_aagc_digital_if_volt_9_8_pos 0
398 #define	reg_aagc_digital_if_volt_9_8_len 2
399 #define	reg_aagc_digital_if_volt_9_8_lsb 8
400 #define xd_r_reg_aagc_rf_gain	0xA07C
401 #define	reg_aagc_rf_gain_pos 0
402 #define	reg_aagc_rf_gain_len 8
403 #define	reg_aagc_rf_gain_lsb 0
404 #define xd_r_reg_aagc_if_gain	0xA07D
405 #define	reg_aagc_if_gain_pos 0
406 #define	reg_aagc_if_gain_len 8
407 #define	reg_aagc_if_gain_lsb 0
408 #define xd_p_tinr_imp_indicator	0xA080
409 #define	tinr_imp_indicator_pos 0
410 #define	tinr_imp_indicator_len 2
411 #define	tinr_imp_indicator_lsb 0
412 #define xd_p_reg_tinr_fifo_size	0xA080
413 #define	reg_tinr_fifo_size_pos 2
414 #define	reg_tinr_fifo_size_len 5
415 #define	reg_tinr_fifo_size_lsb 0
416 #define xd_p_reg_tinr_saturation_cnt_th	0xA081
417 #define	reg_tinr_saturation_cnt_th_pos 0
418 #define	reg_tinr_saturation_cnt_th_len 4
419 #define	reg_tinr_saturation_cnt_th_lsb 0
420 #define xd_p_reg_tinr_saturation_th_3_0	0xA081
421 #define	reg_tinr_saturation_th_3_0_pos 4
422 #define	reg_tinr_saturation_th_3_0_len 4
423 #define	reg_tinr_saturation_th_3_0_lsb 0
424 #define xd_p_reg_tinr_saturation_th_8_4	0xA082
425 #define	reg_tinr_saturation_th_8_4_pos 0
426 #define	reg_tinr_saturation_th_8_4_len 5
427 #define	reg_tinr_saturation_th_8_4_lsb 4
428 #define xd_p_reg_tinr_imp_duration_th_2k_7_0	0xA083
429 #define	reg_tinr_imp_duration_th_2k_7_0_pos 0
430 #define	reg_tinr_imp_duration_th_2k_7_0_len 8
431 #define	reg_tinr_imp_duration_th_2k_7_0_lsb 0
432 #define xd_p_reg_tinr_imp_duration_th_2k_8	0xA084
433 #define	reg_tinr_imp_duration_th_2k_8_pos 0
434 #define	reg_tinr_imp_duration_th_2k_8_len 1
435 #define	reg_tinr_imp_duration_th_2k_8_lsb 0
436 #define xd_p_reg_tinr_imp_duration_th_8k_7_0	0xA085
437 #define	reg_tinr_imp_duration_th_8k_7_0_pos 0
438 #define	reg_tinr_imp_duration_th_8k_7_0_len 8
439 #define	reg_tinr_imp_duration_th_8k_7_0_lsb 0
440 #define xd_p_reg_tinr_imp_duration_th_8k_10_8	0xA086
441 #define	reg_tinr_imp_duration_th_8k_10_8_pos 0
442 #define	reg_tinr_imp_duration_th_8k_10_8_len 3
443 #define	reg_tinr_imp_duration_th_8k_10_8_lsb 8
444 #define xd_p_reg_tinr_freq_ratio_6m_7_0	0xA087
445 #define	reg_tinr_freq_ratio_6m_7_0_pos 0
446 #define	reg_tinr_freq_ratio_6m_7_0_len 8
447 #define	reg_tinr_freq_ratio_6m_7_0_lsb 0
448 #define xd_p_reg_tinr_freq_ratio_6m_12_8	0xA088
449 #define	reg_tinr_freq_ratio_6m_12_8_pos 0
450 #define	reg_tinr_freq_ratio_6m_12_8_len 5
451 #define	reg_tinr_freq_ratio_6m_12_8_lsb 8
452 #define xd_p_reg_tinr_freq_ratio_7m_7_0	0xA089
453 #define	reg_tinr_freq_ratio_7m_7_0_pos 0
454 #define	reg_tinr_freq_ratio_7m_7_0_len 8
455 #define	reg_tinr_freq_ratio_7m_7_0_lsb 0
456 #define xd_p_reg_tinr_freq_ratio_7m_12_8	0xA08A
457 #define	reg_tinr_freq_ratio_7m_12_8_pos 0
458 #define	reg_tinr_freq_ratio_7m_12_8_len 5
459 #define	reg_tinr_freq_ratio_7m_12_8_lsb 8
460 #define xd_p_reg_tinr_freq_ratio_8m_7_0	0xA08B
461 #define	reg_tinr_freq_ratio_8m_7_0_pos 0
462 #define	reg_tinr_freq_ratio_8m_7_0_len 8
463 #define	reg_tinr_freq_ratio_8m_7_0_lsb 0
464 #define xd_p_reg_tinr_freq_ratio_8m_12_8	0xA08C
465 #define	reg_tinr_freq_ratio_8m_12_8_pos 0
466 #define	reg_tinr_freq_ratio_8m_12_8_len 5
467 #define	reg_tinr_freq_ratio_8m_12_8_lsb 8
468 #define xd_p_reg_tinr_imp_duration_th_low_2k	0xA08D
469 #define	reg_tinr_imp_duration_th_low_2k_pos 0
470 #define	reg_tinr_imp_duration_th_low_2k_len 8
471 #define	reg_tinr_imp_duration_th_low_2k_lsb 0
472 #define xd_p_reg_tinr_imp_duration_th_low_8k	0xA08E
473 #define	reg_tinr_imp_duration_th_low_8k_pos 0
474 #define	reg_tinr_imp_duration_th_low_8k_len 8
475 #define	reg_tinr_imp_duration_th_low_8k_lsb 0
476 #define xd_r_reg_tinr_counter_7_0	0xA090
477 #define	reg_tinr_counter_7_0_pos 0
478 #define	reg_tinr_counter_7_0_len 8
479 #define	reg_tinr_counter_7_0_lsb 0
480 #define xd_r_reg_tinr_counter_15_8	0xA091
481 #define	reg_tinr_counter_15_8_pos 0
482 #define	reg_tinr_counter_15_8_len 8
483 #define	reg_tinr_counter_15_8_lsb 8
484 #define xd_p_reg_tinr_adative_tinr_en	0xA093
485 #define	reg_tinr_adative_tinr_en_pos 0
486 #define	reg_tinr_adative_tinr_en_len 1
487 #define	reg_tinr_adative_tinr_en_lsb 0
488 #define xd_p_reg_tinr_peak_fifo_size	0xA093
489 #define	reg_tinr_peak_fifo_size_pos 1
490 #define	reg_tinr_peak_fifo_size_len 5
491 #define	reg_tinr_peak_fifo_size_lsb 0
492 #define xd_p_reg_tinr_counter_rst	0xA093
493 #define	reg_tinr_counter_rst_pos 6
494 #define	reg_tinr_counter_rst_len 1
495 #define	reg_tinr_counter_rst_lsb 0
496 #define xd_p_reg_tinr_search_period_7_0	0xA094
497 #define	reg_tinr_search_period_7_0_pos 0
498 #define	reg_tinr_search_period_7_0_len 8
499 #define	reg_tinr_search_period_7_0_lsb 0
500 #define xd_p_reg_tinr_search_period_15_8	0xA095
501 #define	reg_tinr_search_period_15_8_pos 0
502 #define	reg_tinr_search_period_15_8_len 8
503 #define	reg_tinr_search_period_15_8_lsb 8
504 #define xd_p_reg_ccifs_fcw_7_0	0xA0A0
505 #define	reg_ccifs_fcw_7_0_pos 0
506 #define	reg_ccifs_fcw_7_0_len 8
507 #define	reg_ccifs_fcw_7_0_lsb 0
508 #define xd_p_reg_ccifs_fcw_12_8	0xA0A1
509 #define	reg_ccifs_fcw_12_8_pos 0
510 #define	reg_ccifs_fcw_12_8_len 5
511 #define	reg_ccifs_fcw_12_8_lsb 8
512 #define xd_p_reg_ccifs_spec_inv	0xA0A1
513 #define	reg_ccifs_spec_inv_pos 5
514 #define	reg_ccifs_spec_inv_len 1
515 #define	reg_ccifs_spec_inv_lsb 0
516 #define xd_p_reg_gp_trigger	0xA0A2
517 #define	reg_gp_trigger_pos 0
518 #define	reg_gp_trigger_len 1
519 #define	reg_gp_trigger_lsb 0
520 #define xd_p_reg_trigger_sel	0xA0A2
521 #define	reg_trigger_sel_pos 1
522 #define	reg_trigger_sel_len 2
523 #define	reg_trigger_sel_lsb 0
524 #define xd_p_reg_debug_ofdm	0xA0A2
525 #define	reg_debug_ofdm_pos 3
526 #define	reg_debug_ofdm_len 2
527 #define	reg_debug_ofdm_lsb 0
528 #define xd_p_reg_trigger_module_sel	0xA0A3
529 #define	reg_trigger_module_sel_pos 0
530 #define	reg_trigger_module_sel_len 6
531 #define	reg_trigger_module_sel_lsb 0
532 #define xd_p_reg_trigger_set_sel	0xA0A4
533 #define	reg_trigger_set_sel_pos 0
534 #define	reg_trigger_set_sel_len 6
535 #define	reg_trigger_set_sel_lsb 0
536 #define xd_p_reg_fw_int_mask_n	0xA0A4
537 #define	reg_fw_int_mask_n_pos 6
538 #define	reg_fw_int_mask_n_len 1
539 #define	reg_fw_int_mask_n_lsb 0
540 #define xd_p_reg_debug_group	0xA0A5
541 #define	reg_debug_group_pos 0
542 #define	reg_debug_group_len 4
543 #define	reg_debug_group_lsb 0
544 #define xd_p_reg_odbg_clk_sel	0xA0A5
545 #define	reg_odbg_clk_sel_pos 4
546 #define	reg_odbg_clk_sel_len 2
547 #define	reg_odbg_clk_sel_lsb 0
548 #define xd_p_reg_ccif_sc	0xA0C0
549 #define	reg_ccif_sc_pos 0
550 #define	reg_ccif_sc_len 4
551 #define	reg_ccif_sc_lsb 0
552 #define xd_r_reg_ccif_saturate	0xA0C1
553 #define	reg_ccif_saturate_pos 0
554 #define	reg_ccif_saturate_len 2
555 #define	reg_ccif_saturate_lsb 0
556 #define xd_r_reg_antif_saturate	0xA0C1
557 #define	reg_antif_saturate_pos 2
558 #define	reg_antif_saturate_len 4
559 #define	reg_antif_saturate_lsb 0
560 #define xd_r_reg_acif_saturate	0xA0C2
561 #define	reg_acif_saturate_pos 0
562 #define	reg_acif_saturate_len 8
563 #define	reg_acif_saturate_lsb 0
564 #define xd_p_reg_tmr_timer0_threshold_7_0	0xA0C8
565 #define	reg_tmr_timer0_threshold_7_0_pos 0
566 #define	reg_tmr_timer0_threshold_7_0_len 8
567 #define	reg_tmr_timer0_threshold_7_0_lsb 0
568 #define xd_p_reg_tmr_timer0_threshold_15_8	0xA0C9
569 #define	reg_tmr_timer0_threshold_15_8_pos 0
570 #define	reg_tmr_timer0_threshold_15_8_len 8
571 #define	reg_tmr_timer0_threshold_15_8_lsb 8
572 #define xd_p_reg_tmr_timer0_enable	0xA0CA
573 #define	reg_tmr_timer0_enable_pos 0
574 #define	reg_tmr_timer0_enable_len 1
575 #define	reg_tmr_timer0_enable_lsb 0
576 #define xd_p_reg_tmr_timer0_clk_sel	0xA0CA
577 #define	reg_tmr_timer0_clk_sel_pos 1
578 #define	reg_tmr_timer0_clk_sel_len 1
579 #define	reg_tmr_timer0_clk_sel_lsb 0
580 #define xd_p_reg_tmr_timer0_int	0xA0CA
581 #define	reg_tmr_timer0_int_pos 2
582 #define	reg_tmr_timer0_int_len 1
583 #define	reg_tmr_timer0_int_lsb 0
584 #define xd_p_reg_tmr_timer0_rst	0xA0CA
585 #define	reg_tmr_timer0_rst_pos 3
586 #define	reg_tmr_timer0_rst_len 1
587 #define	reg_tmr_timer0_rst_lsb 0
588 #define xd_r_reg_tmr_timer0_count_7_0	0xA0CB
589 #define	reg_tmr_timer0_count_7_0_pos 0
590 #define	reg_tmr_timer0_count_7_0_len 8
591 #define	reg_tmr_timer0_count_7_0_lsb 0
592 #define xd_r_reg_tmr_timer0_count_15_8	0xA0CC
593 #define	reg_tmr_timer0_count_15_8_pos 0
594 #define	reg_tmr_timer0_count_15_8_len 8
595 #define	reg_tmr_timer0_count_15_8_lsb 8
596 #define xd_p_reg_suspend	0xA0CD
597 #define	reg_suspend_pos 0
598 #define	reg_suspend_len 1
599 #define	reg_suspend_lsb 0
600 #define xd_p_reg_suspend_rdy	0xA0CD
601 #define	reg_suspend_rdy_pos 1
602 #define	reg_suspend_rdy_len 1
603 #define	reg_suspend_rdy_lsb 0
604 #define xd_p_reg_resume	0xA0CD
605 #define	reg_resume_pos 2
606 #define	reg_resume_len 1
607 #define	reg_resume_lsb 0
608 #define xd_p_reg_resume_rdy	0xA0CD
609 #define	reg_resume_rdy_pos 3
610 #define	reg_resume_rdy_len 1
611 #define	reg_resume_rdy_lsb 0
612 #define xd_p_reg_fmf	0xA0CE
613 #define	reg_fmf_pos 0
614 #define	reg_fmf_len 8
615 #define	reg_fmf_lsb 0
616 #define xd_p_ccid_accumulate_num_2k_7_0	0xA100
617 #define	ccid_accumulate_num_2k_7_0_pos 0
618 #define	ccid_accumulate_num_2k_7_0_len 8
619 #define	ccid_accumulate_num_2k_7_0_lsb 0
620 #define xd_p_ccid_accumulate_num_2k_12_8	0xA101
621 #define	ccid_accumulate_num_2k_12_8_pos 0
622 #define	ccid_accumulate_num_2k_12_8_len 5
623 #define	ccid_accumulate_num_2k_12_8_lsb 8
624 #define xd_p_ccid_accumulate_num_8k_7_0	0xA102
625 #define	ccid_accumulate_num_8k_7_0_pos 0
626 #define	ccid_accumulate_num_8k_7_0_len 8
627 #define	ccid_accumulate_num_8k_7_0_lsb 0
628 #define xd_p_ccid_accumulate_num_8k_14_8	0xA103
629 #define	ccid_accumulate_num_8k_14_8_pos 0
630 #define	ccid_accumulate_num_8k_14_8_len 7
631 #define	ccid_accumulate_num_8k_14_8_lsb 8
632 #define xd_p_ccid_desired_level_0	0xA103
633 #define	ccid_desired_level_0_pos 7
634 #define	ccid_desired_level_0_len 1
635 #define	ccid_desired_level_0_lsb 0
636 #define xd_p_ccid_desired_level_8_1	0xA104
637 #define	ccid_desired_level_8_1_pos 0
638 #define	ccid_desired_level_8_1_len 8
639 #define	ccid_desired_level_8_1_lsb 1
640 #define xd_p_ccid_apply_delay	0xA105
641 #define	ccid_apply_delay_pos 0
642 #define	ccid_apply_delay_len 7
643 #define	ccid_apply_delay_lsb 0
644 #define xd_p_ccid_CCID_Threshold1	0xA106
645 #define	ccid_CCID_Threshold1_pos 0
646 #define	ccid_CCID_Threshold1_len 8
647 #define	ccid_CCID_Threshold1_lsb 0
648 #define xd_p_ccid_CCID_Threshold2	0xA107
649 #define	ccid_CCID_Threshold2_pos 0
650 #define	ccid_CCID_Threshold2_len 8
651 #define	ccid_CCID_Threshold2_lsb 0
652 #define xd_p_reg_ccid_gain_scale	0xA108
653 #define	reg_ccid_gain_scale_pos 0
654 #define	reg_ccid_gain_scale_len 4
655 #define	reg_ccid_gain_scale_lsb 0
656 #define xd_p_reg_ccid2_passband_gain_set	0xA108
657 #define	reg_ccid2_passband_gain_set_pos 4
658 #define	reg_ccid2_passband_gain_set_len 4
659 #define	reg_ccid2_passband_gain_set_lsb 0
660 #define xd_r_ccid_multiplier_7_0	0xA109
661 #define	ccid_multiplier_7_0_pos 0
662 #define	ccid_multiplier_7_0_len 8
663 #define	ccid_multiplier_7_0_lsb 0
664 #define xd_r_ccid_multiplier_15_8	0xA10A
665 #define	ccid_multiplier_15_8_pos 0
666 #define	ccid_multiplier_15_8_len 8
667 #define	ccid_multiplier_15_8_lsb 8
668 #define xd_r_ccid_right_shift_bits	0xA10B
669 #define	ccid_right_shift_bits_pos 0
670 #define	ccid_right_shift_bits_len 4
671 #define	ccid_right_shift_bits_lsb 0
672 #define xd_r_reg_ccid_sx_7_0	0xA10C
673 #define	reg_ccid_sx_7_0_pos 0
674 #define	reg_ccid_sx_7_0_len 8
675 #define	reg_ccid_sx_7_0_lsb 0
676 #define xd_r_reg_ccid_sx_15_8	0xA10D
677 #define	reg_ccid_sx_15_8_pos 0
678 #define	reg_ccid_sx_15_8_len 8
679 #define	reg_ccid_sx_15_8_lsb 8
680 #define xd_r_reg_ccid_sx_21_16	0xA10E
681 #define	reg_ccid_sx_21_16_pos 0
682 #define	reg_ccid_sx_21_16_len 6
683 #define	reg_ccid_sx_21_16_lsb 16
684 #define xd_r_reg_ccid_sy_7_0	0xA110
685 #define	reg_ccid_sy_7_0_pos 0
686 #define	reg_ccid_sy_7_0_len 8
687 #define	reg_ccid_sy_7_0_lsb 0
688 #define xd_r_reg_ccid_sy_15_8	0xA111
689 #define	reg_ccid_sy_15_8_pos 0
690 #define	reg_ccid_sy_15_8_len 8
691 #define	reg_ccid_sy_15_8_lsb 8
692 #define xd_r_reg_ccid_sy_23_16	0xA112
693 #define	reg_ccid_sy_23_16_pos 0
694 #define	reg_ccid_sy_23_16_len 8
695 #define	reg_ccid_sy_23_16_lsb 16
696 #define xd_r_reg_ccid2_sz_7_0	0xA114
697 #define	reg_ccid2_sz_7_0_pos 0
698 #define	reg_ccid2_sz_7_0_len 8
699 #define	reg_ccid2_sz_7_0_lsb 0
700 #define xd_r_reg_ccid2_sz_15_8	0xA115
701 #define	reg_ccid2_sz_15_8_pos 0
702 #define	reg_ccid2_sz_15_8_len 8
703 #define	reg_ccid2_sz_15_8_lsb 8
704 #define xd_r_reg_ccid2_sz_23_16	0xA116
705 #define	reg_ccid2_sz_23_16_pos 0
706 #define	reg_ccid2_sz_23_16_len 8
707 #define	reg_ccid2_sz_23_16_lsb 16
708 #define xd_r_reg_ccid2_sz_25_24	0xA117
709 #define	reg_ccid2_sz_25_24_pos 0
710 #define	reg_ccid2_sz_25_24_len 2
711 #define	reg_ccid2_sz_25_24_lsb 24
712 #define xd_r_reg_ccid2_sy_7_0	0xA118
713 #define	reg_ccid2_sy_7_0_pos 0
714 #define	reg_ccid2_sy_7_0_len 8
715 #define	reg_ccid2_sy_7_0_lsb 0
716 #define xd_r_reg_ccid2_sy_15_8	0xA119
717 #define	reg_ccid2_sy_15_8_pos 0
718 #define	reg_ccid2_sy_15_8_len 8
719 #define	reg_ccid2_sy_15_8_lsb 8
720 #define xd_r_reg_ccid2_sy_23_16	0xA11A
721 #define	reg_ccid2_sy_23_16_pos 0
722 #define	reg_ccid2_sy_23_16_len 8
723 #define	reg_ccid2_sy_23_16_lsb 16
724 #define xd_r_reg_ccid2_sy_25_24	0xA11B
725 #define	reg_ccid2_sy_25_24_pos 0
726 #define	reg_ccid2_sy_25_24_len 2
727 #define	reg_ccid2_sy_25_24_lsb 24
728 #define xd_p_dagc1_accumulate_num_2k_7_0	0xA120
729 #define	dagc1_accumulate_num_2k_7_0_pos 0
730 #define	dagc1_accumulate_num_2k_7_0_len 8
731 #define	dagc1_accumulate_num_2k_7_0_lsb 0
732 #define xd_p_dagc1_accumulate_num_2k_12_8	0xA121
733 #define	dagc1_accumulate_num_2k_12_8_pos 0
734 #define	dagc1_accumulate_num_2k_12_8_len 5
735 #define	dagc1_accumulate_num_2k_12_8_lsb 8
736 #define xd_p_dagc1_accumulate_num_8k_7_0	0xA122
737 #define	dagc1_accumulate_num_8k_7_0_pos 0
738 #define	dagc1_accumulate_num_8k_7_0_len 8
739 #define	dagc1_accumulate_num_8k_7_0_lsb 0
740 #define xd_p_dagc1_accumulate_num_8k_14_8	0xA123
741 #define	dagc1_accumulate_num_8k_14_8_pos 0
742 #define	dagc1_accumulate_num_8k_14_8_len 7
743 #define	dagc1_accumulate_num_8k_14_8_lsb 8
744 #define xd_p_dagc1_desired_level_0	0xA123
745 #define	dagc1_desired_level_0_pos 7
746 #define	dagc1_desired_level_0_len 1
747 #define	dagc1_desired_level_0_lsb 0
748 #define xd_p_dagc1_desired_level_8_1	0xA124
749 #define	dagc1_desired_level_8_1_pos 0
750 #define	dagc1_desired_level_8_1_len 8
751 #define	dagc1_desired_level_8_1_lsb 1
752 #define xd_p_dagc1_apply_delay	0xA125
753 #define	dagc1_apply_delay_pos 0
754 #define	dagc1_apply_delay_len 7
755 #define	dagc1_apply_delay_lsb 0
756 #define xd_p_dagc1_bypass_scale_ctl	0xA126
757 #define	dagc1_bypass_scale_ctl_pos 0
758 #define	dagc1_bypass_scale_ctl_len 2
759 #define	dagc1_bypass_scale_ctl_lsb 0
760 #define xd_p_reg_dagc1_in_sat_cnt_7_0	0xA127
761 #define	reg_dagc1_in_sat_cnt_7_0_pos 0
762 #define	reg_dagc1_in_sat_cnt_7_0_len 8
763 #define	reg_dagc1_in_sat_cnt_7_0_lsb 0
764 #define xd_p_reg_dagc1_in_sat_cnt_15_8	0xA128
765 #define	reg_dagc1_in_sat_cnt_15_8_pos 0
766 #define	reg_dagc1_in_sat_cnt_15_8_len 8
767 #define	reg_dagc1_in_sat_cnt_15_8_lsb 8
768 #define xd_p_reg_dagc1_in_sat_cnt_23_16	0xA129
769 #define	reg_dagc1_in_sat_cnt_23_16_pos 0
770 #define	reg_dagc1_in_sat_cnt_23_16_len 8
771 #define	reg_dagc1_in_sat_cnt_23_16_lsb 16
772 #define xd_p_reg_dagc1_in_sat_cnt_31_24	0xA12A
773 #define	reg_dagc1_in_sat_cnt_31_24_pos 0
774 #define	reg_dagc1_in_sat_cnt_31_24_len 8
775 #define	reg_dagc1_in_sat_cnt_31_24_lsb 24
776 #define xd_p_reg_dagc1_out_sat_cnt_7_0	0xA12B
777 #define	reg_dagc1_out_sat_cnt_7_0_pos 0
778 #define	reg_dagc1_out_sat_cnt_7_0_len 8
779 #define	reg_dagc1_out_sat_cnt_7_0_lsb 0
780 #define xd_p_reg_dagc1_out_sat_cnt_15_8	0xA12C
781 #define	reg_dagc1_out_sat_cnt_15_8_pos 0
782 #define	reg_dagc1_out_sat_cnt_15_8_len 8
783 #define	reg_dagc1_out_sat_cnt_15_8_lsb 8
784 #define xd_p_reg_dagc1_out_sat_cnt_23_16	0xA12D
785 #define	reg_dagc1_out_sat_cnt_23_16_pos 0
786 #define	reg_dagc1_out_sat_cnt_23_16_len 8
787 #define	reg_dagc1_out_sat_cnt_23_16_lsb 16
788 #define xd_p_reg_dagc1_out_sat_cnt_31_24	0xA12E
789 #define	reg_dagc1_out_sat_cnt_31_24_pos 0
790 #define	reg_dagc1_out_sat_cnt_31_24_len 8
791 #define	reg_dagc1_out_sat_cnt_31_24_lsb 24
792 #define xd_r_dagc1_multiplier_7_0	0xA136
793 #define	dagc1_multiplier_7_0_pos 0
794 #define	dagc1_multiplier_7_0_len 8
795 #define	dagc1_multiplier_7_0_lsb 0
796 #define xd_r_dagc1_multiplier_15_8	0xA137
797 #define	dagc1_multiplier_15_8_pos 0
798 #define	dagc1_multiplier_15_8_len 8
799 #define	dagc1_multiplier_15_8_lsb 8
800 #define xd_r_dagc1_right_shift_bits	0xA138
801 #define	dagc1_right_shift_bits_pos 0
802 #define	dagc1_right_shift_bits_len 4
803 #define	dagc1_right_shift_bits_lsb 0
804 #define xd_p_reg_bfs_fcw_7_0	0xA140
805 #define	reg_bfs_fcw_7_0_pos 0
806 #define	reg_bfs_fcw_7_0_len 8
807 #define	reg_bfs_fcw_7_0_lsb 0
808 #define xd_p_reg_bfs_fcw_15_8	0xA141
809 #define	reg_bfs_fcw_15_8_pos 0
810 #define	reg_bfs_fcw_15_8_len 8
811 #define	reg_bfs_fcw_15_8_lsb 8
812 #define xd_p_reg_bfs_fcw_22_16	0xA142
813 #define	reg_bfs_fcw_22_16_pos 0
814 #define	reg_bfs_fcw_22_16_len 7
815 #define	reg_bfs_fcw_22_16_lsb 16
816 #define xd_p_reg_antif_sf_7_0	0xA144
817 #define	reg_antif_sf_7_0_pos 0
818 #define	reg_antif_sf_7_0_len 8
819 #define	reg_antif_sf_7_0_lsb 0
820 #define xd_p_reg_antif_sf_11_8	0xA145
821 #define	reg_antif_sf_11_8_pos 0
822 #define	reg_antif_sf_11_8_len 4
823 #define	reg_antif_sf_11_8_lsb 8
824 #define xd_r_bfs_fcw_q_7_0	0xA150
825 #define	bfs_fcw_q_7_0_pos 0
826 #define	bfs_fcw_q_7_0_len 8
827 #define	bfs_fcw_q_7_0_lsb 0
828 #define xd_r_bfs_fcw_q_15_8	0xA151
829 #define	bfs_fcw_q_15_8_pos 0
830 #define	bfs_fcw_q_15_8_len 8
831 #define	bfs_fcw_q_15_8_lsb 8
832 #define xd_r_bfs_fcw_q_22_16	0xA152
833 #define	bfs_fcw_q_22_16_pos 0
834 #define	bfs_fcw_q_22_16_len 7
835 #define	bfs_fcw_q_22_16_lsb 16
836 #define xd_p_reg_dca_enu	0xA160
837 #define	reg_dca_enu_pos 0
838 #define	reg_dca_enu_len 1
839 #define	reg_dca_enu_lsb 0
840 #define xd_p_reg_dca_enl	0xA160
841 #define	reg_dca_enl_pos 1
842 #define	reg_dca_enl_len 1
843 #define	reg_dca_enl_lsb 0
844 #define xd_p_reg_dca_lower_chip	0xA160
845 #define	reg_dca_lower_chip_pos 2
846 #define	reg_dca_lower_chip_len 1
847 #define	reg_dca_lower_chip_lsb 0
848 #define xd_p_reg_dca_upper_chip	0xA160
849 #define	reg_dca_upper_chip_pos 3
850 #define	reg_dca_upper_chip_len 1
851 #define	reg_dca_upper_chip_lsb 0
852 #define xd_p_reg_dca_platch	0xA160
853 #define	reg_dca_platch_pos 4
854 #define	reg_dca_platch_len 1
855 #define	reg_dca_platch_lsb 0
856 #define xd_p_reg_dca_th	0xA161
857 #define	reg_dca_th_pos 0
858 #define	reg_dca_th_len 5
859 #define	reg_dca_th_lsb 0
860 #define xd_p_reg_dca_scale	0xA162
861 #define	reg_dca_scale_pos 0
862 #define	reg_dca_scale_len 4
863 #define	reg_dca_scale_lsb 0
864 #define xd_p_reg_dca_tone_7_0	0xA163
865 #define	reg_dca_tone_7_0_pos 0
866 #define	reg_dca_tone_7_0_len 8
867 #define	reg_dca_tone_7_0_lsb 0
868 #define xd_p_reg_dca_tone_12_8	0xA164
869 #define	reg_dca_tone_12_8_pos 0
870 #define	reg_dca_tone_12_8_len 5
871 #define	reg_dca_tone_12_8_lsb 8
872 #define xd_p_reg_dca_time_7_0	0xA165
873 #define	reg_dca_time_7_0_pos 0
874 #define	reg_dca_time_7_0_len 8
875 #define	reg_dca_time_7_0_lsb 0
876 #define xd_p_reg_dca_time_15_8	0xA166
877 #define	reg_dca_time_15_8_pos 0
878 #define	reg_dca_time_15_8_len 8
879 #define	reg_dca_time_15_8_lsb 8
880 #define xd_r_dcasm	0xA167
881 #define	dcasm_pos 0
882 #define	dcasm_len 3
883 #define	dcasm_lsb 0
884 #define xd_p_reg_qnt_valuew_7_0	0xA168
885 #define	reg_qnt_valuew_7_0_pos 0
886 #define	reg_qnt_valuew_7_0_len 8
887 #define	reg_qnt_valuew_7_0_lsb 0
888 #define xd_p_reg_qnt_valuew_10_8	0xA169
889 #define	reg_qnt_valuew_10_8_pos 0
890 #define	reg_qnt_valuew_10_8_len 3
891 #define	reg_qnt_valuew_10_8_lsb 8
892 #define xd_p_dca_sbx_gain_diff_7_0	0xA16A
893 #define	dca_sbx_gain_diff_7_0_pos 0
894 #define	dca_sbx_gain_diff_7_0_len 8
895 #define	dca_sbx_gain_diff_7_0_lsb 0
896 #define xd_p_dca_sbx_gain_diff_9_8	0xA16B
897 #define	dca_sbx_gain_diff_9_8_pos 0
898 #define	dca_sbx_gain_diff_9_8_len 2
899 #define	dca_sbx_gain_diff_9_8_lsb 8
900 #define xd_p_reg_dca_stand_alone	0xA16C
901 #define	reg_dca_stand_alone_pos 0
902 #define	reg_dca_stand_alone_len 1
903 #define	reg_dca_stand_alone_lsb 0
904 #define xd_p_reg_dca_upper_out_en	0xA16C
905 #define	reg_dca_upper_out_en_pos 1
906 #define	reg_dca_upper_out_en_len 1
907 #define	reg_dca_upper_out_en_lsb 0
908 #define xd_p_reg_dca_rc_en	0xA16C
909 #define	reg_dca_rc_en_pos 2
910 #define	reg_dca_rc_en_len 1
911 #define	reg_dca_rc_en_lsb 0
912 #define xd_p_reg_dca_retrain_send	0xA16C
913 #define	reg_dca_retrain_send_pos 3
914 #define	reg_dca_retrain_send_len 1
915 #define	reg_dca_retrain_send_lsb 0
916 #define xd_p_reg_dca_retrain_rec	0xA16C
917 #define	reg_dca_retrain_rec_pos 4
918 #define	reg_dca_retrain_rec_len 1
919 #define	reg_dca_retrain_rec_lsb 0
920 #define xd_p_reg_dca_api_tpsrdy	0xA16C
921 #define	reg_dca_api_tpsrdy_pos 5
922 #define	reg_dca_api_tpsrdy_len 1
923 #define	reg_dca_api_tpsrdy_lsb 0
924 #define xd_p_reg_dca_symbol_gap	0xA16D
925 #define	reg_dca_symbol_gap_pos 0
926 #define	reg_dca_symbol_gap_len 4
927 #define	reg_dca_symbol_gap_lsb 0
928 #define xd_p_reg_qnt_nfvaluew_7_0	0xA16E
929 #define	reg_qnt_nfvaluew_7_0_pos 0
930 #define	reg_qnt_nfvaluew_7_0_len 8
931 #define	reg_qnt_nfvaluew_7_0_lsb 0
932 #define xd_p_reg_qnt_nfvaluew_10_8	0xA16F
933 #define	reg_qnt_nfvaluew_10_8_pos 0
934 #define	reg_qnt_nfvaluew_10_8_len 3
935 #define	reg_qnt_nfvaluew_10_8_lsb 8
936 #define xd_p_reg_qnt_flatness_thr_7_0	0xA170
937 #define	reg_qnt_flatness_thr_7_0_pos 0
938 #define	reg_qnt_flatness_thr_7_0_len 8
939 #define	reg_qnt_flatness_thr_7_0_lsb 0
940 #define xd_p_reg_qnt_flatness_thr_9_8	0xA171
941 #define	reg_qnt_flatness_thr_9_8_pos 0
942 #define	reg_qnt_flatness_thr_9_8_len 2
943 #define	reg_qnt_flatness_thr_9_8_lsb 8
944 #define xd_p_reg_dca_tone_idx_5_0	0xA171
945 #define	reg_dca_tone_idx_5_0_pos 2
946 #define	reg_dca_tone_idx_5_0_len 6
947 #define	reg_dca_tone_idx_5_0_lsb 0
948 #define xd_p_reg_dca_tone_idx_12_6	0xA172
949 #define	reg_dca_tone_idx_12_6_pos 0
950 #define	reg_dca_tone_idx_12_6_len 7
951 #define	reg_dca_tone_idx_12_6_lsb 6
952 #define xd_p_reg_dca_data_vld	0xA173
953 #define	reg_dca_data_vld_pos 0
954 #define	reg_dca_data_vld_len 1
955 #define	reg_dca_data_vld_lsb 0
956 #define xd_p_reg_dca_read_update	0xA173
957 #define	reg_dca_read_update_pos 1
958 #define	reg_dca_read_update_len 1
959 #define	reg_dca_read_update_lsb 0
960 #define xd_r_reg_dca_data_re_5_0	0xA173
961 #define	reg_dca_data_re_5_0_pos 2
962 #define	reg_dca_data_re_5_0_len 6
963 #define	reg_dca_data_re_5_0_lsb 0
964 #define xd_r_reg_dca_data_re_10_6	0xA174
965 #define	reg_dca_data_re_10_6_pos 0
966 #define	reg_dca_data_re_10_6_len 5
967 #define	reg_dca_data_re_10_6_lsb 6
968 #define xd_r_reg_dca_data_im_7_0	0xA175
969 #define	reg_dca_data_im_7_0_pos 0
970 #define	reg_dca_data_im_7_0_len 8
971 #define	reg_dca_data_im_7_0_lsb 0
972 #define xd_r_reg_dca_data_im_10_8	0xA176
973 #define	reg_dca_data_im_10_8_pos 0
974 #define	reg_dca_data_im_10_8_len 3
975 #define	reg_dca_data_im_10_8_lsb 8
976 #define xd_r_reg_dca_data_h2_7_0	0xA178
977 #define	reg_dca_data_h2_7_0_pos 0
978 #define	reg_dca_data_h2_7_0_len 8
979 #define	reg_dca_data_h2_7_0_lsb 0
980 #define xd_r_reg_dca_data_h2_9_8	0xA179
981 #define	reg_dca_data_h2_9_8_pos 0
982 #define	reg_dca_data_h2_9_8_len 2
983 #define	reg_dca_data_h2_9_8_lsb 8
984 #define xd_p_reg_f_adc_7_0	0xA180
985 #define	reg_f_adc_7_0_pos 0
986 #define	reg_f_adc_7_0_len 8
987 #define	reg_f_adc_7_0_lsb 0
988 #define xd_p_reg_f_adc_15_8	0xA181
989 #define	reg_f_adc_15_8_pos 0
990 #define	reg_f_adc_15_8_len 8
991 #define	reg_f_adc_15_8_lsb 8
992 #define xd_p_reg_f_adc_23_16	0xA182
993 #define	reg_f_adc_23_16_pos 0
994 #define	reg_f_adc_23_16_len 8
995 #define	reg_f_adc_23_16_lsb 16
996 #define xd_r_intp_mu_7_0	0xA190
997 #define	intp_mu_7_0_pos 0
998 #define	intp_mu_7_0_len 8
999 #define	intp_mu_7_0_lsb 0
1000 #define xd_r_intp_mu_15_8	0xA191
1001 #define	intp_mu_15_8_pos 0
1002 #define	intp_mu_15_8_len 8
1003 #define	intp_mu_15_8_lsb 8
1004 #define xd_r_intp_mu_19_16	0xA192
1005 #define	intp_mu_19_16_pos 0
1006 #define	intp_mu_19_16_len 4
1007 #define	intp_mu_19_16_lsb 16
1008 #define xd_p_reg_agc_rst	0xA1A0
1009 #define	reg_agc_rst_pos 0
1010 #define	reg_agc_rst_len 1
1011 #define	reg_agc_rst_lsb 0
1012 #define xd_p_rf_agc_en	0xA1A0
1013 #define	rf_agc_en_pos 1
1014 #define	rf_agc_en_len 1
1015 #define	rf_agc_en_lsb 0
1016 #define xd_p_rf_agc_dis	0xA1A0
1017 #define	rf_agc_dis_pos 2
1018 #define	rf_agc_dis_len 1
1019 #define	rf_agc_dis_lsb 0
1020 #define xd_p_if_agc_rst	0xA1A0
1021 #define	if_agc_rst_pos 3
1022 #define	if_agc_rst_len 1
1023 #define	if_agc_rst_lsb 0
1024 #define xd_p_if_agc_en	0xA1A0
1025 #define	if_agc_en_pos 4
1026 #define	if_agc_en_len 1
1027 #define	if_agc_en_lsb 0
1028 #define xd_p_if_agc_dis	0xA1A0
1029 #define	if_agc_dis_pos 5
1030 #define	if_agc_dis_len 1
1031 #define	if_agc_dis_lsb 0
1032 #define xd_p_agc_lock	0xA1A0
1033 #define	agc_lock_pos 6
1034 #define	agc_lock_len 1
1035 #define	agc_lock_lsb 0
1036 #define xd_p_reg_tinr_rst	0xA1A1
1037 #define	reg_tinr_rst_pos 0
1038 #define	reg_tinr_rst_len 1
1039 #define	reg_tinr_rst_lsb 0
1040 #define xd_p_reg_tinr_en	0xA1A1
1041 #define	reg_tinr_en_pos 1
1042 #define	reg_tinr_en_len 1
1043 #define	reg_tinr_en_lsb 0
1044 #define xd_p_reg_ccifs_en	0xA1A2
1045 #define	reg_ccifs_en_pos 0
1046 #define	reg_ccifs_en_len 1
1047 #define	reg_ccifs_en_lsb 0
1048 #define xd_p_reg_ccifs_dis	0xA1A2
1049 #define	reg_ccifs_dis_pos 1
1050 #define	reg_ccifs_dis_len 1
1051 #define	reg_ccifs_dis_lsb 0
1052 #define xd_p_reg_ccifs_rst	0xA1A2
1053 #define	reg_ccifs_rst_pos 2
1054 #define	reg_ccifs_rst_len 1
1055 #define	reg_ccifs_rst_lsb 0
1056 #define xd_p_reg_ccifs_byp	0xA1A2
1057 #define	reg_ccifs_byp_pos 3
1058 #define	reg_ccifs_byp_len 1
1059 #define	reg_ccifs_byp_lsb 0
1060 #define xd_p_reg_ccif_en	0xA1A3
1061 #define	reg_ccif_en_pos 0
1062 #define	reg_ccif_en_len 1
1063 #define	reg_ccif_en_lsb 0
1064 #define xd_p_reg_ccif_dis	0xA1A3
1065 #define	reg_ccif_dis_pos 1
1066 #define	reg_ccif_dis_len 1
1067 #define	reg_ccif_dis_lsb 0
1068 #define xd_p_reg_ccif_rst	0xA1A3
1069 #define	reg_ccif_rst_pos 2
1070 #define	reg_ccif_rst_len 1
1071 #define	reg_ccif_rst_lsb 0
1072 #define xd_p_reg_ccif_byp	0xA1A3
1073 #define	reg_ccif_byp_pos 3
1074 #define	reg_ccif_byp_len 1
1075 #define	reg_ccif_byp_lsb 0
1076 #define xd_p_dagc1_rst	0xA1A4
1077 #define	dagc1_rst_pos 0
1078 #define	dagc1_rst_len 1
1079 #define	dagc1_rst_lsb 0
1080 #define xd_p_dagc1_en	0xA1A4
1081 #define	dagc1_en_pos 1
1082 #define	dagc1_en_len 1
1083 #define	dagc1_en_lsb 0
1084 #define xd_p_dagc1_mode	0xA1A4
1085 #define	dagc1_mode_pos 2
1086 #define	dagc1_mode_len 2
1087 #define	dagc1_mode_lsb 0
1088 #define xd_p_dagc1_done	0xA1A4
1089 #define	dagc1_done_pos 4
1090 #define	dagc1_done_len 1
1091 #define	dagc1_done_lsb 0
1092 #define xd_p_ccid_rst	0xA1A5
1093 #define	ccid_rst_pos 0
1094 #define	ccid_rst_len 1
1095 #define	ccid_rst_lsb 0
1096 #define xd_p_ccid_en	0xA1A5
1097 #define	ccid_en_pos 1
1098 #define	ccid_en_len 1
1099 #define	ccid_en_lsb 0
1100 #define xd_p_ccid_mode	0xA1A5
1101 #define	ccid_mode_pos 2
1102 #define	ccid_mode_len 2
1103 #define	ccid_mode_lsb 0
1104 #define xd_p_ccid_done	0xA1A5
1105 #define	ccid_done_pos 4
1106 #define	ccid_done_len 1
1107 #define	ccid_done_lsb 0
1108 #define xd_r_ccid_deted	0xA1A5
1109 #define	ccid_deted_pos 5
1110 #define	ccid_deted_len 1
1111 #define	ccid_deted_lsb 0
1112 #define xd_p_ccid2_en	0xA1A5
1113 #define	ccid2_en_pos 6
1114 #define	ccid2_en_len 1
1115 #define	ccid2_en_lsb 0
1116 #define xd_p_ccid2_done	0xA1A5
1117 #define	ccid2_done_pos 7
1118 #define	ccid2_done_len 1
1119 #define	ccid2_done_lsb 0
1120 #define xd_p_reg_bfs_en	0xA1A6
1121 #define	reg_bfs_en_pos 0
1122 #define	reg_bfs_en_len 1
1123 #define	reg_bfs_en_lsb 0
1124 #define xd_p_reg_bfs_dis	0xA1A6
1125 #define	reg_bfs_dis_pos 1
1126 #define	reg_bfs_dis_len 1
1127 #define	reg_bfs_dis_lsb 0
1128 #define xd_p_reg_bfs_rst	0xA1A6
1129 #define	reg_bfs_rst_pos 2
1130 #define	reg_bfs_rst_len 1
1131 #define	reg_bfs_rst_lsb 0
1132 #define xd_p_reg_bfs_byp	0xA1A6
1133 #define	reg_bfs_byp_pos 3
1134 #define	reg_bfs_byp_len 1
1135 #define	reg_bfs_byp_lsb 0
1136 #define xd_p_reg_antif_en	0xA1A7
1137 #define	reg_antif_en_pos 0
1138 #define	reg_antif_en_len 1
1139 #define	reg_antif_en_lsb 0
1140 #define xd_p_reg_antif_dis	0xA1A7
1141 #define	reg_antif_dis_pos 1
1142 #define	reg_antif_dis_len 1
1143 #define	reg_antif_dis_lsb 0
1144 #define xd_p_reg_antif_rst	0xA1A7
1145 #define	reg_antif_rst_pos 2
1146 #define	reg_antif_rst_len 1
1147 #define	reg_antif_rst_lsb 0
1148 #define xd_p_reg_antif_byp	0xA1A7
1149 #define	reg_antif_byp_pos 3
1150 #define	reg_antif_byp_len 1
1151 #define	reg_antif_byp_lsb 0
1152 #define xd_p_intp_en	0xA1A8
1153 #define	intp_en_pos 0
1154 #define	intp_en_len 1
1155 #define	intp_en_lsb 0
1156 #define xd_p_intp_dis	0xA1A8
1157 #define	intp_dis_pos 1
1158 #define	intp_dis_len 1
1159 #define	intp_dis_lsb 0
1160 #define xd_p_intp_rst	0xA1A8
1161 #define	intp_rst_pos 2
1162 #define	intp_rst_len 1
1163 #define	intp_rst_lsb 0
1164 #define xd_p_intp_byp	0xA1A8
1165 #define	intp_byp_pos 3
1166 #define	intp_byp_len 1
1167 #define	intp_byp_lsb 0
1168 #define xd_p_reg_acif_en	0xA1A9
1169 #define	reg_acif_en_pos 0
1170 #define	reg_acif_en_len 1
1171 #define	reg_acif_en_lsb 0
1172 #define xd_p_reg_acif_dis	0xA1A9
1173 #define	reg_acif_dis_pos 1
1174 #define	reg_acif_dis_len 1
1175 #define	reg_acif_dis_lsb 0
1176 #define xd_p_reg_acif_rst	0xA1A9
1177 #define	reg_acif_rst_pos 2
1178 #define	reg_acif_rst_len 1
1179 #define	reg_acif_rst_lsb 0
1180 #define xd_p_reg_acif_byp	0xA1A9
1181 #define	reg_acif_byp_pos 3
1182 #define	reg_acif_byp_len 1
1183 #define	reg_acif_byp_lsb 0
1184 #define xd_p_reg_acif_sync_mode	0xA1A9
1185 #define	reg_acif_sync_mode_pos 4
1186 #define	reg_acif_sync_mode_len 1
1187 #define	reg_acif_sync_mode_lsb 0
1188 #define xd_p_dagc2_rst	0xA1AA
1189 #define	dagc2_rst_pos 0
1190 #define	dagc2_rst_len 1
1191 #define	dagc2_rst_lsb 0
1192 #define xd_p_dagc2_en	0xA1AA
1193 #define	dagc2_en_pos 1
1194 #define	dagc2_en_len 1
1195 #define	dagc2_en_lsb 0
1196 #define xd_p_dagc2_mode	0xA1AA
1197 #define	dagc2_mode_pos 2
1198 #define	dagc2_mode_len 2
1199 #define	dagc2_mode_lsb 0
1200 #define xd_p_dagc2_done	0xA1AA
1201 #define	dagc2_done_pos 4
1202 #define	dagc2_done_len 1
1203 #define	dagc2_done_lsb 0
1204 #define xd_p_reg_dca_en	0xA1AB
1205 #define	reg_dca_en_pos 0
1206 #define	reg_dca_en_len 1
1207 #define	reg_dca_en_lsb 0
1208 #define xd_p_dagc2_accumulate_num_2k_7_0	0xA1C0
1209 #define	dagc2_accumulate_num_2k_7_0_pos 0
1210 #define	dagc2_accumulate_num_2k_7_0_len 8
1211 #define	dagc2_accumulate_num_2k_7_0_lsb 0
1212 #define xd_p_dagc2_accumulate_num_2k_12_8	0xA1C1
1213 #define	dagc2_accumulate_num_2k_12_8_pos 0
1214 #define	dagc2_accumulate_num_2k_12_8_len 5
1215 #define	dagc2_accumulate_num_2k_12_8_lsb 8
1216 #define xd_p_dagc2_accumulate_num_8k_7_0	0xA1C2
1217 #define	dagc2_accumulate_num_8k_7_0_pos 0
1218 #define	dagc2_accumulate_num_8k_7_0_len 8
1219 #define	dagc2_accumulate_num_8k_7_0_lsb 0
1220 #define xd_p_dagc2_accumulate_num_8k_12_8	0xA1C3
1221 #define	dagc2_accumulate_num_8k_12_8_pos 0
1222 #define	dagc2_accumulate_num_8k_12_8_len 5
1223 #define	dagc2_accumulate_num_8k_12_8_lsb 8
1224 #define xd_p_dagc2_desired_level_2_0	0xA1C3
1225 #define	dagc2_desired_level_2_0_pos 5
1226 #define	dagc2_desired_level_2_0_len 3
1227 #define	dagc2_desired_level_2_0_lsb 0
1228 #define xd_p_dagc2_desired_level_8_3	0xA1C4
1229 #define	dagc2_desired_level_8_3_pos 0
1230 #define	dagc2_desired_level_8_3_len 6
1231 #define	dagc2_desired_level_8_3_lsb 3
1232 #define xd_p_dagc2_apply_delay	0xA1C5
1233 #define	dagc2_apply_delay_pos 0
1234 #define	dagc2_apply_delay_len 7
1235 #define	dagc2_apply_delay_lsb 0
1236 #define xd_p_dagc2_bypass_scale_ctl	0xA1C6
1237 #define	dagc2_bypass_scale_ctl_pos 0
1238 #define	dagc2_bypass_scale_ctl_len 3
1239 #define	dagc2_bypass_scale_ctl_lsb 0
1240 #define xd_p_dagc2_programmable_shift1	0xA1C7
1241 #define	dagc2_programmable_shift1_pos 0
1242 #define	dagc2_programmable_shift1_len 8
1243 #define	dagc2_programmable_shift1_lsb 0
1244 #define xd_p_dagc2_programmable_shift2	0xA1C8
1245 #define	dagc2_programmable_shift2_pos 0
1246 #define	dagc2_programmable_shift2_len 8
1247 #define	dagc2_programmable_shift2_lsb 0
1248 #define xd_p_reg_dagc2_in_sat_cnt_7_0	0xA1C9
1249 #define	reg_dagc2_in_sat_cnt_7_0_pos 0
1250 #define	reg_dagc2_in_sat_cnt_7_0_len 8
1251 #define	reg_dagc2_in_sat_cnt_7_0_lsb 0
1252 #define xd_p_reg_dagc2_in_sat_cnt_15_8	0xA1CA
1253 #define	reg_dagc2_in_sat_cnt_15_8_pos 0
1254 #define	reg_dagc2_in_sat_cnt_15_8_len 8
1255 #define	reg_dagc2_in_sat_cnt_15_8_lsb 8
1256 #define xd_p_reg_dagc2_in_sat_cnt_23_16	0xA1CB
1257 #define	reg_dagc2_in_sat_cnt_23_16_pos 0
1258 #define	reg_dagc2_in_sat_cnt_23_16_len 8
1259 #define	reg_dagc2_in_sat_cnt_23_16_lsb 16
1260 #define xd_p_reg_dagc2_in_sat_cnt_31_24	0xA1CC
1261 #define	reg_dagc2_in_sat_cnt_31_24_pos 0
1262 #define	reg_dagc2_in_sat_cnt_31_24_len 8
1263 #define	reg_dagc2_in_sat_cnt_31_24_lsb 24
1264 #define xd_p_reg_dagc2_out_sat_cnt_7_0	0xA1CD
1265 #define	reg_dagc2_out_sat_cnt_7_0_pos 0
1266 #define	reg_dagc2_out_sat_cnt_7_0_len 8
1267 #define	reg_dagc2_out_sat_cnt_7_0_lsb 0
1268 #define xd_p_reg_dagc2_out_sat_cnt_15_8	0xA1CE
1269 #define	reg_dagc2_out_sat_cnt_15_8_pos 0
1270 #define	reg_dagc2_out_sat_cnt_15_8_len 8
1271 #define	reg_dagc2_out_sat_cnt_15_8_lsb 8
1272 #define xd_p_reg_dagc2_out_sat_cnt_23_16	0xA1CF
1273 #define	reg_dagc2_out_sat_cnt_23_16_pos 0
1274 #define	reg_dagc2_out_sat_cnt_23_16_len 8
1275 #define	reg_dagc2_out_sat_cnt_23_16_lsb 16
1276 #define xd_p_reg_dagc2_out_sat_cnt_31_24	0xA1D0
1277 #define	reg_dagc2_out_sat_cnt_31_24_pos 0
1278 #define	reg_dagc2_out_sat_cnt_31_24_len 8
1279 #define	reg_dagc2_out_sat_cnt_31_24_lsb 24
1280 #define xd_r_dagc2_multiplier_7_0	0xA1D6
1281 #define	dagc2_multiplier_7_0_pos 0
1282 #define	dagc2_multiplier_7_0_len 8
1283 #define	dagc2_multiplier_7_0_lsb 0
1284 #define xd_r_dagc2_multiplier_15_8	0xA1D7
1285 #define	dagc2_multiplier_15_8_pos 0
1286 #define	dagc2_multiplier_15_8_len 8
1287 #define	dagc2_multiplier_15_8_lsb 8
1288 #define xd_r_dagc2_right_shift_bits	0xA1D8
1289 #define	dagc2_right_shift_bits_pos 0
1290 #define	dagc2_right_shift_bits_len 4
1291 #define	dagc2_right_shift_bits_lsb 0
1292 #define xd_p_cfoe_NS_coeff1_7_0	0xA200
1293 #define	cfoe_NS_coeff1_7_0_pos 0
1294 #define	cfoe_NS_coeff1_7_0_len 8
1295 #define	cfoe_NS_coeff1_7_0_lsb 0
1296 #define xd_p_cfoe_NS_coeff1_15_8	0xA201
1297 #define	cfoe_NS_coeff1_15_8_pos 0
1298 #define	cfoe_NS_coeff1_15_8_len 8
1299 #define	cfoe_NS_coeff1_15_8_lsb 8
1300 #define xd_p_cfoe_NS_coeff1_23_16	0xA202
1301 #define	cfoe_NS_coeff1_23_16_pos 0
1302 #define	cfoe_NS_coeff1_23_16_len 8
1303 #define	cfoe_NS_coeff1_23_16_lsb 16
1304 #define xd_p_cfoe_NS_coeff1_25_24	0xA203
1305 #define	cfoe_NS_coeff1_25_24_pos 0
1306 #define	cfoe_NS_coeff1_25_24_len 2
1307 #define	cfoe_NS_coeff1_25_24_lsb 24
1308 #define xd_p_cfoe_NS_coeff2_5_0	0xA203
1309 #define	cfoe_NS_coeff2_5_0_pos 2
1310 #define	cfoe_NS_coeff2_5_0_len 6
1311 #define	cfoe_NS_coeff2_5_0_lsb 0
1312 #define xd_p_cfoe_NS_coeff2_13_6	0xA204
1313 #define	cfoe_NS_coeff2_13_6_pos 0
1314 #define	cfoe_NS_coeff2_13_6_len 8
1315 #define	cfoe_NS_coeff2_13_6_lsb 6
1316 #define xd_p_cfoe_NS_coeff2_21_14	0xA205
1317 #define	cfoe_NS_coeff2_21_14_pos 0
1318 #define	cfoe_NS_coeff2_21_14_len 8
1319 #define	cfoe_NS_coeff2_21_14_lsb 14
1320 #define xd_p_cfoe_NS_coeff2_24_22	0xA206
1321 #define	cfoe_NS_coeff2_24_22_pos 0
1322 #define	cfoe_NS_coeff2_24_22_len 3
1323 #define	cfoe_NS_coeff2_24_22_lsb 22
1324 #define xd_p_cfoe_lf_c1_4_0	0xA206
1325 #define	cfoe_lf_c1_4_0_pos 3
1326 #define	cfoe_lf_c1_4_0_len 5
1327 #define	cfoe_lf_c1_4_0_lsb 0
1328 #define xd_p_cfoe_lf_c1_12_5	0xA207
1329 #define	cfoe_lf_c1_12_5_pos 0
1330 #define	cfoe_lf_c1_12_5_len 8
1331 #define	cfoe_lf_c1_12_5_lsb 5
1332 #define xd_p_cfoe_lf_c1_20_13	0xA208
1333 #define	cfoe_lf_c1_20_13_pos 0
1334 #define	cfoe_lf_c1_20_13_len 8
1335 #define	cfoe_lf_c1_20_13_lsb 13
1336 #define xd_p_cfoe_lf_c1_25_21	0xA209
1337 #define	cfoe_lf_c1_25_21_pos 0
1338 #define	cfoe_lf_c1_25_21_len 5
1339 #define	cfoe_lf_c1_25_21_lsb 21
1340 #define xd_p_cfoe_lf_c2_2_0	0xA209
1341 #define	cfoe_lf_c2_2_0_pos 5
1342 #define	cfoe_lf_c2_2_0_len 3
1343 #define	cfoe_lf_c2_2_0_lsb 0
1344 #define xd_p_cfoe_lf_c2_10_3	0xA20A
1345 #define	cfoe_lf_c2_10_3_pos 0
1346 #define	cfoe_lf_c2_10_3_len 8
1347 #define	cfoe_lf_c2_10_3_lsb 3
1348 #define xd_p_cfoe_lf_c2_18_11	0xA20B
1349 #define	cfoe_lf_c2_18_11_pos 0
1350 #define	cfoe_lf_c2_18_11_len 8
1351 #define	cfoe_lf_c2_18_11_lsb 11
1352 #define xd_p_cfoe_lf_c2_25_19	0xA20C
1353 #define	cfoe_lf_c2_25_19_pos 0
1354 #define	cfoe_lf_c2_25_19_len 7
1355 #define	cfoe_lf_c2_25_19_lsb 19
1356 #define xd_p_cfoe_ifod_7_0	0xA20D
1357 #define	cfoe_ifod_7_0_pos 0
1358 #define	cfoe_ifod_7_0_len 8
1359 #define	cfoe_ifod_7_0_lsb 0
1360 #define xd_p_cfoe_ifod_10_8	0xA20E
1361 #define	cfoe_ifod_10_8_pos 0
1362 #define	cfoe_ifod_10_8_len 3
1363 #define	cfoe_ifod_10_8_lsb 8
1364 #define xd_p_cfoe_Divg_ctr_th	0xA20E
1365 #define	cfoe_Divg_ctr_th_pos 4
1366 #define	cfoe_Divg_ctr_th_len 4
1367 #define	cfoe_Divg_ctr_th_lsb 0
1368 #define xd_p_cfoe_FOT_divg_th	0xA20F
1369 #define	cfoe_FOT_divg_th_pos 0
1370 #define	cfoe_FOT_divg_th_len 8
1371 #define	cfoe_FOT_divg_th_lsb 0
1372 #define xd_p_cfoe_FOT_cnvg_th	0xA210
1373 #define	cfoe_FOT_cnvg_th_pos 0
1374 #define	cfoe_FOT_cnvg_th_len 8
1375 #define	cfoe_FOT_cnvg_th_lsb 0
1376 #define xd_p_reg_cfoe_offset_7_0	0xA211
1377 #define	reg_cfoe_offset_7_0_pos 0
1378 #define	reg_cfoe_offset_7_0_len 8
1379 #define	reg_cfoe_offset_7_0_lsb 0
1380 #define xd_p_reg_cfoe_offset_9_8	0xA212
1381 #define	reg_cfoe_offset_9_8_pos 0
1382 #define	reg_cfoe_offset_9_8_len 2
1383 #define	reg_cfoe_offset_9_8_lsb 8
1384 #define xd_p_reg_cfoe_ifoe_sign_corr	0xA212
1385 #define	reg_cfoe_ifoe_sign_corr_pos 2
1386 #define	reg_cfoe_ifoe_sign_corr_len 1
1387 #define	reg_cfoe_ifoe_sign_corr_lsb 0
1388 #define xd_r_cfoe_fot_LF_output_7_0	0xA218
1389 #define	cfoe_fot_LF_output_7_0_pos 0
1390 #define	cfoe_fot_LF_output_7_0_len 8
1391 #define	cfoe_fot_LF_output_7_0_lsb 0
1392 #define xd_r_cfoe_fot_LF_output_15_8	0xA219
1393 #define	cfoe_fot_LF_output_15_8_pos 0
1394 #define	cfoe_fot_LF_output_15_8_len 8
1395 #define	cfoe_fot_LF_output_15_8_lsb 8
1396 #define xd_r_cfoe_ifo_metric_7_0	0xA21A
1397 #define	cfoe_ifo_metric_7_0_pos 0
1398 #define	cfoe_ifo_metric_7_0_len 8
1399 #define	cfoe_ifo_metric_7_0_lsb 0
1400 #define xd_r_cfoe_ifo_metric_15_8	0xA21B
1401 #define	cfoe_ifo_metric_15_8_pos 0
1402 #define	cfoe_ifo_metric_15_8_len 8
1403 #define	cfoe_ifo_metric_15_8_lsb 8
1404 #define xd_r_cfoe_ifo_metric_23_16	0xA21C
1405 #define	cfoe_ifo_metric_23_16_pos 0
1406 #define	cfoe_ifo_metric_23_16_len 8
1407 #define	cfoe_ifo_metric_23_16_lsb 16
1408 #define xd_p_ste_Nu	0xA220
1409 #define	ste_Nu_pos 0
1410 #define	ste_Nu_len 2
1411 #define	ste_Nu_lsb 0
1412 #define xd_p_ste_GI	0xA220
1413 #define	ste_GI_pos 2
1414 #define	ste_GI_len 3
1415 #define	ste_GI_lsb 0
1416 #define xd_p_ste_symbol_num	0xA221
1417 #define	ste_symbol_num_pos 0
1418 #define	ste_symbol_num_len 2
1419 #define	ste_symbol_num_lsb 0
1420 #define xd_p_ste_sample_num	0xA221
1421 #define	ste_sample_num_pos 2
1422 #define	ste_sample_num_len 2
1423 #define	ste_sample_num_lsb 0
1424 #define xd_p_reg_ste_buf_en	0xA221
1425 #define	reg_ste_buf_en_pos 7
1426 #define	reg_ste_buf_en_len 1
1427 #define	reg_ste_buf_en_lsb 0
1428 #define xd_p_ste_FFT_offset_7_0	0xA222
1429 #define	ste_FFT_offset_7_0_pos 0
1430 #define	ste_FFT_offset_7_0_len 8
1431 #define	ste_FFT_offset_7_0_lsb 0
1432 #define xd_p_ste_FFT_offset_11_8	0xA223
1433 #define	ste_FFT_offset_11_8_pos 0
1434 #define	ste_FFT_offset_11_8_len 4
1435 #define	ste_FFT_offset_11_8_lsb 8
1436 #define xd_p_reg_ste_tstmod	0xA223
1437 #define	reg_ste_tstmod_pos 5
1438 #define	reg_ste_tstmod_len 1
1439 #define	reg_ste_tstmod_lsb 0
1440 #define xd_p_ste_adv_start_7_0	0xA224
1441 #define	ste_adv_start_7_0_pos 0
1442 #define	ste_adv_start_7_0_len 8
1443 #define	ste_adv_start_7_0_lsb 0
1444 #define xd_p_ste_adv_start_10_8	0xA225
1445 #define	ste_adv_start_10_8_pos 0
1446 #define	ste_adv_start_10_8_len 3
1447 #define	ste_adv_start_10_8_lsb 8
1448 #define xd_p_ste_adv_stop	0xA226
1449 #define	ste_adv_stop_pos 0
1450 #define	ste_adv_stop_len 8
1451 #define	ste_adv_stop_lsb 0
1452 #define xd_r_ste_P_value_7_0	0xA228
1453 #define	ste_P_value_7_0_pos 0
1454 #define	ste_P_value_7_0_len 8
1455 #define	ste_P_value_7_0_lsb 0
1456 #define xd_r_ste_P_value_10_8	0xA229
1457 #define	ste_P_value_10_8_pos 0
1458 #define	ste_P_value_10_8_len 3
1459 #define	ste_P_value_10_8_lsb 8
1460 #define xd_r_ste_M_value_7_0	0xA22A
1461 #define	ste_M_value_7_0_pos 0
1462 #define	ste_M_value_7_0_len 8
1463 #define	ste_M_value_7_0_lsb 0
1464 #define xd_r_ste_M_value_10_8	0xA22B
1465 #define	ste_M_value_10_8_pos 0
1466 #define	ste_M_value_10_8_len 3
1467 #define	ste_M_value_10_8_lsb 8
1468 #define xd_r_ste_H1	0xA22C
1469 #define	ste_H1_pos 0
1470 #define	ste_H1_len 7
1471 #define	ste_H1_lsb 0
1472 #define xd_r_ste_H2	0xA22D
1473 #define	ste_H2_pos 0
1474 #define	ste_H2_len 7
1475 #define	ste_H2_lsb 0
1476 #define xd_r_ste_H3	0xA22E
1477 #define	ste_H3_pos 0
1478 #define	ste_H3_len 7
1479 #define	ste_H3_lsb 0
1480 #define xd_r_ste_H4	0xA22F
1481 #define	ste_H4_pos 0
1482 #define	ste_H4_len 7
1483 #define	ste_H4_lsb 0
1484 #define xd_r_ste_Corr_value_I_7_0	0xA230
1485 #define	ste_Corr_value_I_7_0_pos 0
1486 #define	ste_Corr_value_I_7_0_len 8
1487 #define	ste_Corr_value_I_7_0_lsb 0
1488 #define xd_r_ste_Corr_value_I_15_8	0xA231
1489 #define	ste_Corr_value_I_15_8_pos 0
1490 #define	ste_Corr_value_I_15_8_len 8
1491 #define	ste_Corr_value_I_15_8_lsb 8
1492 #define xd_r_ste_Corr_value_I_23_16	0xA232
1493 #define	ste_Corr_value_I_23_16_pos 0
1494 #define	ste_Corr_value_I_23_16_len 8
1495 #define	ste_Corr_value_I_23_16_lsb 16
1496 #define xd_r_ste_Corr_value_I_27_24	0xA233
1497 #define	ste_Corr_value_I_27_24_pos 0
1498 #define	ste_Corr_value_I_27_24_len 4
1499 #define	ste_Corr_value_I_27_24_lsb 24
1500 #define xd_r_ste_Corr_value_Q_7_0	0xA234
1501 #define	ste_Corr_value_Q_7_0_pos 0
1502 #define	ste_Corr_value_Q_7_0_len 8
1503 #define	ste_Corr_value_Q_7_0_lsb 0
1504 #define xd_r_ste_Corr_value_Q_15_8	0xA235
1505 #define	ste_Corr_value_Q_15_8_pos 0
1506 #define	ste_Corr_value_Q_15_8_len 8
1507 #define	ste_Corr_value_Q_15_8_lsb 8
1508 #define xd_r_ste_Corr_value_Q_23_16	0xA236
1509 #define	ste_Corr_value_Q_23_16_pos 0
1510 #define	ste_Corr_value_Q_23_16_len 8
1511 #define	ste_Corr_value_Q_23_16_lsb 16
1512 #define xd_r_ste_Corr_value_Q_27_24	0xA237
1513 #define	ste_Corr_value_Q_27_24_pos 0
1514 #define	ste_Corr_value_Q_27_24_len 4
1515 #define	ste_Corr_value_Q_27_24_lsb 24
1516 #define xd_r_ste_J_num_7_0	0xA238
1517 #define	ste_J_num_7_0_pos 0
1518 #define	ste_J_num_7_0_len 8
1519 #define	ste_J_num_7_0_lsb 0
1520 #define xd_r_ste_J_num_15_8	0xA239
1521 #define	ste_J_num_15_8_pos 0
1522 #define	ste_J_num_15_8_len 8
1523 #define	ste_J_num_15_8_lsb 8
1524 #define xd_r_ste_J_num_23_16	0xA23A
1525 #define	ste_J_num_23_16_pos 0
1526 #define	ste_J_num_23_16_len 8
1527 #define	ste_J_num_23_16_lsb 16
1528 #define xd_r_ste_J_num_31_24	0xA23B
1529 #define	ste_J_num_31_24_pos 0
1530 #define	ste_J_num_31_24_len 8
1531 #define	ste_J_num_31_24_lsb 24
1532 #define xd_r_ste_J_den_7_0	0xA23C
1533 #define	ste_J_den_7_0_pos 0
1534 #define	ste_J_den_7_0_len 8
1535 #define	ste_J_den_7_0_lsb 0
1536 #define xd_r_ste_J_den_15_8	0xA23D
1537 #define	ste_J_den_15_8_pos 0
1538 #define	ste_J_den_15_8_len 8
1539 #define	ste_J_den_15_8_lsb 8
1540 #define xd_r_ste_J_den_18_16	0xA23E
1541 #define	ste_J_den_18_16_pos 0
1542 #define	ste_J_den_18_16_len 3
1543 #define	ste_J_den_18_16_lsb 16
1544 #define xd_r_ste_Beacon_Indicator	0xA23E
1545 #define	ste_Beacon_Indicator_pos 4
1546 #define	ste_Beacon_Indicator_len 1
1547 #define	ste_Beacon_Indicator_lsb 0
1548 #define xd_r_tpsd_Frame_Num	0xA250
1549 #define	tpsd_Frame_Num_pos 0
1550 #define	tpsd_Frame_Num_len 2
1551 #define	tpsd_Frame_Num_lsb 0
1552 #define xd_r_tpsd_Constel	0xA250
1553 #define	tpsd_Constel_pos 2
1554 #define	tpsd_Constel_len 2
1555 #define	tpsd_Constel_lsb 0
1556 #define xd_r_tpsd_GI	0xA250
1557 #define	tpsd_GI_pos 4
1558 #define	tpsd_GI_len 2
1559 #define	tpsd_GI_lsb 0
1560 #define xd_r_tpsd_Mode	0xA250
1561 #define	tpsd_Mode_pos 6
1562 #define	tpsd_Mode_len 2
1563 #define	tpsd_Mode_lsb 0
1564 #define xd_r_tpsd_CR_HP	0xA251
1565 #define	tpsd_CR_HP_pos 0
1566 #define	tpsd_CR_HP_len 3
1567 #define	tpsd_CR_HP_lsb 0
1568 #define xd_r_tpsd_CR_LP	0xA251
1569 #define	tpsd_CR_LP_pos 3
1570 #define	tpsd_CR_LP_len 3
1571 #define	tpsd_CR_LP_lsb 0
1572 #define xd_r_tpsd_Hie	0xA252
1573 #define	tpsd_Hie_pos 0
1574 #define	tpsd_Hie_len 3
1575 #define	tpsd_Hie_lsb 0
1576 #define xd_r_tpsd_Res_Bits	0xA252
1577 #define	tpsd_Res_Bits_pos 3
1578 #define	tpsd_Res_Bits_len 5
1579 #define	tpsd_Res_Bits_lsb 0
1580 #define xd_r_tpsd_Res_Bits_0	0xA253
1581 #define	tpsd_Res_Bits_0_pos 0
1582 #define	tpsd_Res_Bits_0_len 1
1583 #define	tpsd_Res_Bits_0_lsb 0
1584 #define xd_r_tpsd_LengthInd	0xA253
1585 #define	tpsd_LengthInd_pos 1
1586 #define	tpsd_LengthInd_len 6
1587 #define	tpsd_LengthInd_lsb 0
1588 #define xd_r_tpsd_Cell_Id_7_0	0xA254
1589 #define	tpsd_Cell_Id_7_0_pos 0
1590 #define	tpsd_Cell_Id_7_0_len 8
1591 #define	tpsd_Cell_Id_7_0_lsb 0
1592 #define xd_r_tpsd_Cell_Id_15_8	0xA255
1593 #define	tpsd_Cell_Id_15_8_pos 0
1594 #define	tpsd_Cell_Id_15_8_len 8
1595 #define	tpsd_Cell_Id_15_8_lsb 0
1596 #define xd_p_reg_fft_mask_tone0_7_0	0xA260
1597 #define	reg_fft_mask_tone0_7_0_pos 0
1598 #define	reg_fft_mask_tone0_7_0_len 8
1599 #define	reg_fft_mask_tone0_7_0_lsb 0
1600 #define xd_p_reg_fft_mask_tone0_12_8	0xA261
1601 #define	reg_fft_mask_tone0_12_8_pos 0
1602 #define	reg_fft_mask_tone0_12_8_len 5
1603 #define	reg_fft_mask_tone0_12_8_lsb 8
1604 #define xd_p_reg_fft_mask_tone1_7_0	0xA262
1605 #define	reg_fft_mask_tone1_7_0_pos 0
1606 #define	reg_fft_mask_tone1_7_0_len 8
1607 #define	reg_fft_mask_tone1_7_0_lsb 0
1608 #define xd_p_reg_fft_mask_tone1_12_8	0xA263
1609 #define	reg_fft_mask_tone1_12_8_pos 0
1610 #define	reg_fft_mask_tone1_12_8_len 5
1611 #define	reg_fft_mask_tone1_12_8_lsb 8
1612 #define xd_p_reg_fft_mask_tone2_7_0	0xA264
1613 #define	reg_fft_mask_tone2_7_0_pos 0
1614 #define	reg_fft_mask_tone2_7_0_len 8
1615 #define	reg_fft_mask_tone2_7_0_lsb 0
1616 #define xd_p_reg_fft_mask_tone2_12_8	0xA265
1617 #define	reg_fft_mask_tone2_12_8_pos 0
1618 #define	reg_fft_mask_tone2_12_8_len 5
1619 #define	reg_fft_mask_tone2_12_8_lsb 8
1620 #define xd_p_reg_fft_mask_tone3_7_0	0xA266
1621 #define	reg_fft_mask_tone3_7_0_pos 0
1622 #define	reg_fft_mask_tone3_7_0_len 8
1623 #define	reg_fft_mask_tone3_7_0_lsb 0
1624 #define xd_p_reg_fft_mask_tone3_12_8	0xA267
1625 #define	reg_fft_mask_tone3_12_8_pos 0
1626 #define	reg_fft_mask_tone3_12_8_len 5
1627 #define	reg_fft_mask_tone3_12_8_lsb 8
1628 #define xd_p_reg_fft_mask_from0_7_0	0xA268
1629 #define	reg_fft_mask_from0_7_0_pos 0
1630 #define	reg_fft_mask_from0_7_0_len 8
1631 #define	reg_fft_mask_from0_7_0_lsb 0
1632 #define xd_p_reg_fft_mask_from0_12_8	0xA269
1633 #define	reg_fft_mask_from0_12_8_pos 0
1634 #define	reg_fft_mask_from0_12_8_len 5
1635 #define	reg_fft_mask_from0_12_8_lsb 8
1636 #define xd_p_reg_fft_mask_to0_7_0	0xA26A
1637 #define	reg_fft_mask_to0_7_0_pos 0
1638 #define	reg_fft_mask_to0_7_0_len 8
1639 #define	reg_fft_mask_to0_7_0_lsb 0
1640 #define xd_p_reg_fft_mask_to0_12_8	0xA26B
1641 #define	reg_fft_mask_to0_12_8_pos 0
1642 #define	reg_fft_mask_to0_12_8_len 5
1643 #define	reg_fft_mask_to0_12_8_lsb 8
1644 #define xd_p_reg_fft_mask_from1_7_0	0xA26C
1645 #define	reg_fft_mask_from1_7_0_pos 0
1646 #define	reg_fft_mask_from1_7_0_len 8
1647 #define	reg_fft_mask_from1_7_0_lsb 0
1648 #define xd_p_reg_fft_mask_from1_12_8	0xA26D
1649 #define	reg_fft_mask_from1_12_8_pos 0
1650 #define	reg_fft_mask_from1_12_8_len 5
1651 #define	reg_fft_mask_from1_12_8_lsb 8
1652 #define xd_p_reg_fft_mask_to1_7_0	0xA26E
1653 #define	reg_fft_mask_to1_7_0_pos 0
1654 #define	reg_fft_mask_to1_7_0_len 8
1655 #define	reg_fft_mask_to1_7_0_lsb 0
1656 #define xd_p_reg_fft_mask_to1_12_8	0xA26F
1657 #define	reg_fft_mask_to1_12_8_pos 0
1658 #define	reg_fft_mask_to1_12_8_len 5
1659 #define	reg_fft_mask_to1_12_8_lsb 8
1660 #define xd_p_reg_cge_idx0_7_0	0xA280
1661 #define	reg_cge_idx0_7_0_pos 0
1662 #define	reg_cge_idx0_7_0_len 8
1663 #define	reg_cge_idx0_7_0_lsb 0
1664 #define xd_p_reg_cge_idx0_12_8	0xA281
1665 #define	reg_cge_idx0_12_8_pos 0
1666 #define	reg_cge_idx0_12_8_len 5
1667 #define	reg_cge_idx0_12_8_lsb 8
1668 #define xd_p_reg_cge_idx1_7_0	0xA282
1669 #define	reg_cge_idx1_7_0_pos 0
1670 #define	reg_cge_idx1_7_0_len 8
1671 #define	reg_cge_idx1_7_0_lsb 0
1672 #define xd_p_reg_cge_idx1_12_8	0xA283
1673 #define	reg_cge_idx1_12_8_pos 0
1674 #define	reg_cge_idx1_12_8_len 5
1675 #define	reg_cge_idx1_12_8_lsb 8
1676 #define xd_p_reg_cge_idx2_7_0	0xA284
1677 #define	reg_cge_idx2_7_0_pos 0
1678 #define	reg_cge_idx2_7_0_len 8
1679 #define	reg_cge_idx2_7_0_lsb 0
1680 #define xd_p_reg_cge_idx2_12_8	0xA285
1681 #define	reg_cge_idx2_12_8_pos 0
1682 #define	reg_cge_idx2_12_8_len 5
1683 #define	reg_cge_idx2_12_8_lsb 8
1684 #define xd_p_reg_cge_idx3_7_0	0xA286
1685 #define	reg_cge_idx3_7_0_pos 0
1686 #define	reg_cge_idx3_7_0_len 8
1687 #define	reg_cge_idx3_7_0_lsb 0
1688 #define xd_p_reg_cge_idx3_12_8	0xA287
1689 #define	reg_cge_idx3_12_8_pos 0
1690 #define	reg_cge_idx3_12_8_len 5
1691 #define	reg_cge_idx3_12_8_lsb 8
1692 #define xd_p_reg_cge_idx4_7_0	0xA288
1693 #define	reg_cge_idx4_7_0_pos 0
1694 #define	reg_cge_idx4_7_0_len 8
1695 #define	reg_cge_idx4_7_0_lsb 0
1696 #define xd_p_reg_cge_idx4_12_8	0xA289
1697 #define	reg_cge_idx4_12_8_pos 0
1698 #define	reg_cge_idx4_12_8_len 5
1699 #define	reg_cge_idx4_12_8_lsb 8
1700 #define xd_p_reg_cge_idx5_7_0	0xA28A
1701 #define	reg_cge_idx5_7_0_pos 0
1702 #define	reg_cge_idx5_7_0_len 8
1703 #define	reg_cge_idx5_7_0_lsb 0
1704 #define xd_p_reg_cge_idx5_12_8	0xA28B
1705 #define	reg_cge_idx5_12_8_pos 0
1706 #define	reg_cge_idx5_12_8_len 5
1707 #define	reg_cge_idx5_12_8_lsb 8
1708 #define xd_p_reg_cge_idx6_7_0	0xA28C
1709 #define	reg_cge_idx6_7_0_pos 0
1710 #define	reg_cge_idx6_7_0_len 8
1711 #define	reg_cge_idx6_7_0_lsb 0
1712 #define xd_p_reg_cge_idx6_12_8	0xA28D
1713 #define	reg_cge_idx6_12_8_pos 0
1714 #define	reg_cge_idx6_12_8_len 5
1715 #define	reg_cge_idx6_12_8_lsb 8
1716 #define xd_p_reg_cge_idx7_7_0	0xA28E
1717 #define	reg_cge_idx7_7_0_pos 0
1718 #define	reg_cge_idx7_7_0_len 8
1719 #define	reg_cge_idx7_7_0_lsb 0
1720 #define xd_p_reg_cge_idx7_12_8	0xA28F
1721 #define	reg_cge_idx7_12_8_pos 0
1722 #define	reg_cge_idx7_12_8_len 5
1723 #define	reg_cge_idx7_12_8_lsb 8
1724 #define xd_p_reg_cge_idx8_7_0	0xA290
1725 #define	reg_cge_idx8_7_0_pos 0
1726 #define	reg_cge_idx8_7_0_len 8
1727 #define	reg_cge_idx8_7_0_lsb 0
1728 #define xd_p_reg_cge_idx8_12_8	0xA291
1729 #define	reg_cge_idx8_12_8_pos 0
1730 #define	reg_cge_idx8_12_8_len 5
1731 #define	reg_cge_idx8_12_8_lsb 8
1732 #define xd_p_reg_cge_idx9_7_0	0xA292
1733 #define	reg_cge_idx9_7_0_pos 0
1734 #define	reg_cge_idx9_7_0_len 8
1735 #define	reg_cge_idx9_7_0_lsb 0
1736 #define xd_p_reg_cge_idx9_12_8	0xA293
1737 #define	reg_cge_idx9_12_8_pos 0
1738 #define	reg_cge_idx9_12_8_len 5
1739 #define	reg_cge_idx9_12_8_lsb 8
1740 #define xd_p_reg_cge_idx10_7_0	0xA294
1741 #define	reg_cge_idx10_7_0_pos 0
1742 #define	reg_cge_idx10_7_0_len 8
1743 #define	reg_cge_idx10_7_0_lsb 0
1744 #define xd_p_reg_cge_idx10_12_8	0xA295
1745 #define	reg_cge_idx10_12_8_pos 0
1746 #define	reg_cge_idx10_12_8_len 5
1747 #define	reg_cge_idx10_12_8_lsb 8
1748 #define xd_p_reg_cge_idx11_7_0	0xA296
1749 #define	reg_cge_idx11_7_0_pos 0
1750 #define	reg_cge_idx11_7_0_len 8
1751 #define	reg_cge_idx11_7_0_lsb 0
1752 #define xd_p_reg_cge_idx11_12_8	0xA297
1753 #define	reg_cge_idx11_12_8_pos 0
1754 #define	reg_cge_idx11_12_8_len 5
1755 #define	reg_cge_idx11_12_8_lsb 8
1756 #define xd_p_reg_cge_idx12_7_0	0xA298
1757 #define	reg_cge_idx12_7_0_pos 0
1758 #define	reg_cge_idx12_7_0_len 8
1759 #define	reg_cge_idx12_7_0_lsb 0
1760 #define xd_p_reg_cge_idx12_12_8	0xA299
1761 #define	reg_cge_idx12_12_8_pos 0
1762 #define	reg_cge_idx12_12_8_len 5
1763 #define	reg_cge_idx12_12_8_lsb 8
1764 #define xd_p_reg_cge_idx13_7_0	0xA29A
1765 #define	reg_cge_idx13_7_0_pos 0
1766 #define	reg_cge_idx13_7_0_len 8
1767 #define	reg_cge_idx13_7_0_lsb 0
1768 #define xd_p_reg_cge_idx13_12_8	0xA29B
1769 #define	reg_cge_idx13_12_8_pos 0
1770 #define	reg_cge_idx13_12_8_len 5
1771 #define	reg_cge_idx13_12_8_lsb 8
1772 #define xd_p_reg_cge_idx14_7_0	0xA29C
1773 #define	reg_cge_idx14_7_0_pos 0
1774 #define	reg_cge_idx14_7_0_len 8
1775 #define	reg_cge_idx14_7_0_lsb 0
1776 #define xd_p_reg_cge_idx14_12_8	0xA29D
1777 #define	reg_cge_idx14_12_8_pos 0
1778 #define	reg_cge_idx14_12_8_len 5
1779 #define	reg_cge_idx14_12_8_lsb 8
1780 #define xd_p_reg_cge_idx15_7_0	0xA29E
1781 #define	reg_cge_idx15_7_0_pos 0
1782 #define	reg_cge_idx15_7_0_len 8
1783 #define	reg_cge_idx15_7_0_lsb 0
1784 #define xd_p_reg_cge_idx15_12_8	0xA29F
1785 #define	reg_cge_idx15_12_8_pos 0
1786 #define	reg_cge_idx15_12_8_len 5
1787 #define	reg_cge_idx15_12_8_lsb 8
1788 #define xd_r_reg_fft_crc	0xA2A8
1789 #define	reg_fft_crc_pos 0
1790 #define	reg_fft_crc_len 8
1791 #define	reg_fft_crc_lsb 0
1792 #define xd_p_fd_fft_shift_max	0xA2A9
1793 #define	fd_fft_shift_max_pos 0
1794 #define	fd_fft_shift_max_len 4
1795 #define	fd_fft_shift_max_lsb 0
1796 #define xd_r_fd_fft_shift	0xA2A9
1797 #define	fd_fft_shift_pos 4
1798 #define	fd_fft_shift_len 4
1799 #define	fd_fft_shift_lsb 0
1800 #define xd_r_fd_fft_frame_num	0xA2AA
1801 #define	fd_fft_frame_num_pos 0
1802 #define	fd_fft_frame_num_len 2
1803 #define	fd_fft_frame_num_lsb 0
1804 #define xd_r_fd_fft_symbol_count	0xA2AB
1805 #define	fd_fft_symbol_count_pos 0
1806 #define	fd_fft_symbol_count_len 7
1807 #define	fd_fft_symbol_count_lsb 0
1808 #define xd_r_reg_fft_idx_max_7_0	0xA2AC
1809 #define	reg_fft_idx_max_7_0_pos 0
1810 #define	reg_fft_idx_max_7_0_len 8
1811 #define	reg_fft_idx_max_7_0_lsb 0
1812 #define xd_r_reg_fft_idx_max_12_8	0xA2AD
1813 #define	reg_fft_idx_max_12_8_pos 0
1814 #define	reg_fft_idx_max_12_8_len 5
1815 #define	reg_fft_idx_max_12_8_lsb 8
1816 #define xd_p_reg_cge_program	0xA2AE
1817 #define	reg_cge_program_pos 0
1818 #define	reg_cge_program_len 1
1819 #define	reg_cge_program_lsb 0
1820 #define xd_p_reg_cge_fixed	0xA2AE
1821 #define	reg_cge_fixed_pos 1
1822 #define	reg_cge_fixed_len 1
1823 #define	reg_cge_fixed_lsb 0
1824 #define xd_p_reg_fft_rotate_en	0xA2AE
1825 #define	reg_fft_rotate_en_pos 2
1826 #define	reg_fft_rotate_en_len 1
1827 #define	reg_fft_rotate_en_lsb 0
1828 #define xd_p_reg_fft_rotate_base_4_0	0xA2AE
1829 #define	reg_fft_rotate_base_4_0_pos 3
1830 #define	reg_fft_rotate_base_4_0_len 5
1831 #define	reg_fft_rotate_base_4_0_lsb 0
1832 #define xd_p_reg_fft_rotate_base_12_5	0xA2AF
1833 #define	reg_fft_rotate_base_12_5_pos 0
1834 #define	reg_fft_rotate_base_12_5_len 8
1835 #define	reg_fft_rotate_base_12_5_lsb 5
1836 #define xd_p_reg_gp_trigger_fd	0xA2B8
1837 #define	reg_gp_trigger_fd_pos 0
1838 #define	reg_gp_trigger_fd_len 1
1839 #define	reg_gp_trigger_fd_lsb 0
1840 #define xd_p_reg_trigger_sel_fd	0xA2B8
1841 #define	reg_trigger_sel_fd_pos 1
1842 #define	reg_trigger_sel_fd_len 2
1843 #define	reg_trigger_sel_fd_lsb 0
1844 #define xd_p_reg_trigger_module_sel_fd	0xA2B9
1845 #define	reg_trigger_module_sel_fd_pos 0
1846 #define	reg_trigger_module_sel_fd_len 6
1847 #define	reg_trigger_module_sel_fd_lsb 0
1848 #define xd_p_reg_trigger_set_sel_fd	0xA2BA
1849 #define	reg_trigger_set_sel_fd_pos 0
1850 #define	reg_trigger_set_sel_fd_len 6
1851 #define	reg_trigger_set_sel_fd_lsb 0
1852 #define xd_p_reg_fd_noname_7_0	0xA2BC
1853 #define	reg_fd_noname_7_0_pos 0
1854 #define	reg_fd_noname_7_0_len 8
1855 #define	reg_fd_noname_7_0_lsb 0
1856 #define xd_p_reg_fd_noname_15_8	0xA2BD
1857 #define	reg_fd_noname_15_8_pos 0
1858 #define	reg_fd_noname_15_8_len 8
1859 #define	reg_fd_noname_15_8_lsb 8
1860 #define xd_p_reg_fd_noname_23_16	0xA2BE
1861 #define	reg_fd_noname_23_16_pos 0
1862 #define	reg_fd_noname_23_16_len 8
1863 #define	reg_fd_noname_23_16_lsb 16
1864 #define xd_p_reg_fd_noname_31_24	0xA2BF
1865 #define	reg_fd_noname_31_24_pos 0
1866 #define	reg_fd_noname_31_24_len 8
1867 #define	reg_fd_noname_31_24_lsb 24
1868 #define xd_r_fd_fpcc_cp_corr_signn	0xA2C0
1869 #define	fd_fpcc_cp_corr_signn_pos 0
1870 #define	fd_fpcc_cp_corr_signn_len 8
1871 #define	fd_fpcc_cp_corr_signn_lsb 0
1872 #define xd_p_reg_feq_s1	0xA2C1
1873 #define	reg_feq_s1_pos 0
1874 #define	reg_feq_s1_len 5
1875 #define	reg_feq_s1_lsb 0
1876 #define xd_p_fd_fpcc_cp_corr_tone_th	0xA2C2
1877 #define	fd_fpcc_cp_corr_tone_th_pos 0
1878 #define	fd_fpcc_cp_corr_tone_th_len 6
1879 #define	fd_fpcc_cp_corr_tone_th_lsb 0
1880 #define xd_p_fd_fpcc_cp_corr_symbol_log_th	0xA2C3
1881 #define	fd_fpcc_cp_corr_symbol_log_th_pos 0
1882 #define	fd_fpcc_cp_corr_symbol_log_th_len 4
1883 #define	fd_fpcc_cp_corr_symbol_log_th_lsb 0
1884 #define xd_p_fd_fpcc_cp_corr_int	0xA2C4
1885 #define	fd_fpcc_cp_corr_int_pos 0
1886 #define	fd_fpcc_cp_corr_int_len 1
1887 #define	fd_fpcc_cp_corr_int_lsb 0
1888 #define xd_p_reg_sfoe_ns_7_0	0xA320
1889 #define	reg_sfoe_ns_7_0_pos 0
1890 #define	reg_sfoe_ns_7_0_len 8
1891 #define	reg_sfoe_ns_7_0_lsb 0
1892 #define xd_p_reg_sfoe_ns_14_8	0xA321
1893 #define	reg_sfoe_ns_14_8_pos 0
1894 #define	reg_sfoe_ns_14_8_len 7
1895 #define	reg_sfoe_ns_14_8_lsb 8
1896 #define xd_p_reg_sfoe_c1_7_0	0xA322
1897 #define	reg_sfoe_c1_7_0_pos 0
1898 #define	reg_sfoe_c1_7_0_len 8
1899 #define	reg_sfoe_c1_7_0_lsb 0
1900 #define xd_p_reg_sfoe_c1_15_8	0xA323
1901 #define	reg_sfoe_c1_15_8_pos 0
1902 #define	reg_sfoe_c1_15_8_len 8
1903 #define	reg_sfoe_c1_15_8_lsb 8
1904 #define xd_p_reg_sfoe_c1_17_16	0xA324
1905 #define	reg_sfoe_c1_17_16_pos 0
1906 #define	reg_sfoe_c1_17_16_len 2
1907 #define	reg_sfoe_c1_17_16_lsb 16
1908 #define xd_p_reg_sfoe_c2_7_0	0xA325
1909 #define	reg_sfoe_c2_7_0_pos 0
1910 #define	reg_sfoe_c2_7_0_len 8
1911 #define	reg_sfoe_c2_7_0_lsb 0
1912 #define xd_p_reg_sfoe_c2_15_8	0xA326
1913 #define	reg_sfoe_c2_15_8_pos 0
1914 #define	reg_sfoe_c2_15_8_len 8
1915 #define	reg_sfoe_c2_15_8_lsb 8
1916 #define xd_p_reg_sfoe_c2_17_16	0xA327
1917 #define	reg_sfoe_c2_17_16_pos 0
1918 #define	reg_sfoe_c2_17_16_len 2
1919 #define	reg_sfoe_c2_17_16_lsb 16
1920 #define xd_r_reg_sfoe_out_9_2	0xA328
1921 #define	reg_sfoe_out_9_2_pos 0
1922 #define	reg_sfoe_out_9_2_len 8
1923 #define	reg_sfoe_out_9_2_lsb 0
1924 #define xd_r_reg_sfoe_out_1_0	0xA329
1925 #define	reg_sfoe_out_1_0_pos 0
1926 #define	reg_sfoe_out_1_0_len 2
1927 #define	reg_sfoe_out_1_0_lsb 0
1928 #define xd_p_reg_sfoe_lm_counter_th	0xA32A
1929 #define	reg_sfoe_lm_counter_th_pos 0
1930 #define	reg_sfoe_lm_counter_th_len 4
1931 #define	reg_sfoe_lm_counter_th_lsb 0
1932 #define xd_p_reg_sfoe_convg_th	0xA32B
1933 #define	reg_sfoe_convg_th_pos 0
1934 #define	reg_sfoe_convg_th_len 8
1935 #define	reg_sfoe_convg_th_lsb 0
1936 #define xd_p_reg_sfoe_divg_th	0xA32C
1937 #define	reg_sfoe_divg_th_pos 0
1938 #define	reg_sfoe_divg_th_len 8
1939 #define	reg_sfoe_divg_th_lsb 0
1940 #define xd_p_fd_tpsd_en	0xA330
1941 #define	fd_tpsd_en_pos 0
1942 #define	fd_tpsd_en_len 1
1943 #define	fd_tpsd_en_lsb 0
1944 #define xd_p_fd_tpsd_dis	0xA330
1945 #define	fd_tpsd_dis_pos 1
1946 #define	fd_tpsd_dis_len 1
1947 #define	fd_tpsd_dis_lsb 0
1948 #define xd_p_fd_tpsd_rst	0xA330
1949 #define	fd_tpsd_rst_pos 2
1950 #define	fd_tpsd_rst_len 1
1951 #define	fd_tpsd_rst_lsb 0
1952 #define xd_p_fd_tpsd_lock	0xA330
1953 #define	fd_tpsd_lock_pos 3
1954 #define	fd_tpsd_lock_len 1
1955 #define	fd_tpsd_lock_lsb 0
1956 #define xd_r_fd_tpsd_s19	0xA330
1957 #define	fd_tpsd_s19_pos 4
1958 #define	fd_tpsd_s19_len 1
1959 #define	fd_tpsd_s19_lsb 0
1960 #define xd_r_fd_tpsd_s17	0xA330
1961 #define	fd_tpsd_s17_pos 5
1962 #define	fd_tpsd_s17_len 1
1963 #define	fd_tpsd_s17_lsb 0
1964 #define xd_p_fd_sfr_ste_en	0xA331
1965 #define	fd_sfr_ste_en_pos 0
1966 #define	fd_sfr_ste_en_len 1
1967 #define	fd_sfr_ste_en_lsb 0
1968 #define xd_p_fd_sfr_ste_dis	0xA331
1969 #define	fd_sfr_ste_dis_pos 1
1970 #define	fd_sfr_ste_dis_len 1
1971 #define	fd_sfr_ste_dis_lsb 0
1972 #define xd_p_fd_sfr_ste_rst	0xA331
1973 #define	fd_sfr_ste_rst_pos 2
1974 #define	fd_sfr_ste_rst_len 1
1975 #define	fd_sfr_ste_rst_lsb 0
1976 #define xd_p_fd_sfr_ste_mode	0xA331
1977 #define	fd_sfr_ste_mode_pos 3
1978 #define	fd_sfr_ste_mode_len 1
1979 #define	fd_sfr_ste_mode_lsb 0
1980 #define xd_p_fd_sfr_ste_done	0xA331
1981 #define	fd_sfr_ste_done_pos 4
1982 #define	fd_sfr_ste_done_len 1
1983 #define	fd_sfr_ste_done_lsb 0
1984 #define xd_p_reg_cfoe_ffoe_en	0xA332
1985 #define	reg_cfoe_ffoe_en_pos 0
1986 #define	reg_cfoe_ffoe_en_len 1
1987 #define	reg_cfoe_ffoe_en_lsb 0
1988 #define xd_p_reg_cfoe_ffoe_dis	0xA332
1989 #define	reg_cfoe_ffoe_dis_pos 1
1990 #define	reg_cfoe_ffoe_dis_len 1
1991 #define	reg_cfoe_ffoe_dis_lsb 0
1992 #define xd_p_reg_cfoe_ffoe_rst	0xA332
1993 #define	reg_cfoe_ffoe_rst_pos 2
1994 #define	reg_cfoe_ffoe_rst_len 1
1995 #define	reg_cfoe_ffoe_rst_lsb 0
1996 #define xd_p_reg_cfoe_ifoe_en	0xA332
1997 #define	reg_cfoe_ifoe_en_pos 3
1998 #define	reg_cfoe_ifoe_en_len 1
1999 #define	reg_cfoe_ifoe_en_lsb 0
2000 #define xd_p_reg_cfoe_ifoe_dis	0xA332
2001 #define	reg_cfoe_ifoe_dis_pos 4
2002 #define	reg_cfoe_ifoe_dis_len 1
2003 #define	reg_cfoe_ifoe_dis_lsb 0
2004 #define xd_p_reg_cfoe_ifoe_rst	0xA332
2005 #define	reg_cfoe_ifoe_rst_pos 5
2006 #define	reg_cfoe_ifoe_rst_len 1
2007 #define	reg_cfoe_ifoe_rst_lsb 0
2008 #define xd_p_reg_cfoe_fot_en	0xA332
2009 #define	reg_cfoe_fot_en_pos 6
2010 #define	reg_cfoe_fot_en_len 1
2011 #define	reg_cfoe_fot_en_lsb 0
2012 #define xd_p_reg_cfoe_fot_lm_en	0xA332
2013 #define	reg_cfoe_fot_lm_en_pos 7
2014 #define	reg_cfoe_fot_lm_en_len 1
2015 #define	reg_cfoe_fot_lm_en_lsb 0
2016 #define xd_p_reg_cfoe_fot_rst	0xA333
2017 #define	reg_cfoe_fot_rst_pos 0
2018 #define	reg_cfoe_fot_rst_len 1
2019 #define	reg_cfoe_fot_rst_lsb 0
2020 #define xd_r_fd_cfoe_ffoe_done	0xA333
2021 #define	fd_cfoe_ffoe_done_pos 1
2022 #define	fd_cfoe_ffoe_done_len 1
2023 #define	fd_cfoe_ffoe_done_lsb 0
2024 #define xd_p_fd_cfoe_metric_vld	0xA333
2025 #define	fd_cfoe_metric_vld_pos 2
2026 #define	fd_cfoe_metric_vld_len 1
2027 #define	fd_cfoe_metric_vld_lsb 0
2028 #define xd_p_reg_cfoe_ifod_vld	0xA333
2029 #define	reg_cfoe_ifod_vld_pos 3
2030 #define	reg_cfoe_ifod_vld_len 1
2031 #define	reg_cfoe_ifod_vld_lsb 0
2032 #define xd_r_fd_cfoe_ifoe_done	0xA333
2033 #define	fd_cfoe_ifoe_done_pos 4
2034 #define	fd_cfoe_ifoe_done_len 1
2035 #define	fd_cfoe_ifoe_done_lsb 0
2036 #define xd_r_fd_cfoe_fot_valid	0xA333
2037 #define	fd_cfoe_fot_valid_pos 5
2038 #define	fd_cfoe_fot_valid_len 1
2039 #define	fd_cfoe_fot_valid_lsb 0
2040 #define xd_p_reg_cfoe_divg_int	0xA333
2041 #define	reg_cfoe_divg_int_pos 6
2042 #define	reg_cfoe_divg_int_len 1
2043 #define	reg_cfoe_divg_int_lsb 0
2044 #define xd_r_reg_cfoe_divg_flag	0xA333
2045 #define	reg_cfoe_divg_flag_pos 7
2046 #define	reg_cfoe_divg_flag_len 1
2047 #define	reg_cfoe_divg_flag_lsb 0
2048 #define xd_p_reg_sfoe_en	0xA334
2049 #define	reg_sfoe_en_pos 0
2050 #define	reg_sfoe_en_len 1
2051 #define	reg_sfoe_en_lsb 0
2052 #define xd_p_reg_sfoe_dis	0xA334
2053 #define	reg_sfoe_dis_pos 1
2054 #define	reg_sfoe_dis_len 1
2055 #define	reg_sfoe_dis_lsb 0
2056 #define xd_p_reg_sfoe_rst	0xA334
2057 #define	reg_sfoe_rst_pos 2
2058 #define	reg_sfoe_rst_len 1
2059 #define	reg_sfoe_rst_lsb 0
2060 #define xd_p_reg_sfoe_vld_int	0xA334
2061 #define	reg_sfoe_vld_int_pos 3
2062 #define	reg_sfoe_vld_int_len 1
2063 #define	reg_sfoe_vld_int_lsb 0
2064 #define xd_p_reg_sfoe_lm_en	0xA334
2065 #define	reg_sfoe_lm_en_pos 4
2066 #define	reg_sfoe_lm_en_len 1
2067 #define	reg_sfoe_lm_en_lsb 0
2068 #define xd_p_reg_sfoe_divg_int	0xA334
2069 #define	reg_sfoe_divg_int_pos 5
2070 #define	reg_sfoe_divg_int_len 1
2071 #define	reg_sfoe_divg_int_lsb 0
2072 #define xd_r_reg_sfoe_divg_flag	0xA334
2073 #define	reg_sfoe_divg_flag_pos 6
2074 #define	reg_sfoe_divg_flag_len 1
2075 #define	reg_sfoe_divg_flag_lsb 0
2076 #define xd_p_reg_fft_rst	0xA335
2077 #define	reg_fft_rst_pos 0
2078 #define	reg_fft_rst_len 1
2079 #define	reg_fft_rst_lsb 0
2080 #define xd_p_reg_fft_fast_beacon	0xA335
2081 #define	reg_fft_fast_beacon_pos 1
2082 #define	reg_fft_fast_beacon_len 1
2083 #define	reg_fft_fast_beacon_lsb 0
2084 #define xd_p_reg_fft_fast_valid	0xA335
2085 #define	reg_fft_fast_valid_pos 2
2086 #define	reg_fft_fast_valid_len 1
2087 #define	reg_fft_fast_valid_lsb 0
2088 #define xd_p_reg_fft_mask_en	0xA335
2089 #define	reg_fft_mask_en_pos 3
2090 #define	reg_fft_mask_en_len 1
2091 #define	reg_fft_mask_en_lsb 0
2092 #define xd_p_reg_fft_crc_en	0xA335
2093 #define	reg_fft_crc_en_pos 4
2094 #define	reg_fft_crc_en_len 1
2095 #define	reg_fft_crc_en_lsb 0
2096 #define xd_p_reg_finr_en	0xA336
2097 #define	reg_finr_en_pos 0
2098 #define	reg_finr_en_len 1
2099 #define	reg_finr_en_lsb 0
2100 #define xd_p_fd_fste_en	0xA337
2101 #define	fd_fste_en_pos 1
2102 #define	fd_fste_en_len 1
2103 #define	fd_fste_en_lsb 0
2104 #define xd_p_fd_sqi_tps_level_shift	0xA338
2105 #define	fd_sqi_tps_level_shift_pos 0
2106 #define	fd_sqi_tps_level_shift_len 8
2107 #define	fd_sqi_tps_level_shift_lsb 0
2108 #define xd_p_fd_pilot_ma_len	0xA339
2109 #define	fd_pilot_ma_len_pos 0
2110 #define	fd_pilot_ma_len_len 6
2111 #define	fd_pilot_ma_len_lsb 0
2112 #define xd_p_fd_tps_ma_len	0xA33A
2113 #define	fd_tps_ma_len_pos 0
2114 #define	fd_tps_ma_len_len 6
2115 #define	fd_tps_ma_len_lsb 0
2116 #define xd_p_fd_sqi_s3	0xA33B
2117 #define	fd_sqi_s3_pos 0
2118 #define	fd_sqi_s3_len 8
2119 #define	fd_sqi_s3_lsb 0
2120 #define xd_p_fd_sqi_dummy_reg_0	0xA33C
2121 #define	fd_sqi_dummy_reg_0_pos 0
2122 #define	fd_sqi_dummy_reg_0_len 1
2123 #define	fd_sqi_dummy_reg_0_lsb 0
2124 #define xd_p_fd_sqi_debug_sel	0xA33C
2125 #define	fd_sqi_debug_sel_pos 1
2126 #define	fd_sqi_debug_sel_len 2
2127 #define	fd_sqi_debug_sel_lsb 0
2128 #define xd_p_fd_sqi_s2	0xA33C
2129 #define	fd_sqi_s2_pos 3
2130 #define	fd_sqi_s2_len 5
2131 #define	fd_sqi_s2_lsb 0
2132 #define xd_p_fd_sqi_dummy_reg_1	0xA33D
2133 #define	fd_sqi_dummy_reg_1_pos 0
2134 #define	fd_sqi_dummy_reg_1_len 1
2135 #define	fd_sqi_dummy_reg_1_lsb 0
2136 #define xd_p_fd_inr_ignore	0xA33D
2137 #define	fd_inr_ignore_pos 1
2138 #define	fd_inr_ignore_len 1
2139 #define	fd_inr_ignore_lsb 0
2140 #define xd_p_fd_pilot_ignore	0xA33D
2141 #define	fd_pilot_ignore_pos 2
2142 #define	fd_pilot_ignore_len 1
2143 #define	fd_pilot_ignore_lsb 0
2144 #define xd_p_fd_etps_ignore	0xA33D
2145 #define	fd_etps_ignore_pos 3
2146 #define	fd_etps_ignore_len 1
2147 #define	fd_etps_ignore_lsb 0
2148 #define xd_p_fd_sqi_s1	0xA33D
2149 #define	fd_sqi_s1_pos 4
2150 #define	fd_sqi_s1_len 4
2151 #define	fd_sqi_s1_lsb 0
2152 #define xd_p_reg_fste_ehw_7_0	0xA33E
2153 #define	reg_fste_ehw_7_0_pos 0
2154 #define	reg_fste_ehw_7_0_len 8
2155 #define	reg_fste_ehw_7_0_lsb 0
2156 #define xd_p_reg_fste_ehw_9_8	0xA33F
2157 #define	reg_fste_ehw_9_8_pos 0
2158 #define	reg_fste_ehw_9_8_len 2
2159 #define	reg_fste_ehw_9_8_lsb 8
2160 #define xd_p_reg_fste_i_adj_vld	0xA33F
2161 #define	reg_fste_i_adj_vld_pos 2
2162 #define	reg_fste_i_adj_vld_len 1
2163 #define	reg_fste_i_adj_vld_lsb 0
2164 #define xd_p_reg_fste_phase_ini_7_0	0xA340
2165 #define	reg_fste_phase_ini_7_0_pos 0
2166 #define	reg_fste_phase_ini_7_0_len 8
2167 #define	reg_fste_phase_ini_7_0_lsb 0
2168 #define xd_p_reg_fste_phase_ini_11_8	0xA341
2169 #define	reg_fste_phase_ini_11_8_pos 0
2170 #define	reg_fste_phase_ini_11_8_len 4
2171 #define	reg_fste_phase_ini_11_8_lsb 8
2172 #define xd_p_reg_fste_phase_inc_3_0	0xA341
2173 #define	reg_fste_phase_inc_3_0_pos 4
2174 #define	reg_fste_phase_inc_3_0_len 4
2175 #define	reg_fste_phase_inc_3_0_lsb 0
2176 #define xd_p_reg_fste_phase_inc_11_4	0xA342
2177 #define	reg_fste_phase_inc_11_4_pos 0
2178 #define	reg_fste_phase_inc_11_4_len 8
2179 #define	reg_fste_phase_inc_11_4_lsb 4
2180 #define xd_p_reg_fste_acum_cost_cnt_max	0xA343
2181 #define	reg_fste_acum_cost_cnt_max_pos 0
2182 #define	reg_fste_acum_cost_cnt_max_len 4
2183 #define	reg_fste_acum_cost_cnt_max_lsb 0
2184 #define xd_p_reg_fste_step_size_std	0xA343
2185 #define	reg_fste_step_size_std_pos 4
2186 #define	reg_fste_step_size_std_len 4
2187 #define	reg_fste_step_size_std_lsb 0
2188 #define xd_p_reg_fste_step_size_max	0xA344
2189 #define	reg_fste_step_size_max_pos 0
2190 #define	reg_fste_step_size_max_len 4
2191 #define	reg_fste_step_size_max_lsb 0
2192 #define xd_p_reg_fste_step_size_min	0xA344
2193 #define	reg_fste_step_size_min_pos 4
2194 #define	reg_fste_step_size_min_len 4
2195 #define	reg_fste_step_size_min_lsb 0
2196 #define xd_p_reg_fste_frac_step_size_7_0	0xA345
2197 #define	reg_fste_frac_step_size_7_0_pos 0
2198 #define	reg_fste_frac_step_size_7_0_len 8
2199 #define	reg_fste_frac_step_size_7_0_lsb 0
2200 #define xd_p_reg_fste_frac_step_size_15_8	0xA346
2201 #define	reg_fste_frac_step_size_15_8_pos 0
2202 #define	reg_fste_frac_step_size_15_8_len 8
2203 #define	reg_fste_frac_step_size_15_8_lsb 8
2204 #define xd_p_reg_fste_frac_step_size_19_16	0xA347
2205 #define	reg_fste_frac_step_size_19_16_pos 0
2206 #define	reg_fste_frac_step_size_19_16_len 4
2207 #define	reg_fste_frac_step_size_19_16_lsb 16
2208 #define xd_p_reg_fste_rpd_dir_cnt_max	0xA347
2209 #define	reg_fste_rpd_dir_cnt_max_pos 4
2210 #define	reg_fste_rpd_dir_cnt_max_len 4
2211 #define	reg_fste_rpd_dir_cnt_max_lsb 0
2212 #define xd_p_reg_fste_ehs	0xA348
2213 #define	reg_fste_ehs_pos 0
2214 #define	reg_fste_ehs_len 4
2215 #define	reg_fste_ehs_lsb 0
2216 #define xd_p_reg_fste_frac_cost_cnt_max_3_0	0xA348
2217 #define	reg_fste_frac_cost_cnt_max_3_0_pos 4
2218 #define	reg_fste_frac_cost_cnt_max_3_0_len 4
2219 #define	reg_fste_frac_cost_cnt_max_3_0_lsb 0
2220 #define xd_p_reg_fste_frac_cost_cnt_max_9_4	0xA349
2221 #define	reg_fste_frac_cost_cnt_max_9_4_pos 0
2222 #define	reg_fste_frac_cost_cnt_max_9_4_len 6
2223 #define	reg_fste_frac_cost_cnt_max_9_4_lsb 4
2224 #define xd_p_reg_fste_w0_7_0	0xA34A
2225 #define	reg_fste_w0_7_0_pos 0
2226 #define	reg_fste_w0_7_0_len 8
2227 #define	reg_fste_w0_7_0_lsb 0
2228 #define xd_p_reg_fste_w0_11_8	0xA34B
2229 #define	reg_fste_w0_11_8_pos 0
2230 #define	reg_fste_w0_11_8_len 4
2231 #define	reg_fste_w0_11_8_lsb 8
2232 #define xd_p_reg_fste_w1_3_0	0xA34B
2233 #define	reg_fste_w1_3_0_pos 4
2234 #define	reg_fste_w1_3_0_len 4
2235 #define	reg_fste_w1_3_0_lsb 0
2236 #define xd_p_reg_fste_w1_11_4	0xA34C
2237 #define	reg_fste_w1_11_4_pos 0
2238 #define	reg_fste_w1_11_4_len 8
2239 #define	reg_fste_w1_11_4_lsb 4
2240 #define xd_p_reg_fste_w2_7_0	0xA34D
2241 #define	reg_fste_w2_7_0_pos 0
2242 #define	reg_fste_w2_7_0_len 8
2243 #define	reg_fste_w2_7_0_lsb 0
2244 #define xd_p_reg_fste_w2_11_8	0xA34E
2245 #define	reg_fste_w2_11_8_pos 0
2246 #define	reg_fste_w2_11_8_len 4
2247 #define	reg_fste_w2_11_8_lsb 8
2248 #define xd_p_reg_fste_w3_3_0	0xA34E
2249 #define	reg_fste_w3_3_0_pos 4
2250 #define	reg_fste_w3_3_0_len 4
2251 #define	reg_fste_w3_3_0_lsb 0
2252 #define xd_p_reg_fste_w3_11_4	0xA34F
2253 #define	reg_fste_w3_11_4_pos 0
2254 #define	reg_fste_w3_11_4_len 8
2255 #define	reg_fste_w3_11_4_lsb 4
2256 #define xd_p_reg_fste_w4_7_0	0xA350
2257 #define	reg_fste_w4_7_0_pos 0
2258 #define	reg_fste_w4_7_0_len 8
2259 #define	reg_fste_w4_7_0_lsb 0
2260 #define xd_p_reg_fste_w4_11_8	0xA351
2261 #define	reg_fste_w4_11_8_pos 0
2262 #define	reg_fste_w4_11_8_len 4
2263 #define	reg_fste_w4_11_8_lsb 8
2264 #define xd_p_reg_fste_w5_3_0	0xA351
2265 #define	reg_fste_w5_3_0_pos 4
2266 #define	reg_fste_w5_3_0_len 4
2267 #define	reg_fste_w5_3_0_lsb 0
2268 #define xd_p_reg_fste_w5_11_4	0xA352
2269 #define	reg_fste_w5_11_4_pos 0
2270 #define	reg_fste_w5_11_4_len 8
2271 #define	reg_fste_w5_11_4_lsb 4
2272 #define xd_p_reg_fste_w6_7_0	0xA353
2273 #define	reg_fste_w6_7_0_pos 0
2274 #define	reg_fste_w6_7_0_len 8
2275 #define	reg_fste_w6_7_0_lsb 0
2276 #define xd_p_reg_fste_w6_11_8	0xA354
2277 #define	reg_fste_w6_11_8_pos 0
2278 #define	reg_fste_w6_11_8_len 4
2279 #define	reg_fste_w6_11_8_lsb 8
2280 #define xd_p_reg_fste_w7_3_0	0xA354
2281 #define	reg_fste_w7_3_0_pos 4
2282 #define	reg_fste_w7_3_0_len 4
2283 #define	reg_fste_w7_3_0_lsb 0
2284 #define xd_p_reg_fste_w7_11_4	0xA355
2285 #define	reg_fste_w7_11_4_pos 0
2286 #define	reg_fste_w7_11_4_len 8
2287 #define	reg_fste_w7_11_4_lsb 4
2288 #define xd_p_reg_fste_w8_7_0	0xA356
2289 #define	reg_fste_w8_7_0_pos 0
2290 #define	reg_fste_w8_7_0_len 8
2291 #define	reg_fste_w8_7_0_lsb 0
2292 #define xd_p_reg_fste_w8_11_8	0xA357
2293 #define	reg_fste_w8_11_8_pos 0
2294 #define	reg_fste_w8_11_8_len 4
2295 #define	reg_fste_w8_11_8_lsb 8
2296 #define xd_p_reg_fste_w9_3_0	0xA357
2297 #define	reg_fste_w9_3_0_pos 4
2298 #define	reg_fste_w9_3_0_len 4
2299 #define	reg_fste_w9_3_0_lsb 0
2300 #define xd_p_reg_fste_w9_11_4	0xA358
2301 #define	reg_fste_w9_11_4_pos 0
2302 #define	reg_fste_w9_11_4_len 8
2303 #define	reg_fste_w9_11_4_lsb 4
2304 #define xd_p_reg_fste_wa_7_0	0xA359
2305 #define	reg_fste_wa_7_0_pos 0
2306 #define	reg_fste_wa_7_0_len 8
2307 #define	reg_fste_wa_7_0_lsb 0
2308 #define xd_p_reg_fste_wa_11_8	0xA35A
2309 #define	reg_fste_wa_11_8_pos 0
2310 #define	reg_fste_wa_11_8_len 4
2311 #define	reg_fste_wa_11_8_lsb 8
2312 #define xd_p_reg_fste_wb_3_0	0xA35A
2313 #define	reg_fste_wb_3_0_pos 4
2314 #define	reg_fste_wb_3_0_len 4
2315 #define	reg_fste_wb_3_0_lsb 0
2316 #define xd_p_reg_fste_wb_11_4	0xA35B
2317 #define	reg_fste_wb_11_4_pos 0
2318 #define	reg_fste_wb_11_4_len 8
2319 #define	reg_fste_wb_11_4_lsb 4
2320 #define xd_r_fd_fste_i_adj	0xA35C
2321 #define	fd_fste_i_adj_pos 0
2322 #define	fd_fste_i_adj_len 5
2323 #define	fd_fste_i_adj_lsb 0
2324 #define xd_r_fd_fste_f_adj_7_0	0xA35D
2325 #define	fd_fste_f_adj_7_0_pos 0
2326 #define	fd_fste_f_adj_7_0_len 8
2327 #define	fd_fste_f_adj_7_0_lsb 0
2328 #define xd_r_fd_fste_f_adj_15_8	0xA35E
2329 #define	fd_fste_f_adj_15_8_pos 0
2330 #define	fd_fste_f_adj_15_8_len 8
2331 #define	fd_fste_f_adj_15_8_lsb 8
2332 #define xd_r_fd_fste_f_adj_19_16	0xA35F
2333 #define	fd_fste_f_adj_19_16_pos 0
2334 #define	fd_fste_f_adj_19_16_len 4
2335 #define	fd_fste_f_adj_19_16_lsb 16
2336 #define xd_p_reg_feq_Leak_Bypass	0xA366
2337 #define	reg_feq_Leak_Bypass_pos 0
2338 #define	reg_feq_Leak_Bypass_len 1
2339 #define	reg_feq_Leak_Bypass_lsb 0
2340 #define xd_p_reg_feq_Leak_Mneg1	0xA366
2341 #define	reg_feq_Leak_Mneg1_pos 1
2342 #define	reg_feq_Leak_Mneg1_len 3
2343 #define	reg_feq_Leak_Mneg1_lsb 0
2344 #define xd_p_reg_feq_Leak_B_ShiftQ	0xA366
2345 #define	reg_feq_Leak_B_ShiftQ_pos 4
2346 #define	reg_feq_Leak_B_ShiftQ_len 4
2347 #define	reg_feq_Leak_B_ShiftQ_lsb 0
2348 #define xd_p_reg_feq_Leak_B_Float0	0xA367
2349 #define	reg_feq_Leak_B_Float0_pos 0
2350 #define	reg_feq_Leak_B_Float0_len 8
2351 #define	reg_feq_Leak_B_Float0_lsb 0
2352 #define xd_p_reg_feq_Leak_B_Float1	0xA368
2353 #define	reg_feq_Leak_B_Float1_pos 0
2354 #define	reg_feq_Leak_B_Float1_len 8
2355 #define	reg_feq_Leak_B_Float1_lsb 0
2356 #define xd_p_reg_feq_Leak_B_Float2	0xA369
2357 #define	reg_feq_Leak_B_Float2_pos 0
2358 #define	reg_feq_Leak_B_Float2_len 8
2359 #define	reg_feq_Leak_B_Float2_lsb 0
2360 #define xd_p_reg_feq_Leak_B_Float3	0xA36A
2361 #define	reg_feq_Leak_B_Float3_pos 0
2362 #define	reg_feq_Leak_B_Float3_len 8
2363 #define	reg_feq_Leak_B_Float3_lsb 0
2364 #define xd_p_reg_feq_Leak_B_Float4	0xA36B
2365 #define	reg_feq_Leak_B_Float4_pos 0
2366 #define	reg_feq_Leak_B_Float4_len 8
2367 #define	reg_feq_Leak_B_Float4_lsb 0
2368 #define xd_p_reg_feq_Leak_B_Float5	0xA36C
2369 #define	reg_feq_Leak_B_Float5_pos 0
2370 #define	reg_feq_Leak_B_Float5_len 8
2371 #define	reg_feq_Leak_B_Float5_lsb 0
2372 #define xd_p_reg_feq_Leak_B_Float6	0xA36D
2373 #define	reg_feq_Leak_B_Float6_pos 0
2374 #define	reg_feq_Leak_B_Float6_len 8
2375 #define	reg_feq_Leak_B_Float6_lsb 0
2376 #define xd_p_reg_feq_Leak_B_Float7	0xA36E
2377 #define	reg_feq_Leak_B_Float7_pos 0
2378 #define	reg_feq_Leak_B_Float7_len 8
2379 #define	reg_feq_Leak_B_Float7_lsb 0
2380 #define xd_r_reg_feq_data_h2_7_0	0xA36F
2381 #define	reg_feq_data_h2_7_0_pos 0
2382 #define	reg_feq_data_h2_7_0_len 8
2383 #define	reg_feq_data_h2_7_0_lsb 0
2384 #define xd_r_reg_feq_data_h2_9_8	0xA370
2385 #define	reg_feq_data_h2_9_8_pos 0
2386 #define	reg_feq_data_h2_9_8_len 2
2387 #define	reg_feq_data_h2_9_8_lsb 8
2388 #define xd_p_reg_feq_leak_use_slice_tps	0xA371
2389 #define	reg_feq_leak_use_slice_tps_pos 0
2390 #define	reg_feq_leak_use_slice_tps_len 1
2391 #define	reg_feq_leak_use_slice_tps_lsb 0
2392 #define xd_p_reg_feq_read_update	0xA371
2393 #define	reg_feq_read_update_pos 1
2394 #define	reg_feq_read_update_len 1
2395 #define	reg_feq_read_update_lsb 0
2396 #define xd_p_reg_feq_data_vld	0xA371
2397 #define	reg_feq_data_vld_pos 2
2398 #define	reg_feq_data_vld_len 1
2399 #define	reg_feq_data_vld_lsb 0
2400 #define xd_p_reg_feq_tone_idx_4_0	0xA371
2401 #define	reg_feq_tone_idx_4_0_pos 3
2402 #define	reg_feq_tone_idx_4_0_len 5
2403 #define	reg_feq_tone_idx_4_0_lsb 0
2404 #define xd_p_reg_feq_tone_idx_12_5	0xA372
2405 #define	reg_feq_tone_idx_12_5_pos 0
2406 #define	reg_feq_tone_idx_12_5_len 8
2407 #define	reg_feq_tone_idx_12_5_lsb 5
2408 #define xd_r_reg_feq_data_re_7_0	0xA373
2409 #define	reg_feq_data_re_7_0_pos 0
2410 #define	reg_feq_data_re_7_0_len 8
2411 #define	reg_feq_data_re_7_0_lsb 0
2412 #define xd_r_reg_feq_data_re_10_8	0xA374
2413 #define	reg_feq_data_re_10_8_pos 0
2414 #define	reg_feq_data_re_10_8_len 3
2415 #define	reg_feq_data_re_10_8_lsb 8
2416 #define xd_r_reg_feq_data_im_7_0	0xA375
2417 #define	reg_feq_data_im_7_0_pos 0
2418 #define	reg_feq_data_im_7_0_len 8
2419 #define	reg_feq_data_im_7_0_lsb 0
2420 #define xd_r_reg_feq_data_im_10_8	0xA376
2421 #define	reg_feq_data_im_10_8_pos 0
2422 #define	reg_feq_data_im_10_8_len 3
2423 #define	reg_feq_data_im_10_8_lsb 8
2424 #define xd_r_reg_feq_y_re	0xA377
2425 #define	reg_feq_y_re_pos 0
2426 #define	reg_feq_y_re_len 8
2427 #define	reg_feq_y_re_lsb 0
2428 #define xd_r_reg_feq_y_im	0xA378
2429 #define	reg_feq_y_im_pos 0
2430 #define	reg_feq_y_im_len 8
2431 #define	reg_feq_y_im_lsb 0
2432 #define xd_r_reg_feq_h_re_7_0	0xA379
2433 #define	reg_feq_h_re_7_0_pos 0
2434 #define	reg_feq_h_re_7_0_len 8
2435 #define	reg_feq_h_re_7_0_lsb 0
2436 #define xd_r_reg_feq_h_re_8	0xA37A
2437 #define	reg_feq_h_re_8_pos 0
2438 #define	reg_feq_h_re_8_len 1
2439 #define	reg_feq_h_re_8_lsb 0
2440 #define xd_r_reg_feq_h_im_7_0	0xA37B
2441 #define	reg_feq_h_im_7_0_pos 0
2442 #define	reg_feq_h_im_7_0_len 8
2443 #define	reg_feq_h_im_7_0_lsb 0
2444 #define xd_r_reg_feq_h_im_8	0xA37C
2445 #define	reg_feq_h_im_8_pos 0
2446 #define	reg_feq_h_im_8_len 1
2447 #define	reg_feq_h_im_8_lsb 0
2448 #define xd_p_fec_super_frm_unit_7_0	0xA380
2449 #define	fec_super_frm_unit_7_0_pos 0
2450 #define	fec_super_frm_unit_7_0_len 8
2451 #define	fec_super_frm_unit_7_0_lsb 0
2452 #define xd_p_fec_super_frm_unit_15_8	0xA381
2453 #define	fec_super_frm_unit_15_8_pos 0
2454 #define	fec_super_frm_unit_15_8_len 8
2455 #define	fec_super_frm_unit_15_8_lsb 8
2456 #define xd_r_fec_vtb_err_bit_cnt_7_0	0xA382
2457 #define	fec_vtb_err_bit_cnt_7_0_pos 0
2458 #define	fec_vtb_err_bit_cnt_7_0_len 8
2459 #define	fec_vtb_err_bit_cnt_7_0_lsb 0
2460 #define xd_r_fec_vtb_err_bit_cnt_15_8	0xA383
2461 #define	fec_vtb_err_bit_cnt_15_8_pos 0
2462 #define	fec_vtb_err_bit_cnt_15_8_len 8
2463 #define	fec_vtb_err_bit_cnt_15_8_lsb 8
2464 #define xd_r_fec_vtb_err_bit_cnt_23_16	0xA384
2465 #define	fec_vtb_err_bit_cnt_23_16_pos 0
2466 #define	fec_vtb_err_bit_cnt_23_16_len 8
2467 #define	fec_vtb_err_bit_cnt_23_16_lsb 16
2468 #define xd_p_fec_rsd_packet_unit_7_0	0xA385
2469 #define	fec_rsd_packet_unit_7_0_pos 0
2470 #define	fec_rsd_packet_unit_7_0_len 8
2471 #define	fec_rsd_packet_unit_7_0_lsb 0
2472 #define xd_p_fec_rsd_packet_unit_15_8	0xA386
2473 #define	fec_rsd_packet_unit_15_8_pos 0
2474 #define	fec_rsd_packet_unit_15_8_len 8
2475 #define	fec_rsd_packet_unit_15_8_lsb 8
2476 #define xd_r_fec_rsd_bit_err_cnt_7_0	0xA387
2477 #define	fec_rsd_bit_err_cnt_7_0_pos 0
2478 #define	fec_rsd_bit_err_cnt_7_0_len 8
2479 #define	fec_rsd_bit_err_cnt_7_0_lsb 0
2480 #define xd_r_fec_rsd_bit_err_cnt_15_8	0xA388
2481 #define	fec_rsd_bit_err_cnt_15_8_pos 0
2482 #define	fec_rsd_bit_err_cnt_15_8_len 8
2483 #define	fec_rsd_bit_err_cnt_15_8_lsb 8
2484 #define xd_r_fec_rsd_bit_err_cnt_23_16	0xA389
2485 #define	fec_rsd_bit_err_cnt_23_16_pos 0
2486 #define	fec_rsd_bit_err_cnt_23_16_len 8
2487 #define	fec_rsd_bit_err_cnt_23_16_lsb 16
2488 #define xd_r_fec_rsd_abort_packet_cnt_7_0	0xA38A
2489 #define	fec_rsd_abort_packet_cnt_7_0_pos 0
2490 #define	fec_rsd_abort_packet_cnt_7_0_len 8
2491 #define	fec_rsd_abort_packet_cnt_7_0_lsb 0
2492 #define xd_r_fec_rsd_abort_packet_cnt_15_8	0xA38B
2493 #define	fec_rsd_abort_packet_cnt_15_8_pos 0
2494 #define	fec_rsd_abort_packet_cnt_15_8_len 8
2495 #define	fec_rsd_abort_packet_cnt_15_8_lsb 8
2496 #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0	0xA38C
2497 #define	fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
2498 #define	fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
2499 #define	fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
2500 #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8	0xA38D
2501 #define	fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
2502 #define	fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
2503 #define	fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
2504 #define xd_p_fec_RS_TH_1_7_0	0xA38E
2505 #define	fec_RS_TH_1_7_0_pos 0
2506 #define	fec_RS_TH_1_7_0_len 8
2507 #define	fec_RS_TH_1_7_0_lsb 0
2508 #define xd_p_fec_RS_TH_1_15_8	0xA38F
2509 #define	fec_RS_TH_1_15_8_pos 0
2510 #define	fec_RS_TH_1_15_8_len 8
2511 #define	fec_RS_TH_1_15_8_lsb 8
2512 #define xd_p_fec_RS_TH_2	0xA390
2513 #define	fec_RS_TH_2_pos 0
2514 #define	fec_RS_TH_2_len 8
2515 #define	fec_RS_TH_2_lsb 0
2516 #define xd_p_fec_mon_en	0xA391
2517 #define	fec_mon_en_pos 0
2518 #define	fec_mon_en_len 1
2519 #define	fec_mon_en_lsb 0
2520 #define xd_p_reg_b8to47	0xA391
2521 #define	reg_b8to47_pos 1
2522 #define	reg_b8to47_len 1
2523 #define	reg_b8to47_lsb 0
2524 #define xd_p_reg_rsd_sync_rep	0xA391
2525 #define	reg_rsd_sync_rep_pos 2
2526 #define	reg_rsd_sync_rep_len 1
2527 #define	reg_rsd_sync_rep_lsb 0
2528 #define xd_p_fec_rsd_retrain_rst	0xA391
2529 #define	fec_rsd_retrain_rst_pos 3
2530 #define	fec_rsd_retrain_rst_len 1
2531 #define	fec_rsd_retrain_rst_lsb 0
2532 #define xd_r_fec_rsd_ber_rdy	0xA391
2533 #define	fec_rsd_ber_rdy_pos 4
2534 #define	fec_rsd_ber_rdy_len 1
2535 #define	fec_rsd_ber_rdy_lsb 0
2536 #define xd_p_fec_rsd_ber_rst	0xA391
2537 #define	fec_rsd_ber_rst_pos 5
2538 #define	fec_rsd_ber_rst_len 1
2539 #define	fec_rsd_ber_rst_lsb 0
2540 #define xd_r_fec_vtb_ber_rdy	0xA391
2541 #define	fec_vtb_ber_rdy_pos 6
2542 #define	fec_vtb_ber_rdy_len 1
2543 #define	fec_vtb_ber_rdy_lsb 0
2544 #define xd_p_fec_vtb_ber_rst	0xA391
2545 #define	fec_vtb_ber_rst_pos 7
2546 #define	fec_vtb_ber_rst_len 1
2547 #define	fec_vtb_ber_rst_lsb 0
2548 #define xd_p_reg_vtb_clk40en	0xA392
2549 #define	reg_vtb_clk40en_pos 0
2550 #define	reg_vtb_clk40en_len 1
2551 #define	reg_vtb_clk40en_lsb 0
2552 #define xd_p_fec_vtb_rsd_mon_en	0xA392
2553 #define	fec_vtb_rsd_mon_en_pos 1
2554 #define	fec_vtb_rsd_mon_en_len 1
2555 #define	fec_vtb_rsd_mon_en_lsb 0
2556 #define xd_p_reg_fec_data_en	0xA392
2557 #define	reg_fec_data_en_pos 2
2558 #define	reg_fec_data_en_len 1
2559 #define	reg_fec_data_en_lsb 0
2560 #define xd_p_fec_dummy_reg_2	0xA392
2561 #define	fec_dummy_reg_2_pos 3
2562 #define	fec_dummy_reg_2_len 3
2563 #define	fec_dummy_reg_2_lsb 0
2564 #define xd_p_reg_sync_chk	0xA392
2565 #define	reg_sync_chk_pos 6
2566 #define	reg_sync_chk_len 1
2567 #define	reg_sync_chk_lsb 0
2568 #define xd_p_fec_rsd_bypass	0xA392
2569 #define	fec_rsd_bypass_pos 7
2570 #define	fec_rsd_bypass_len 1
2571 #define	fec_rsd_bypass_lsb 0
2572 #define xd_p_fec_sw_rst	0xA393
2573 #define	fec_sw_rst_pos 0
2574 #define	fec_sw_rst_len 1
2575 #define	fec_sw_rst_lsb 0
2576 #define xd_r_fec_vtb_pm_crc	0xA394
2577 #define	fec_vtb_pm_crc_pos 0
2578 #define	fec_vtb_pm_crc_len 8
2579 #define	fec_vtb_pm_crc_lsb 0
2580 #define xd_r_fec_vtb_tb_7_crc	0xA395
2581 #define	fec_vtb_tb_7_crc_pos 0
2582 #define	fec_vtb_tb_7_crc_len 8
2583 #define	fec_vtb_tb_7_crc_lsb 0
2584 #define xd_r_fec_vtb_tb_6_crc	0xA396
2585 #define	fec_vtb_tb_6_crc_pos 0
2586 #define	fec_vtb_tb_6_crc_len 8
2587 #define	fec_vtb_tb_6_crc_lsb 0
2588 #define xd_r_fec_vtb_tb_5_crc	0xA397
2589 #define	fec_vtb_tb_5_crc_pos 0
2590 #define	fec_vtb_tb_5_crc_len 8
2591 #define	fec_vtb_tb_5_crc_lsb 0
2592 #define xd_r_fec_vtb_tb_4_crc	0xA398
2593 #define	fec_vtb_tb_4_crc_pos 0
2594 #define	fec_vtb_tb_4_crc_len 8
2595 #define	fec_vtb_tb_4_crc_lsb 0
2596 #define xd_r_fec_vtb_tb_3_crc	0xA399
2597 #define	fec_vtb_tb_3_crc_pos 0
2598 #define	fec_vtb_tb_3_crc_len 8
2599 #define	fec_vtb_tb_3_crc_lsb 0
2600 #define xd_r_fec_vtb_tb_2_crc	0xA39A
2601 #define	fec_vtb_tb_2_crc_pos 0
2602 #define	fec_vtb_tb_2_crc_len 8
2603 #define	fec_vtb_tb_2_crc_lsb 0
2604 #define xd_r_fec_vtb_tb_1_crc	0xA39B
2605 #define	fec_vtb_tb_1_crc_pos 0
2606 #define	fec_vtb_tb_1_crc_len 8
2607 #define	fec_vtb_tb_1_crc_lsb 0
2608 #define xd_r_fec_vtb_tb_0_crc	0xA39C
2609 #define	fec_vtb_tb_0_crc_pos 0
2610 #define	fec_vtb_tb_0_crc_len 8
2611 #define	fec_vtb_tb_0_crc_lsb 0
2612 #define xd_r_fec_rsd_bank0_crc	0xA39D
2613 #define	fec_rsd_bank0_crc_pos 0
2614 #define	fec_rsd_bank0_crc_len 8
2615 #define	fec_rsd_bank0_crc_lsb 0
2616 #define xd_r_fec_rsd_bank1_crc	0xA39E
2617 #define	fec_rsd_bank1_crc_pos 0
2618 #define	fec_rsd_bank1_crc_len 8
2619 #define	fec_rsd_bank1_crc_lsb 0
2620 #define xd_r_fec_idi_vtb_crc	0xA39F
2621 #define	fec_idi_vtb_crc_pos 0
2622 #define	fec_idi_vtb_crc_len 8
2623 #define	fec_idi_vtb_crc_lsb 0
2624 #define xd_g_reg_tpsd_txmod	0xA3C0
2625 #define	reg_tpsd_txmod_pos 0
2626 #define	reg_tpsd_txmod_len 2
2627 #define	reg_tpsd_txmod_lsb 0
2628 #define xd_g_reg_tpsd_gi	0xA3C0
2629 #define	reg_tpsd_gi_pos 2
2630 #define	reg_tpsd_gi_len 2
2631 #define	reg_tpsd_gi_lsb 0
2632 #define xd_g_reg_tpsd_hier	0xA3C0
2633 #define	reg_tpsd_hier_pos 4
2634 #define	reg_tpsd_hier_len 3
2635 #define	reg_tpsd_hier_lsb 0
2636 #define xd_g_reg_bw	0xA3C1
2637 #define	reg_bw_pos 2
2638 #define	reg_bw_len 2
2639 #define	reg_bw_lsb 0
2640 #define xd_g_reg_dec_pri	0xA3C1
2641 #define	reg_dec_pri_pos 4
2642 #define	reg_dec_pri_len 1
2643 #define	reg_dec_pri_lsb 0
2644 #define xd_g_reg_tpsd_const	0xA3C1
2645 #define	reg_tpsd_const_pos 6
2646 #define	reg_tpsd_const_len 2
2647 #define	reg_tpsd_const_lsb 0
2648 #define xd_g_reg_tpsd_hpcr	0xA3C2
2649 #define	reg_tpsd_hpcr_pos 0
2650 #define	reg_tpsd_hpcr_len 3
2651 #define	reg_tpsd_hpcr_lsb 0
2652 #define xd_g_reg_tpsd_lpcr	0xA3C2
2653 #define	reg_tpsd_lpcr_pos 3
2654 #define	reg_tpsd_lpcr_len 3
2655 #define	reg_tpsd_lpcr_lsb 0
2656 #define xd_g_reg_ofsm_clk	0xA3D0
2657 #define	reg_ofsm_clk_pos 0
2658 #define	reg_ofsm_clk_len 3
2659 #define	reg_ofsm_clk_lsb 0
2660 #define xd_g_reg_fclk_cfg	0xA3D1
2661 #define	reg_fclk_cfg_pos 0
2662 #define	reg_fclk_cfg_len 1
2663 #define	reg_fclk_cfg_lsb 0
2664 #define xd_g_reg_fclk_idi	0xA3D1
2665 #define	reg_fclk_idi_pos 1
2666 #define	reg_fclk_idi_len 1
2667 #define	reg_fclk_idi_lsb 0
2668 #define xd_g_reg_fclk_odi	0xA3D1
2669 #define	reg_fclk_odi_pos 2
2670 #define	reg_fclk_odi_len 1
2671 #define	reg_fclk_odi_lsb 0
2672 #define xd_g_reg_fclk_rsd	0xA3D1
2673 #define	reg_fclk_rsd_pos 3
2674 #define	reg_fclk_rsd_len 1
2675 #define	reg_fclk_rsd_lsb 0
2676 #define xd_g_reg_fclk_vtb	0xA3D1
2677 #define	reg_fclk_vtb_pos 4
2678 #define	reg_fclk_vtb_len 1
2679 #define	reg_fclk_vtb_lsb 0
2680 #define xd_g_reg_fclk_cste	0xA3D1
2681 #define	reg_fclk_cste_pos 5
2682 #define	reg_fclk_cste_len 1
2683 #define	reg_fclk_cste_lsb 0
2684 #define xd_g_reg_fclk_mp2if	0xA3D1
2685 #define	reg_fclk_mp2if_pos 6
2686 #define	reg_fclk_mp2if_len 1
2687 #define	reg_fclk_mp2if_lsb 0
2688 #define xd_I2C_i2c_m_slave_addr	0xA400
2689 #define	i2c_m_slave_addr_pos 0
2690 #define	i2c_m_slave_addr_len 8
2691 #define	i2c_m_slave_addr_lsb 0
2692 #define xd_I2C_i2c_m_data1	0xA401
2693 #define	i2c_m_data1_pos 0
2694 #define	i2c_m_data1_len 8
2695 #define	i2c_m_data1_lsb 0
2696 #define xd_I2C_i2c_m_data2	0xA402
2697 #define	i2c_m_data2_pos 0
2698 #define	i2c_m_data2_len 8
2699 #define	i2c_m_data2_lsb 0
2700 #define xd_I2C_i2c_m_data3	0xA403
2701 #define	i2c_m_data3_pos 0
2702 #define	i2c_m_data3_len 8
2703 #define	i2c_m_data3_lsb 0
2704 #define xd_I2C_i2c_m_data4	0xA404
2705 #define	i2c_m_data4_pos 0
2706 #define	i2c_m_data4_len 8
2707 #define	i2c_m_data4_lsb 0
2708 #define xd_I2C_i2c_m_data5	0xA405
2709 #define	i2c_m_data5_pos 0
2710 #define	i2c_m_data5_len 8
2711 #define	i2c_m_data5_lsb 0
2712 #define xd_I2C_i2c_m_data6	0xA406
2713 #define	i2c_m_data6_pos 0
2714 #define	i2c_m_data6_len 8
2715 #define	i2c_m_data6_lsb 0
2716 #define xd_I2C_i2c_m_data7	0xA407
2717 #define	i2c_m_data7_pos 0
2718 #define	i2c_m_data7_len 8
2719 #define	i2c_m_data7_lsb 0
2720 #define xd_I2C_i2c_m_data8	0xA408
2721 #define	i2c_m_data8_pos 0
2722 #define	i2c_m_data8_len 8
2723 #define	i2c_m_data8_lsb 0
2724 #define xd_I2C_i2c_m_data9	0xA409
2725 #define	i2c_m_data9_pos 0
2726 #define	i2c_m_data9_len 8
2727 #define	i2c_m_data9_lsb 0
2728 #define xd_I2C_i2c_m_data10	0xA40A
2729 #define	i2c_m_data10_pos 0
2730 #define	i2c_m_data10_len 8
2731 #define	i2c_m_data10_lsb 0
2732 #define xd_I2C_i2c_m_data11	0xA40B
2733 #define	i2c_m_data11_pos 0
2734 #define	i2c_m_data11_len 8
2735 #define	i2c_m_data11_lsb 0
2736 #define xd_I2C_i2c_m_cmd_rw	0xA40C
2737 #define	i2c_m_cmd_rw_pos 0
2738 #define	i2c_m_cmd_rw_len 1
2739 #define	i2c_m_cmd_rw_lsb 0
2740 #define xd_I2C_i2c_m_cmd_rwlen	0xA40C
2741 #define	i2c_m_cmd_rwlen_pos 3
2742 #define	i2c_m_cmd_rwlen_len 4
2743 #define	i2c_m_cmd_rwlen_lsb 0
2744 #define xd_I2C_i2c_m_status_cmd_exe	0xA40D
2745 #define	i2c_m_status_cmd_exe_pos 0
2746 #define	i2c_m_status_cmd_exe_len 1
2747 #define	i2c_m_status_cmd_exe_lsb 0
2748 #define xd_I2C_i2c_m_status_wdat_done	0xA40D
2749 #define	i2c_m_status_wdat_done_pos 1
2750 #define	i2c_m_status_wdat_done_len 1
2751 #define	i2c_m_status_wdat_done_lsb 0
2752 #define xd_I2C_i2c_m_status_wdat_fail	0xA40D
2753 #define	i2c_m_status_wdat_fail_pos 2
2754 #define	i2c_m_status_wdat_fail_len 1
2755 #define	i2c_m_status_wdat_fail_lsb 0
2756 #define xd_I2C_i2c_m_period	0xA40E
2757 #define	i2c_m_period_pos 0
2758 #define	i2c_m_period_len 8
2759 #define	i2c_m_period_lsb 0
2760 #define xd_I2C_i2c_m_reg_msb_lsb	0xA40F
2761 #define	i2c_m_reg_msb_lsb_pos 0
2762 #define	i2c_m_reg_msb_lsb_len 1
2763 #define	i2c_m_reg_msb_lsb_lsb 0
2764 #define xd_I2C_reg_ofdm_rst	0xA40F
2765 #define	reg_ofdm_rst_pos 1
2766 #define	reg_ofdm_rst_len 1
2767 #define	reg_ofdm_rst_lsb 0
2768 #define xd_I2C_reg_sample_period_on_tuner	0xA40F
2769 #define	reg_sample_period_on_tuner_pos 2
2770 #define	reg_sample_period_on_tuner_len 1
2771 #define	reg_sample_period_on_tuner_lsb 0
2772 #define xd_I2C_reg_rst_i2c	0xA40F
2773 #define	reg_rst_i2c_pos 3
2774 #define	reg_rst_i2c_len 1
2775 #define	reg_rst_i2c_lsb 0
2776 #define xd_I2C_reg_ofdm_rst_en	0xA40F
2777 #define	reg_ofdm_rst_en_pos 4
2778 #define	reg_ofdm_rst_en_len 1
2779 #define	reg_ofdm_rst_en_lsb 0
2780 #define xd_I2C_reg_tuner_sda_sync_on	0xA40F
2781 #define	reg_tuner_sda_sync_on_pos 5
2782 #define	reg_tuner_sda_sync_on_len 1
2783 #define	reg_tuner_sda_sync_on_lsb 0
2784 #define xd_p_mp2if_data_access_disable_ofsm	0xA500
2785 #define	mp2if_data_access_disable_ofsm_pos 0
2786 #define	mp2if_data_access_disable_ofsm_len 1
2787 #define	mp2if_data_access_disable_ofsm_lsb 0
2788 #define xd_p_reg_mp2_sw_rst_ofsm	0xA500
2789 #define	reg_mp2_sw_rst_ofsm_pos 1
2790 #define	reg_mp2_sw_rst_ofsm_len 1
2791 #define	reg_mp2_sw_rst_ofsm_lsb 0
2792 #define xd_p_reg_mp2if_clk_en_ofsm	0xA500
2793 #define	reg_mp2if_clk_en_ofsm_pos 2
2794 #define	reg_mp2if_clk_en_ofsm_len 1
2795 #define	reg_mp2if_clk_en_ofsm_lsb 0
2796 #define xd_r_mp2if_sync_byte_locked	0xA500
2797 #define	mp2if_sync_byte_locked_pos 3
2798 #define	mp2if_sync_byte_locked_len 1
2799 #define	mp2if_sync_byte_locked_lsb 0
2800 #define xd_r_mp2if_ts_not_188	0xA500
2801 #define	mp2if_ts_not_188_pos 4
2802 #define	mp2if_ts_not_188_len 1
2803 #define	mp2if_ts_not_188_lsb 0
2804 #define xd_r_mp2if_psb_empty	0xA500
2805 #define	mp2if_psb_empty_pos 5
2806 #define	mp2if_psb_empty_len 1
2807 #define	mp2if_psb_empty_lsb 0
2808 #define xd_r_mp2if_psb_overflow	0xA500
2809 #define	mp2if_psb_overflow_pos 6
2810 #define	mp2if_psb_overflow_len 1
2811 #define	mp2if_psb_overflow_lsb 0
2812 #define xd_p_mp2if_keep_sf_sync_byte_ofsm	0xA500
2813 #define	mp2if_keep_sf_sync_byte_ofsm_pos 7
2814 #define	mp2if_keep_sf_sync_byte_ofsm_len 1
2815 #define	mp2if_keep_sf_sync_byte_ofsm_lsb 0
2816 #define xd_r_mp2if_psb_mp2if_num_pkt	0xA501
2817 #define	mp2if_psb_mp2if_num_pkt_pos 0
2818 #define	mp2if_psb_mp2if_num_pkt_len 6
2819 #define	mp2if_psb_mp2if_num_pkt_lsb 0
2820 #define xd_p_reg_mpeg_full_speed_ofsm	0xA501
2821 #define	reg_mpeg_full_speed_ofsm_pos 6
2822 #define	reg_mpeg_full_speed_ofsm_len 1
2823 #define	reg_mpeg_full_speed_ofsm_lsb 0
2824 #define xd_p_mp2if_mpeg_ser_mode_ofsm	0xA501
2825 #define	mp2if_mpeg_ser_mode_ofsm_pos 7
2826 #define	mp2if_mpeg_ser_mode_ofsm_len 1
2827 #define	mp2if_mpeg_ser_mode_ofsm_lsb 0
2828 #define xd_p_reg_sw_mon51	0xA600
2829 #define	reg_sw_mon51_pos 0
2830 #define	reg_sw_mon51_len 8
2831 #define	reg_sw_mon51_lsb 0
2832 #define xd_p_reg_top_pcsel	0xA601
2833 #define	reg_top_pcsel_pos 0
2834 #define	reg_top_pcsel_len 1
2835 #define	reg_top_pcsel_lsb 0
2836 #define xd_p_reg_top_rs232	0xA601
2837 #define	reg_top_rs232_pos 1
2838 #define	reg_top_rs232_len 1
2839 #define	reg_top_rs232_lsb 0
2840 #define xd_p_reg_top_pcout	0xA601
2841 #define	reg_top_pcout_pos 2
2842 #define	reg_top_pcout_len 1
2843 #define	reg_top_pcout_lsb 0
2844 #define xd_p_reg_top_debug	0xA601
2845 #define	reg_top_debug_pos 3
2846 #define	reg_top_debug_len 1
2847 #define	reg_top_debug_lsb 0
2848 #define xd_p_reg_top_adcdly	0xA601
2849 #define	reg_top_adcdly_pos 4
2850 #define	reg_top_adcdly_len 2
2851 #define	reg_top_adcdly_lsb 0
2852 #define xd_p_reg_top_pwrdw	0xA601
2853 #define	reg_top_pwrdw_pos 6
2854 #define	reg_top_pwrdw_len 1
2855 #define	reg_top_pwrdw_lsb 0
2856 #define xd_p_reg_top_pwrdw_inv	0xA601
2857 #define	reg_top_pwrdw_inv_pos 7
2858 #define	reg_top_pwrdw_inv_len 1
2859 #define	reg_top_pwrdw_inv_lsb 0
2860 #define xd_p_reg_top_int_inv	0xA602
2861 #define	reg_top_int_inv_pos 0
2862 #define	reg_top_int_inv_len 1
2863 #define	reg_top_int_inv_lsb 0
2864 #define xd_p_reg_top_dio_sel	0xA602
2865 #define	reg_top_dio_sel_pos 1
2866 #define	reg_top_dio_sel_len 1
2867 #define	reg_top_dio_sel_lsb 0
2868 #define xd_p_reg_top_gpioon0	0xA603
2869 #define	reg_top_gpioon0_pos 0
2870 #define	reg_top_gpioon0_len 1
2871 #define	reg_top_gpioon0_lsb 0
2872 #define xd_p_reg_top_gpioon1	0xA603
2873 #define	reg_top_gpioon1_pos 1
2874 #define	reg_top_gpioon1_len 1
2875 #define	reg_top_gpioon1_lsb 0
2876 #define xd_p_reg_top_gpioon2	0xA603
2877 #define	reg_top_gpioon2_pos 2
2878 #define	reg_top_gpioon2_len 1
2879 #define	reg_top_gpioon2_lsb 0
2880 #define xd_p_reg_top_gpioon3	0xA603
2881 #define	reg_top_gpioon3_pos 3
2882 #define	reg_top_gpioon3_len 1
2883 #define	reg_top_gpioon3_lsb 0
2884 #define xd_p_reg_top_lockon1	0xA603
2885 #define	reg_top_lockon1_pos 4
2886 #define	reg_top_lockon1_len 1
2887 #define	reg_top_lockon1_lsb 0
2888 #define xd_p_reg_top_lockon2	0xA603
2889 #define	reg_top_lockon2_pos 5
2890 #define	reg_top_lockon2_len 1
2891 #define	reg_top_lockon2_lsb 0
2892 #define xd_p_reg_top_gpioo0	0xA604
2893 #define	reg_top_gpioo0_pos 0
2894 #define	reg_top_gpioo0_len 1
2895 #define	reg_top_gpioo0_lsb 0
2896 #define xd_p_reg_top_gpioo1	0xA604
2897 #define	reg_top_gpioo1_pos 1
2898 #define	reg_top_gpioo1_len 1
2899 #define	reg_top_gpioo1_lsb 0
2900 #define xd_p_reg_top_gpioo2	0xA604
2901 #define	reg_top_gpioo2_pos 2
2902 #define	reg_top_gpioo2_len 1
2903 #define	reg_top_gpioo2_lsb 0
2904 #define xd_p_reg_top_gpioo3	0xA604
2905 #define	reg_top_gpioo3_pos 3
2906 #define	reg_top_gpioo3_len 1
2907 #define	reg_top_gpioo3_lsb 0
2908 #define xd_p_reg_top_lock1	0xA604
2909 #define	reg_top_lock1_pos 4
2910 #define	reg_top_lock1_len 1
2911 #define	reg_top_lock1_lsb 0
2912 #define xd_p_reg_top_lock2	0xA604
2913 #define	reg_top_lock2_pos 5
2914 #define	reg_top_lock2_len 1
2915 #define	reg_top_lock2_lsb 0
2916 #define xd_p_reg_top_gpioen0	0xA605
2917 #define	reg_top_gpioen0_pos 0
2918 #define	reg_top_gpioen0_len 1
2919 #define	reg_top_gpioen0_lsb 0
2920 #define xd_p_reg_top_gpioen1	0xA605
2921 #define	reg_top_gpioen1_pos 1
2922 #define	reg_top_gpioen1_len 1
2923 #define	reg_top_gpioen1_lsb 0
2924 #define xd_p_reg_top_gpioen2	0xA605
2925 #define	reg_top_gpioen2_pos 2
2926 #define	reg_top_gpioen2_len 1
2927 #define	reg_top_gpioen2_lsb 0
2928 #define xd_p_reg_top_gpioen3	0xA605
2929 #define	reg_top_gpioen3_pos 3
2930 #define	reg_top_gpioen3_len 1
2931 #define	reg_top_gpioen3_lsb 0
2932 #define xd_p_reg_top_locken1	0xA605
2933 #define	reg_top_locken1_pos 4
2934 #define	reg_top_locken1_len 1
2935 #define	reg_top_locken1_lsb 0
2936 #define xd_p_reg_top_locken2	0xA605
2937 #define	reg_top_locken2_pos 5
2938 #define	reg_top_locken2_len 1
2939 #define	reg_top_locken2_lsb 0
2940 #define xd_r_reg_top_gpioi0	0xA606
2941 #define	reg_top_gpioi0_pos 0
2942 #define	reg_top_gpioi0_len 1
2943 #define	reg_top_gpioi0_lsb 0
2944 #define xd_r_reg_top_gpioi1	0xA606
2945 #define	reg_top_gpioi1_pos 1
2946 #define	reg_top_gpioi1_len 1
2947 #define	reg_top_gpioi1_lsb 0
2948 #define xd_r_reg_top_gpioi2	0xA606
2949 #define	reg_top_gpioi2_pos 2
2950 #define	reg_top_gpioi2_len 1
2951 #define	reg_top_gpioi2_lsb 0
2952 #define xd_r_reg_top_gpioi3	0xA606
2953 #define	reg_top_gpioi3_pos 3
2954 #define	reg_top_gpioi3_len 1
2955 #define	reg_top_gpioi3_lsb 0
2956 #define xd_r_reg_top_locki1	0xA606
2957 #define	reg_top_locki1_pos 4
2958 #define	reg_top_locki1_len 1
2959 #define	reg_top_locki1_lsb 0
2960 #define xd_r_reg_top_locki2	0xA606
2961 #define	reg_top_locki2_pos 5
2962 #define	reg_top_locki2_len 1
2963 #define	reg_top_locki2_lsb 0
2964 #define xd_p_reg_dummy_7_0	0xA608
2965 #define	reg_dummy_7_0_pos 0
2966 #define	reg_dummy_7_0_len 8
2967 #define	reg_dummy_7_0_lsb 0
2968 #define xd_p_reg_dummy_15_8	0xA609
2969 #define	reg_dummy_15_8_pos 0
2970 #define	reg_dummy_15_8_len 8
2971 #define	reg_dummy_15_8_lsb 8
2972 #define xd_p_reg_dummy_23_16	0xA60A
2973 #define	reg_dummy_23_16_pos 0
2974 #define	reg_dummy_23_16_len 8
2975 #define	reg_dummy_23_16_lsb 16
2976 #define xd_p_reg_dummy_31_24	0xA60B
2977 #define	reg_dummy_31_24_pos 0
2978 #define	reg_dummy_31_24_len 8
2979 #define	reg_dummy_31_24_lsb 24
2980 #define xd_p_reg_dummy_39_32	0xA60C
2981 #define	reg_dummy_39_32_pos 0
2982 #define	reg_dummy_39_32_len 8
2983 #define	reg_dummy_39_32_lsb 32
2984 #define xd_p_reg_dummy_47_40	0xA60D
2985 #define	reg_dummy_47_40_pos 0
2986 #define	reg_dummy_47_40_len 8
2987 #define	reg_dummy_47_40_lsb 40
2988 #define xd_p_reg_dummy_55_48	0xA60E
2989 #define	reg_dummy_55_48_pos 0
2990 #define	reg_dummy_55_48_len 8
2991 #define	reg_dummy_55_48_lsb 48
2992 #define xd_p_reg_dummy_63_56	0xA60F
2993 #define	reg_dummy_63_56_pos 0
2994 #define	reg_dummy_63_56_len 8
2995 #define	reg_dummy_63_56_lsb 56
2996 #define xd_p_reg_dummy_71_64	0xA610
2997 #define	reg_dummy_71_64_pos 0
2998 #define	reg_dummy_71_64_len 8
2999 #define	reg_dummy_71_64_lsb 64
3000 #define xd_p_reg_dummy_79_72	0xA611
3001 #define	reg_dummy_79_72_pos 0
3002 #define	reg_dummy_79_72_len 8
3003 #define	reg_dummy_79_72_lsb 72
3004 #define xd_p_reg_dummy_87_80	0xA612
3005 #define	reg_dummy_87_80_pos 0
3006 #define	reg_dummy_87_80_len 8
3007 #define	reg_dummy_87_80_lsb 80
3008 #define xd_p_reg_dummy_95_88	0xA613
3009 #define	reg_dummy_95_88_pos 0
3010 #define	reg_dummy_95_88_len 8
3011 #define	reg_dummy_95_88_lsb 88
3012 #define xd_p_reg_dummy_103_96	0xA614
3013 #define	reg_dummy_103_96_pos 0
3014 #define	reg_dummy_103_96_len 8
3015 #define	reg_dummy_103_96_lsb 96
3016 
3017 #define xd_p_reg_unplug_flag	0xA615
3018 #define	reg_unplug_flag_pos 0
3019 #define	reg_unplug_flag_len 1
3020 #define	reg_unplug_flag_lsb 104
3021 
3022 #define xd_p_reg_api_dca_stes_request   0xA615
3023 #define reg_api_dca_stes_request_pos 1
3024 #define reg_api_dca_stes_request_len 1
3025 #define reg_api_dca_stes_request_lsb 0
3026 
3027 #define xd_p_reg_back_to_dca_flag	0xA615
3028 #define	reg_back_to_dca_flag_pos 2
3029 #define	reg_back_to_dca_flag_len 1
3030 #define	reg_back_to_dca_flag_lsb 106
3031 
3032 #define xd_p_reg_api_retrain_request    0xA615
3033 #define reg_api_retrain_request_pos 3
3034 #define reg_api_retrain_request_len 1
3035 #define reg_api_retrain_request_lsb 0
3036 
3037 #define xd_p_reg_Dyn_Top_Try_flag	0xA615
3038 #define	reg_Dyn_Top_Try_flag_pos 3
3039 #define	reg_Dyn_Top_Try_flag_len 1
3040 #define	reg_Dyn_Top_Try_flag_lsb 107
3041 
3042 #define xd_p_reg_API_retrain_freeze_flag	0xA615
3043 #define	reg_API_retrain_freeze_flag_pos 4
3044 #define	reg_API_retrain_freeze_flag_len 1
3045 #define	reg_API_retrain_freeze_flag_lsb 108
3046 
3047 #define xd_p_reg_dummy_111_104	0xA615
3048 #define	reg_dummy_111_104_pos 0
3049 #define	reg_dummy_111_104_len 8
3050 #define	reg_dummy_111_104_lsb 104
3051 #define xd_p_reg_dummy_119_112	0xA616
3052 #define	reg_dummy_119_112_pos 0
3053 #define	reg_dummy_119_112_len 8
3054 #define	reg_dummy_119_112_lsb 112
3055 #define xd_p_reg_dummy_127_120	0xA617
3056 #define	reg_dummy_127_120_pos 0
3057 #define	reg_dummy_127_120_len 8
3058 #define	reg_dummy_127_120_lsb 120
3059 #define xd_p_reg_dummy_135_128	0xA618
3060 #define	reg_dummy_135_128_pos 0
3061 #define	reg_dummy_135_128_len 8
3062 #define	reg_dummy_135_128_lsb 128
3063 
3064 #define xd_p_reg_dummy_143_136	0xA619
3065 #define	reg_dummy_143_136_pos 0
3066 #define	reg_dummy_143_136_len 8
3067 #define	reg_dummy_143_136_lsb 136
3068 
3069 #define xd_p_reg_CCIR_dis	0xA619
3070 #define	reg_CCIR_dis_pos 0
3071 #define	reg_CCIR_dis_len 1
3072 #define	reg_CCIR_dis_lsb 0
3073 
3074 #define xd_p_reg_dummy_151_144	0xA61A
3075 #define	reg_dummy_151_144_pos 0
3076 #define	reg_dummy_151_144_len 8
3077 #define	reg_dummy_151_144_lsb 144
3078 
3079 #define xd_p_reg_dummy_159_152	0xA61B
3080 #define	reg_dummy_159_152_pos 0
3081 #define	reg_dummy_159_152_len 8
3082 #define	reg_dummy_159_152_lsb 152
3083 
3084 #define xd_p_reg_dummy_167_160	0xA61C
3085 #define	reg_dummy_167_160_pos 0
3086 #define	reg_dummy_167_160_len 8
3087 #define	reg_dummy_167_160_lsb 160
3088 
3089 #define xd_p_reg_dummy_175_168	0xA61D
3090 #define	reg_dummy_175_168_pos 0
3091 #define	reg_dummy_175_168_len 8
3092 #define	reg_dummy_175_168_lsb 168
3093 
3094 #define xd_p_reg_dummy_183_176	0xA61E
3095 #define	reg_dummy_183_176_pos 0
3096 #define	reg_dummy_183_176_len 8
3097 #define	reg_dummy_183_176_lsb 176
3098 
3099 #define xd_p_reg_ofsm_read_rbc_en  0xA61E
3100 #define reg_ofsm_read_rbc_en_pos 2
3101 #define reg_ofsm_read_rbc_en_len 1
3102 #define reg_ofsm_read_rbc_en_lsb 0
3103 
3104 #define xd_p_reg_ce_filter_selection_dis  0xA61E
3105 #define reg_ce_filter_selection_dis_pos 1
3106 #define reg_ce_filter_selection_dis_len 1
3107 #define reg_ce_filter_selection_dis_lsb 0
3108 
3109 #define xd_p_reg_OFSM_version_control_7_0  0xA611
3110 #define reg_OFSM_version_control_7_0_pos 0
3111 #define reg_OFSM_version_control_7_0_len 8
3112 #define reg_OFSM_version_control_7_0_lsb 0
3113 
3114 #define xd_p_reg_OFSM_version_control_15_8  0xA61F
3115 #define reg_OFSM_version_control_15_8_pos 0
3116 #define reg_OFSM_version_control_15_8_len 8
3117 #define reg_OFSM_version_control_15_8_lsb 0
3118 
3119 #define xd_p_reg_OFSM_version_control_23_16  0xA620
3120 #define reg_OFSM_version_control_23_16_pos 0
3121 #define reg_OFSM_version_control_23_16_len 8
3122 #define reg_OFSM_version_control_23_16_lsb 0
3123 
3124 #define xd_p_reg_dummy_191_184	0xA61F
3125 #define	reg_dummy_191_184_pos 0
3126 #define	reg_dummy_191_184_len 8
3127 #define	reg_dummy_191_184_lsb 184
3128 
3129 #define xd_p_reg_dummy_199_192	0xA620
3130 #define	reg_dummy_199_192_pos 0
3131 #define	reg_dummy_199_192_len 8
3132 #define	reg_dummy_199_192_lsb 192
3133 
3134 #define xd_p_reg_ce_en	0xABC0
3135 #define	reg_ce_en_pos 0
3136 #define	reg_ce_en_len 1
3137 #define	reg_ce_en_lsb 0
3138 #define xd_p_reg_ce_fctrl_en	0xABC0
3139 #define	reg_ce_fctrl_en_pos 1
3140 #define	reg_ce_fctrl_en_len 1
3141 #define	reg_ce_fctrl_en_lsb 0
3142 #define xd_p_reg_ce_fste_tdi	0xABC0
3143 #define	reg_ce_fste_tdi_pos 2
3144 #define	reg_ce_fste_tdi_len 1
3145 #define	reg_ce_fste_tdi_lsb 0
3146 #define xd_p_reg_ce_dynamic	0xABC0
3147 #define	reg_ce_dynamic_pos 3
3148 #define	reg_ce_dynamic_len 1
3149 #define	reg_ce_dynamic_lsb 0
3150 #define xd_p_reg_ce_conf	0xABC0
3151 #define	reg_ce_conf_pos 4
3152 #define	reg_ce_conf_len 2
3153 #define	reg_ce_conf_lsb 0
3154 #define xd_p_reg_ce_dyn12	0xABC0
3155 #define	reg_ce_dyn12_pos 6
3156 #define	reg_ce_dyn12_len 1
3157 #define	reg_ce_dyn12_lsb 0
3158 #define xd_p_reg_ce_derot_en	0xABC0
3159 #define	reg_ce_derot_en_pos 7
3160 #define	reg_ce_derot_en_len 1
3161 #define	reg_ce_derot_en_lsb 0
3162 #define xd_p_reg_ce_dynamic_th_7_0	0xABC1
3163 #define	reg_ce_dynamic_th_7_0_pos 0
3164 #define	reg_ce_dynamic_th_7_0_len 8
3165 #define	reg_ce_dynamic_th_7_0_lsb 0
3166 #define xd_p_reg_ce_dynamic_th_15_8	0xABC2
3167 #define	reg_ce_dynamic_th_15_8_pos 0
3168 #define	reg_ce_dynamic_th_15_8_len 8
3169 #define	reg_ce_dynamic_th_15_8_lsb 8
3170 #define xd_p_reg_ce_s1	0xABC3
3171 #define	reg_ce_s1_pos 0
3172 #define	reg_ce_s1_len 5
3173 #define	reg_ce_s1_lsb 0
3174 #define xd_p_reg_ce_var_forced_value	0xABC3
3175 #define	reg_ce_var_forced_value_pos 5
3176 #define	reg_ce_var_forced_value_len 3
3177 #define	reg_ce_var_forced_value_lsb 0
3178 #define xd_p_reg_ce_data_im_7_0	0xABC4
3179 #define	reg_ce_data_im_7_0_pos 0
3180 #define	reg_ce_data_im_7_0_len 8
3181 #define	reg_ce_data_im_7_0_lsb 0
3182 #define xd_p_reg_ce_data_im_8	0xABC5
3183 #define	reg_ce_data_im_8_pos 0
3184 #define	reg_ce_data_im_8_len 1
3185 #define	reg_ce_data_im_8_lsb 0
3186 #define xd_p_reg_ce_data_re_6_0	0xABC5
3187 #define	reg_ce_data_re_6_0_pos 1
3188 #define	reg_ce_data_re_6_0_len 7
3189 #define	reg_ce_data_re_6_0_lsb 0
3190 #define xd_p_reg_ce_data_re_8_7	0xABC6
3191 #define	reg_ce_data_re_8_7_pos 0
3192 #define	reg_ce_data_re_8_7_len 2
3193 #define	reg_ce_data_re_8_7_lsb 7
3194 #define xd_p_reg_ce_tone_5_0	0xABC6
3195 #define	reg_ce_tone_5_0_pos 2
3196 #define	reg_ce_tone_5_0_len 6
3197 #define	reg_ce_tone_5_0_lsb 0
3198 #define xd_p_reg_ce_tone_12_6	0xABC7
3199 #define	reg_ce_tone_12_6_pos 0
3200 #define	reg_ce_tone_12_6_len 7
3201 #define	reg_ce_tone_12_6_lsb 6
3202 #define xd_p_reg_ce_centroid_drift_th	0xABC8
3203 #define	reg_ce_centroid_drift_th_pos 0
3204 #define	reg_ce_centroid_drift_th_len 8
3205 #define	reg_ce_centroid_drift_th_lsb 0
3206 #define xd_p_reg_ce_centroid_count_max	0xABC9
3207 #define	reg_ce_centroid_count_max_pos 0
3208 #define	reg_ce_centroid_count_max_len 4
3209 #define	reg_ce_centroid_count_max_lsb 0
3210 #define xd_p_reg_ce_centroid_bias_inc_7_0	0xABCA
3211 #define	reg_ce_centroid_bias_inc_7_0_pos 0
3212 #define	reg_ce_centroid_bias_inc_7_0_len 8
3213 #define	reg_ce_centroid_bias_inc_7_0_lsb 0
3214 #define xd_p_reg_ce_centroid_bias_inc_8	0xABCB
3215 #define	reg_ce_centroid_bias_inc_8_pos 0
3216 #define	reg_ce_centroid_bias_inc_8_len 1
3217 #define	reg_ce_centroid_bias_inc_8_lsb 0
3218 #define xd_p_reg_ce_var_th0_7_0	0xABCC
3219 #define	reg_ce_var_th0_7_0_pos 0
3220 #define	reg_ce_var_th0_7_0_len 8
3221 #define	reg_ce_var_th0_7_0_lsb 0
3222 #define xd_p_reg_ce_var_th0_15_8	0xABCD
3223 #define	reg_ce_var_th0_15_8_pos 0
3224 #define	reg_ce_var_th0_15_8_len 8
3225 #define	reg_ce_var_th0_15_8_lsb 8
3226 #define xd_p_reg_ce_var_th1_7_0	0xABCE
3227 #define	reg_ce_var_th1_7_0_pos 0
3228 #define	reg_ce_var_th1_7_0_len 8
3229 #define	reg_ce_var_th1_7_0_lsb 0
3230 #define xd_p_reg_ce_var_th1_15_8	0xABCF
3231 #define	reg_ce_var_th1_15_8_pos 0
3232 #define	reg_ce_var_th1_15_8_len 8
3233 #define	reg_ce_var_th1_15_8_lsb 8
3234 #define xd_p_reg_ce_var_th2_7_0	0xABD0
3235 #define	reg_ce_var_th2_7_0_pos 0
3236 #define	reg_ce_var_th2_7_0_len 8
3237 #define	reg_ce_var_th2_7_0_lsb 0
3238 #define xd_p_reg_ce_var_th2_15_8	0xABD1
3239 #define	reg_ce_var_th2_15_8_pos 0
3240 #define	reg_ce_var_th2_15_8_len 8
3241 #define	reg_ce_var_th2_15_8_lsb 8
3242 #define xd_p_reg_ce_var_th3_7_0	0xABD2
3243 #define	reg_ce_var_th3_7_0_pos 0
3244 #define	reg_ce_var_th3_7_0_len 8
3245 #define	reg_ce_var_th3_7_0_lsb 0
3246 #define xd_p_reg_ce_var_th3_15_8	0xABD3
3247 #define	reg_ce_var_th3_15_8_pos 0
3248 #define	reg_ce_var_th3_15_8_len 8
3249 #define	reg_ce_var_th3_15_8_lsb 8
3250 #define xd_p_reg_ce_var_th4_7_0	0xABD4
3251 #define	reg_ce_var_th4_7_0_pos 0
3252 #define	reg_ce_var_th4_7_0_len 8
3253 #define	reg_ce_var_th4_7_0_lsb 0
3254 #define xd_p_reg_ce_var_th4_15_8	0xABD5
3255 #define	reg_ce_var_th4_15_8_pos 0
3256 #define	reg_ce_var_th4_15_8_len 8
3257 #define	reg_ce_var_th4_15_8_lsb 8
3258 #define xd_p_reg_ce_var_th5_7_0	0xABD6
3259 #define	reg_ce_var_th5_7_0_pos 0
3260 #define	reg_ce_var_th5_7_0_len 8
3261 #define	reg_ce_var_th5_7_0_lsb 0
3262 #define xd_p_reg_ce_var_th5_15_8	0xABD7
3263 #define	reg_ce_var_th5_15_8_pos 0
3264 #define	reg_ce_var_th5_15_8_len 8
3265 #define	reg_ce_var_th5_15_8_lsb 8
3266 #define xd_p_reg_ce_var_th6_7_0	0xABD8
3267 #define	reg_ce_var_th6_7_0_pos 0
3268 #define	reg_ce_var_th6_7_0_len 8
3269 #define	reg_ce_var_th6_7_0_lsb 0
3270 #define xd_p_reg_ce_var_th6_15_8	0xABD9
3271 #define	reg_ce_var_th6_15_8_pos 0
3272 #define	reg_ce_var_th6_15_8_len 8
3273 #define	reg_ce_var_th6_15_8_lsb 8
3274 #define xd_p_reg_ce_fctrl_reset	0xABDA
3275 #define	reg_ce_fctrl_reset_pos 0
3276 #define	reg_ce_fctrl_reset_len 1
3277 #define	reg_ce_fctrl_reset_lsb 0
3278 #define xd_p_reg_ce_cent_auto_clr_en	0xABDA
3279 #define	reg_ce_cent_auto_clr_en_pos 1
3280 #define	reg_ce_cent_auto_clr_en_len 1
3281 #define	reg_ce_cent_auto_clr_en_lsb 0
3282 #define xd_p_reg_ce_fctrl_auto_reset_en	0xABDA
3283 #define	reg_ce_fctrl_auto_reset_en_pos 2
3284 #define	reg_ce_fctrl_auto_reset_en_len 1
3285 #define	reg_ce_fctrl_auto_reset_en_lsb 0
3286 #define xd_p_reg_ce_var_forced_en	0xABDA
3287 #define	reg_ce_var_forced_en_pos 3
3288 #define	reg_ce_var_forced_en_len 1
3289 #define	reg_ce_var_forced_en_lsb 0
3290 #define xd_p_reg_ce_cent_forced_en	0xABDA
3291 #define	reg_ce_cent_forced_en_pos 4
3292 #define	reg_ce_cent_forced_en_len 1
3293 #define	reg_ce_cent_forced_en_lsb 0
3294 #define xd_p_reg_ce_var_max	0xABDA
3295 #define	reg_ce_var_max_pos 5
3296 #define	reg_ce_var_max_len 3
3297 #define	reg_ce_var_max_lsb 0
3298 #define xd_p_reg_ce_cent_forced_value_7_0	0xABDB
3299 #define	reg_ce_cent_forced_value_7_0_pos 0
3300 #define	reg_ce_cent_forced_value_7_0_len 8
3301 #define	reg_ce_cent_forced_value_7_0_lsb 0
3302 #define xd_p_reg_ce_cent_forced_value_11_8	0xABDC
3303 #define	reg_ce_cent_forced_value_11_8_pos 0
3304 #define	reg_ce_cent_forced_value_11_8_len 4
3305 #define	reg_ce_cent_forced_value_11_8_lsb 8
3306 #define xd_p_reg_ce_fctrl_rd	0xABDD
3307 #define	reg_ce_fctrl_rd_pos 0
3308 #define	reg_ce_fctrl_rd_len 1
3309 #define	reg_ce_fctrl_rd_lsb 0
3310 #define xd_p_reg_ce_centroid_max_6_0	0xABDD
3311 #define	reg_ce_centroid_max_6_0_pos 1
3312 #define	reg_ce_centroid_max_6_0_len 7
3313 #define	reg_ce_centroid_max_6_0_lsb 0
3314 #define xd_p_reg_ce_centroid_max_11_7	0xABDE
3315 #define	reg_ce_centroid_max_11_7_pos 0
3316 #define	reg_ce_centroid_max_11_7_len 5
3317 #define	reg_ce_centroid_max_11_7_lsb 7
3318 #define xd_p_reg_ce_var	0xABDF
3319 #define	reg_ce_var_pos 0
3320 #define	reg_ce_var_len 3
3321 #define	reg_ce_var_lsb 0
3322 #define xd_p_reg_ce_fctrl_rdy	0xABDF
3323 #define	reg_ce_fctrl_rdy_pos 3
3324 #define	reg_ce_fctrl_rdy_len 1
3325 #define	reg_ce_fctrl_rdy_lsb 0
3326 #define xd_p_reg_ce_centroid_out_3_0	0xABDF
3327 #define	reg_ce_centroid_out_3_0_pos 4
3328 #define	reg_ce_centroid_out_3_0_len 4
3329 #define	reg_ce_centroid_out_3_0_lsb 0
3330 #define xd_p_reg_ce_centroid_out_11_4	0xABE0
3331 #define	reg_ce_centroid_out_11_4_pos 0
3332 #define	reg_ce_centroid_out_11_4_len 8
3333 #define	reg_ce_centroid_out_11_4_lsb 4
3334 #define xd_p_reg_ce_bias_7_0	0xABE1
3335 #define	reg_ce_bias_7_0_pos 0
3336 #define	reg_ce_bias_7_0_len 8
3337 #define	reg_ce_bias_7_0_lsb 0
3338 #define xd_p_reg_ce_bias_11_8	0xABE2
3339 #define	reg_ce_bias_11_8_pos 0
3340 #define	reg_ce_bias_11_8_len 4
3341 #define	reg_ce_bias_11_8_lsb 8
3342 #define xd_p_reg_ce_m1_3_0	0xABE2
3343 #define	reg_ce_m1_3_0_pos 4
3344 #define	reg_ce_m1_3_0_len 4
3345 #define	reg_ce_m1_3_0_lsb 0
3346 #define xd_p_reg_ce_m1_11_4	0xABE3
3347 #define	reg_ce_m1_11_4_pos 0
3348 #define	reg_ce_m1_11_4_len 8
3349 #define	reg_ce_m1_11_4_lsb 4
3350 #define xd_p_reg_ce_rh0_7_0	0xABE4
3351 #define	reg_ce_rh0_7_0_pos 0
3352 #define	reg_ce_rh0_7_0_len 8
3353 #define	reg_ce_rh0_7_0_lsb 0
3354 #define xd_p_reg_ce_rh0_15_8	0xABE5
3355 #define	reg_ce_rh0_15_8_pos 0
3356 #define	reg_ce_rh0_15_8_len 8
3357 #define	reg_ce_rh0_15_8_lsb 8
3358 #define xd_p_reg_ce_rh0_23_16	0xABE6
3359 #define	reg_ce_rh0_23_16_pos 0
3360 #define	reg_ce_rh0_23_16_len 8
3361 #define	reg_ce_rh0_23_16_lsb 16
3362 #define xd_p_reg_ce_rh0_31_24	0xABE7
3363 #define	reg_ce_rh0_31_24_pos 0
3364 #define	reg_ce_rh0_31_24_len 8
3365 #define	reg_ce_rh0_31_24_lsb 24
3366 #define xd_p_reg_ce_rh3_real_7_0	0xABE8
3367 #define	reg_ce_rh3_real_7_0_pos 0
3368 #define	reg_ce_rh3_real_7_0_len 8
3369 #define	reg_ce_rh3_real_7_0_lsb 0
3370 #define xd_p_reg_ce_rh3_real_15_8	0xABE9
3371 #define	reg_ce_rh3_real_15_8_pos 0
3372 #define	reg_ce_rh3_real_15_8_len 8
3373 #define	reg_ce_rh3_real_15_8_lsb 8
3374 #define xd_p_reg_ce_rh3_real_23_16	0xABEA
3375 #define	reg_ce_rh3_real_23_16_pos 0
3376 #define	reg_ce_rh3_real_23_16_len 8
3377 #define	reg_ce_rh3_real_23_16_lsb 16
3378 #define xd_p_reg_ce_rh3_real_31_24	0xABEB
3379 #define	reg_ce_rh3_real_31_24_pos 0
3380 #define	reg_ce_rh3_real_31_24_len 8
3381 #define	reg_ce_rh3_real_31_24_lsb 24
3382 #define xd_p_reg_ce_rh3_imag_7_0	0xABEC
3383 #define	reg_ce_rh3_imag_7_0_pos 0
3384 #define	reg_ce_rh3_imag_7_0_len 8
3385 #define	reg_ce_rh3_imag_7_0_lsb 0
3386 #define xd_p_reg_ce_rh3_imag_15_8	0xABED
3387 #define	reg_ce_rh3_imag_15_8_pos 0
3388 #define	reg_ce_rh3_imag_15_8_len 8
3389 #define	reg_ce_rh3_imag_15_8_lsb 8
3390 #define xd_p_reg_ce_rh3_imag_23_16	0xABEE
3391 #define	reg_ce_rh3_imag_23_16_pos 0
3392 #define	reg_ce_rh3_imag_23_16_len 8
3393 #define	reg_ce_rh3_imag_23_16_lsb 16
3394 #define xd_p_reg_ce_rh3_imag_31_24	0xABEF
3395 #define	reg_ce_rh3_imag_31_24_pos 0
3396 #define	reg_ce_rh3_imag_31_24_len 8
3397 #define	reg_ce_rh3_imag_31_24_lsb 24
3398 #define xd_p_reg_feq_fix_eh2_7_0	0xABF0
3399 #define	reg_feq_fix_eh2_7_0_pos 0
3400 #define	reg_feq_fix_eh2_7_0_len 8
3401 #define	reg_feq_fix_eh2_7_0_lsb 0
3402 #define xd_p_reg_feq_fix_eh2_15_8	0xABF1
3403 #define	reg_feq_fix_eh2_15_8_pos 0
3404 #define	reg_feq_fix_eh2_15_8_len 8
3405 #define	reg_feq_fix_eh2_15_8_lsb 8
3406 #define xd_p_reg_feq_fix_eh2_23_16	0xABF2
3407 #define	reg_feq_fix_eh2_23_16_pos 0
3408 #define	reg_feq_fix_eh2_23_16_len 8
3409 #define	reg_feq_fix_eh2_23_16_lsb 16
3410 #define xd_p_reg_feq_fix_eh2_31_24	0xABF3
3411 #define	reg_feq_fix_eh2_31_24_pos 0
3412 #define	reg_feq_fix_eh2_31_24_len 8
3413 #define	reg_feq_fix_eh2_31_24_lsb 24
3414 #define xd_p_reg_ce_m2_central_7_0	0xABF4
3415 #define	reg_ce_m2_central_7_0_pos 0
3416 #define	reg_ce_m2_central_7_0_len 8
3417 #define	reg_ce_m2_central_7_0_lsb 0
3418 #define xd_p_reg_ce_m2_central_15_8	0xABF5
3419 #define	reg_ce_m2_central_15_8_pos 0
3420 #define	reg_ce_m2_central_15_8_len 8
3421 #define	reg_ce_m2_central_15_8_lsb 8
3422 #define xd_p_reg_ce_fftshift	0xABF6
3423 #define	reg_ce_fftshift_pos 0
3424 #define	reg_ce_fftshift_len 4
3425 #define	reg_ce_fftshift_lsb 0
3426 #define xd_p_reg_ce_fftshift1	0xABF6
3427 #define	reg_ce_fftshift1_pos 4
3428 #define	reg_ce_fftshift1_len 4
3429 #define	reg_ce_fftshift1_lsb 0
3430 #define xd_p_reg_ce_fftshift2	0xABF7
3431 #define	reg_ce_fftshift2_pos 0
3432 #define	reg_ce_fftshift2_len 4
3433 #define	reg_ce_fftshift2_lsb 0
3434 #define xd_p_reg_ce_top_mobile	0xABF7
3435 #define	reg_ce_top_mobile_pos 4
3436 #define	reg_ce_top_mobile_len 1
3437 #define	reg_ce_top_mobile_lsb 0
3438 #define xd_p_reg_strong_sginal_detected 0xA2BC
3439 #define reg_strong_sginal_detected_pos 2
3440 #define reg_strong_sginal_detected_len 1
3441 #define reg_strong_sginal_detected_lsb 0
3442 
3443 #define XD_MP2IF_BASE                           0xB000
3444 #define XD_MP2IF_CSR                        (0x00 + XD_MP2IF_BASE)
3445 #define XD_MP2IF_DMX_CTRL                       (0x03 + XD_MP2IF_BASE)
3446 #define XD_MP2IF_PID_IDX                        (0x04 + XD_MP2IF_BASE)
3447 #define XD_MP2IF_PID_DATA_L                     (0x05 + XD_MP2IF_BASE)
3448 #define XD_MP2IF_PID_DATA_H                     (0x06 + XD_MP2IF_BASE)
3449 #define XD_MP2IF_MISC                       (0x07 + XD_MP2IF_BASE)
3450 
3451 extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d);
3452 extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg,
3453 				     u8 * value);
3454 extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
3455 				      u8 * values, int len);
3456 extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg,
3457 				      u8 value);
3458 extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
3459 				       u8 * values, int len);
3460 extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg,
3461 				       u8 addr, u8 * values, int len);
3462 extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
3463 					u8 * values, int len);
3464 extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg,
3465 				     u8 pos, u8 len, u8 * value);
3466 extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg,
3467 				      u8 pos, u8 len, u8 value);
3468 extern int af9005_send_command(struct dvb_usb_device *d, u8 command,
3469 			       u8 * wbuf, int wlen, u8 * rbuf, int rlen);
3470 extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address,
3471 			      u8 * values, int len);
3472 extern int af9005_tuner_attach(struct dvb_usb_adapter *adap);
3473 extern int af9005_led_control(struct dvb_usb_device *d, int onoff);
3474 
3475 extern u8 regmask[8];
3476 
3477 /* remote control decoder */
3478 extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len,
3479 			    u32 * event, int *state);
3480 extern struct rc_map_table rc_map_af9005_table[];
3481 extern int rc_map_af9005_table_size;
3482 
3483 #endif
3484