1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Fusb300 UDC (USB gadget)
4  *
5  * Copyright (C) 2010 Faraday Technology Corp.
6  *
7  * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
8  */
9 
10 
11 #ifndef __FUSB300_UDC_H__
12 #define __FUSB300_UDC_H__
13 
14 #include <linux/kernel.h>
15 
16 #define FUSB300_OFFSET_GCR		0x00
17 #define FUSB300_OFFSET_GTM		0x04
18 #define FUSB300_OFFSET_DAR		0x08
19 #define FUSB300_OFFSET_CSR		0x0C
20 #define FUSB300_OFFSET_CXPORT		0x10
21 #define FUSB300_OFFSET_EPSET0(n)	(0x20 + (n - 1) * 0x30)
22 #define FUSB300_OFFSET_EPSET1(n)	(0x24 + (n - 1) * 0x30)
23 #define FUSB300_OFFSET_EPSET2(n)	(0x28 + (n - 1) * 0x30)
24 #define FUSB300_OFFSET_EPFFR(n)		(0x2c + (n - 1) * 0x30)
25 #define FUSB300_OFFSET_EPSTRID(n)	(0x40 + (n - 1) * 0x30)
26 #define FUSB300_OFFSET_HSPTM		0x300
27 #define FUSB300_OFFSET_HSCR		0x304
28 #define FUSB300_OFFSET_SSCR0		0x308
29 #define FUSB300_OFFSET_SSCR1		0x30C
30 #define FUSB300_OFFSET_TT		0x310
31 #define FUSB300_OFFSET_DEVNOTF		0x314
32 #define FUSB300_OFFSET_DNC1		0x318
33 #define FUSB300_OFFSET_CS		0x31C
34 #define FUSB300_OFFSET_SOF		0x324
35 #define FUSB300_OFFSET_EFCS		0x328
36 #define FUSB300_OFFSET_IGR0		0x400
37 #define FUSB300_OFFSET_IGR1		0x404
38 #define FUSB300_OFFSET_IGR2		0x408
39 #define FUSB300_OFFSET_IGR3		0x40C
40 #define FUSB300_OFFSET_IGR4		0x410
41 #define FUSB300_OFFSET_IGR5		0x414
42 #define FUSB300_OFFSET_IGER0		0x420
43 #define FUSB300_OFFSET_IGER1		0x424
44 #define FUSB300_OFFSET_IGER2		0x428
45 #define FUSB300_OFFSET_IGER3		0x42C
46 #define FUSB300_OFFSET_IGER4		0x430
47 #define FUSB300_OFFSET_IGER5		0x434
48 #define FUSB300_OFFSET_DMAHMER		0x500
49 #define FUSB300_OFFSET_EPPRDRDY		0x504
50 #define FUSB300_OFFSET_DMAEPMR		0x508
51 #define FUSB300_OFFSET_DMAENR		0x50C
52 #define FUSB300_OFFSET_DMAAPR		0x510
53 #define FUSB300_OFFSET_AHBCR		0x514
54 #define FUSB300_OFFSET_EPPRD_W0(n)	(0x520 + (n - 1) * 0x10)
55 #define FUSB300_OFFSET_EPPRD_W1(n)	(0x524 + (n - 1) * 0x10)
56 #define FUSB300_OFFSET_EPPRD_W2(n)	(0x528 + (n - 1) * 0x10)
57 #define FUSB300_OFFSET_EPRD_PTR(n)	(0x52C + (n - 1) * 0x10)
58 #define FUSB300_OFFSET_BUFDBG_START	0x800
59 #define FUSB300_OFFSET_BUFDBG_END	0xBFC
60 #define FUSB300_OFFSET_EPPORT(n)	(0x1010 + (n - 1) * 0x10)
61 
62 /*
63  * *	Global Control Register (offset = 000H)
64  * */
65 #define FUSB300_GCR_SF_RST		(1 << 8)
66 #define FUSB300_GCR_VBUS_STATUS		(1 << 7)
67 #define FUSB300_GCR_FORCE_HS_SUSP	(1 << 6)
68 #define FUSB300_GCR_SYNC_FIFO1_CLR	(1 << 5)
69 #define FUSB300_GCR_SYNC_FIFO0_CLR	(1 << 4)
70 #define FUSB300_GCR_FIFOCLR		(1 << 3)
71 #define FUSB300_GCR_GLINTEN		(1 << 2)
72 #define FUSB300_GCR_DEVEN_FS		0x3
73 #define FUSB300_GCR_DEVEN_HS		0x2
74 #define FUSB300_GCR_DEVEN_SS		0x1
75 #define FUSB300_GCR_DEVDIS		0x0
76 #define FUSB300_GCR_DEVEN_MSK		0x3
77 
78 
79 /*
80  * *Global Test Mode (offset = 004H)
81  * */
82 #define FUSB300_GTM_TST_DIS_SOFGEN	(1 << 16)
83 #define FUSB300_GTM_TST_CUR_EP_ENTRY(n)	((n & 0xF) << 12)
84 #define FUSB300_GTM_TST_EP_ENTRY(n)	((n & 0xF) << 8)
85 #define FUSB300_GTM_TST_EP_NUM(n)	((n & 0xF) << 4)
86 #define FUSB300_GTM_TST_FIFO_DEG	(1 << 1)
87 #define FUSB300_GTM_TSTMODE		(1 << 0)
88 
89 /*
90  * * Device Address Register (offset = 008H)
91  * */
92 #define FUSB300_DAR_SETCONFG	(1 << 7)
93 #define FUSB300_DAR_DRVADDR(x)	(x & 0x7F)
94 #define FUSB300_DAR_DRVADDR_MSK	0x7F
95 
96 /*
97  * *Control Transfer Configuration and Status Register
98  * (CX_Config_Status, offset = 00CH)
99  * */
100 #define FUSB300_CSR_LEN(x)	((x & 0xFFFF) << 8)
101 #define FUSB300_CSR_LEN_MSK	(0xFFFF << 8)
102 #define FUSB300_CSR_EMP		(1 << 4)
103 #define FUSB300_CSR_FUL		(1 << 3)
104 #define FUSB300_CSR_CLR		(1 << 2)
105 #define FUSB300_CSR_STL		(1 << 1)
106 #define FUSB300_CSR_DONE	(1 << 0)
107 
108 /*
109  * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
110  * */
111 #define FUSB300_EPSET0_STL_CLR		(1 << 3)
112 #define FUSB300_EPSET0_CLRSEQNUM	(1 << 2)
113 #define FUSB300_EPSET0_STL		(1 << 0)
114 
115 /*
116  * * EPn Setting 1 (EPn_SET1, offset = 024H+(n-1)*30H, n=1~15)
117  * */
118 #define FUSB300_EPSET1_START_ENTRY(x)	((x & 0xFF) << 24)
119 #define FUSB300_EPSET1_START_ENTRY_MSK	(0xFF << 24)
120 #define FUSB300_EPSET1_FIFOENTRY(x)	((x & 0x1F) << 12)
121 #define FUSB300_EPSET1_FIFOENTRY_MSK	(0x1f << 12)
122 #define FUSB300_EPSET1_INTERVAL(x)	((x & 0x7) << 6)
123 #define FUSB300_EPSET1_BWNUM(x)		((x & 0x3) << 4)
124 #define FUSB300_EPSET1_TYPEISO		(1 << 2)
125 #define FUSB300_EPSET1_TYPEBLK		(2 << 2)
126 #define FUSB300_EPSET1_TYPEINT		(3 << 2)
127 #define FUSB300_EPSET1_TYPE(x)		((x & 0x3) << 2)
128 #define FUSB300_EPSET1_TYPE_MSK		(0x3 << 2)
129 #define FUSB300_EPSET1_DIROUT		(0 << 1)
130 #define FUSB300_EPSET1_DIRIN		(1 << 1)
131 #define FUSB300_EPSET1_DIR(x)		((x & 0x1) << 1)
132 #define FUSB300_EPSET1_DIRIN		(1 << 1)
133 #define FUSB300_EPSET1_DIR_MSK		((0x1) << 1)
134 #define FUSB300_EPSET1_ACTDIS		0
135 #define FUSB300_EPSET1_ACTEN		1
136 
137 /*
138  * *EPn Setting 2 (EPn_SET2, offset = 028H+(n-1)*30H, n=1~15)
139  * */
140 #define FUSB300_EPSET2_ADDROFS(x)	((x & 0x7FFF) << 16)
141 #define FUSB300_EPSET2_ADDROFS_MSK	(0x7fff << 16)
142 #define FUSB300_EPSET2_MPS(x)		(x & 0x7FF)
143 #define FUSB300_EPSET2_MPS_MSK		0x7FF
144 
145 /*
146  * * EPn FIFO Register (offset = 2cH+(n-1)*30H)
147  * */
148 #define FUSB300_FFR_RST		(1 << 31)
149 #define FUSB300_FF_FUL		(1 << 30)
150 #define FUSB300_FF_EMPTY	(1 << 29)
151 #define FUSB300_FFR_BYCNT	0x1FFFF
152 
153 /*
154  * *EPn Stream ID (EPn_STR_ID, offset = 040H+(n-1)*30H, n=1~15)
155  * */
156 #define FUSB300_STRID_STREN	(1 << 16)
157 #define FUSB300_STRID_STRID(x)	(x & 0xFFFF)
158 
159 /*
160  * *HS PHY Test Mode (offset = 300H)
161  * */
162 #define FUSB300_HSPTM_TSTPKDONE		(1 << 4)
163 #define FUSB300_HSPTM_TSTPKT		(1 << 3)
164 #define FUSB300_HSPTM_TSTSET0NAK	(1 << 2)
165 #define FUSB300_HSPTM_TSTKSTA		(1 << 1)
166 #define FUSB300_HSPTM_TSTJSTA		(1 << 0)
167 
168 /*
169  * *HS Control Register (offset = 304H)
170  * */
171 #define FUSB300_HSCR_HS_LPM_PERMIT	(1 << 8)
172 #define FUSB300_HSCR_HS_LPM_RMWKUP	(1 << 7)
173 #define FUSB300_HSCR_CAP_LPM_RMWKUP	(1 << 6)
174 #define FUSB300_HSCR_HS_GOSUSP		(1 << 5)
175 #define FUSB300_HSCR_HS_GORMWKU		(1 << 4)
176 #define FUSB300_HSCR_CAP_RMWKUP		(1 << 3)
177 #define FUSB300_HSCR_IDLECNT_0MS	0
178 #define FUSB300_HSCR_IDLECNT_1MS	1
179 #define FUSB300_HSCR_IDLECNT_2MS	2
180 #define FUSB300_HSCR_IDLECNT_3MS	3
181 #define FUSB300_HSCR_IDLECNT_4MS	4
182 #define FUSB300_HSCR_IDLECNT_5MS	5
183 #define FUSB300_HSCR_IDLECNT_6MS	6
184 #define FUSB300_HSCR_IDLECNT_7MS	7
185 
186 /*
187  * * SS Controller Register 0 (offset = 308H)
188  * */
189 #define FUSB300_SSCR0_MAX_INTERVAL(x)	((x & 0x7) << 4)
190 #define FUSB300_SSCR0_U2_FUN_EN		(1 << 1)
191 #define FUSB300_SSCR0_U1_FUN_EN		(1 << 0)
192 
193 /*
194  * * SS Controller Register 1 (offset = 30CH)
195  * */
196 #define FUSB300_SSCR1_GO_U3_DONE	(1 << 8)
197 #define FUSB300_SSCR1_TXDEEMPH_LEVEL	(1 << 7)
198 #define FUSB300_SSCR1_DIS_SCRMB		(1 << 6)
199 #define FUSB300_SSCR1_FORCE_RECOVERY	(1 << 5)
200 #define FUSB300_SSCR1_U3_WAKEUP_EN	(1 << 4)
201 #define FUSB300_SSCR1_U2_EXIT_EN	(1 << 3)
202 #define FUSB300_SSCR1_U1_EXIT_EN	(1 << 2)
203 #define FUSB300_SSCR1_U2_ENTRY_EN	(1 << 1)
204 #define FUSB300_SSCR1_U1_ENTRY_EN	(1 << 0)
205 
206 /*
207  * *SS Controller Register 2  (offset = 310H)
208  * */
209 #define FUSB300_SSCR2_SS_TX_SWING		(1 << 25)
210 #define FUSB300_SSCR2_FORCE_LINKPM_ACCEPT	(1 << 24)
211 #define FUSB300_SSCR2_U2_INACT_TIMEOUT(x)	((x & 0xFF) << 16)
212 #define FUSB300_SSCR2_U1TIMEOUT(x)		((x & 0xFF) << 8)
213 #define FUSB300_SSCR2_U2TIMEOUT(x)		(x & 0xFF)
214 
215 /*
216  * *SS Device Notification Control (DEV_NOTF, offset = 314H)
217  * */
218 #define FUSB300_DEVNOTF_CONTEXT0(x)		((x & 0xFFFFFF) << 8)
219 #define FUSB300_DEVNOTF_TYPE_DIS		0
220 #define FUSB300_DEVNOTF_TYPE_FUNCWAKE		1
221 #define FUSB300_DEVNOTF_TYPE_LTM		2
222 #define FUSB300_DEVNOTF_TYPE_BUSINT_ADJMSG	3
223 
224 /*
225  * *BFM Arbiter Priority Register (BFM_ARB offset = 31CH)
226  * */
227 #define FUSB300_BFMARB_ARB_M1	(1 << 3)
228 #define FUSB300_BFMARB_ARB_M0	(1 << 2)
229 #define FUSB300_BFMARB_ARB_S1	(1 << 1)
230 #define FUSB300_BFMARB_ARB_S0	1
231 
232 /*
233  * *Vendor Specific IO Control Register (offset = 320H)
234  * */
235 #define FUSB300_VSIC_VCTLOAD_N	(1 << 8)
236 #define FUSB300_VSIC_VCTL(x)	(x & 0x3F)
237 
238 /*
239  * *SOF Mask Timer (offset = 324H)
240  * */
241 #define FUSB300_SOF_MASK_TIMER_HS	0x044c
242 #define FUSB300_SOF_MASK_TIMER_FS	0x2710
243 
244 /*
245  * *Error Flag and Control Status (offset = 328H)
246  * */
247 #define FUSB300_EFCS_PM_STATE_U3	3
248 #define FUSB300_EFCS_PM_STATE_U2	2
249 #define FUSB300_EFCS_PM_STATE_U1	1
250 #define FUSB300_EFCS_PM_STATE_U0	0
251 
252 /*
253  * *Interrupt Group 0 Register (offset = 400H)
254  * */
255 #define FUSB300_IGR0_EP15_PRD_INT	(1 << 31)
256 #define FUSB300_IGR0_EP14_PRD_INT	(1 << 30)
257 #define FUSB300_IGR0_EP13_PRD_INT	(1 << 29)
258 #define FUSB300_IGR0_EP12_PRD_INT	(1 << 28)
259 #define FUSB300_IGR0_EP11_PRD_INT	(1 << 27)
260 #define FUSB300_IGR0_EP10_PRD_INT	(1 << 26)
261 #define FUSB300_IGR0_EP9_PRD_INT	(1 << 25)
262 #define FUSB300_IGR0_EP8_PRD_INT	(1 << 24)
263 #define FUSB300_IGR0_EP7_PRD_INT	(1 << 23)
264 #define FUSB300_IGR0_EP6_PRD_INT	(1 << 22)
265 #define FUSB300_IGR0_EP5_PRD_INT	(1 << 21)
266 #define FUSB300_IGR0_EP4_PRD_INT	(1 << 20)
267 #define FUSB300_IGR0_EP3_PRD_INT	(1 << 19)
268 #define FUSB300_IGR0_EP2_PRD_INT	(1 << 18)
269 #define FUSB300_IGR0_EP1_PRD_INT	(1 << 17)
270 #define FUSB300_IGR0_EPn_PRD_INT(n)	(1 << (n + 16))
271 
272 #define FUSB300_IGR0_EP15_FIFO_INT	(1 << 15)
273 #define FUSB300_IGR0_EP14_FIFO_INT	(1 << 14)
274 #define FUSB300_IGR0_EP13_FIFO_INT	(1 << 13)
275 #define FUSB300_IGR0_EP12_FIFO_INT	(1 << 12)
276 #define FUSB300_IGR0_EP11_FIFO_INT	(1 << 11)
277 #define FUSB300_IGR0_EP10_FIFO_INT	(1 << 10)
278 #define FUSB300_IGR0_EP9_FIFO_INT	(1 << 9)
279 #define FUSB300_IGR0_EP8_FIFO_INT	(1 << 8)
280 #define FUSB300_IGR0_EP7_FIFO_INT	(1 << 7)
281 #define FUSB300_IGR0_EP6_FIFO_INT	(1 << 6)
282 #define FUSB300_IGR0_EP5_FIFO_INT	(1 << 5)
283 #define FUSB300_IGR0_EP4_FIFO_INT	(1 << 4)
284 #define FUSB300_IGR0_EP3_FIFO_INT	(1 << 3)
285 #define FUSB300_IGR0_EP2_FIFO_INT	(1 << 2)
286 #define FUSB300_IGR0_EP1_FIFO_INT	(1 << 1)
287 #define FUSB300_IGR0_EPn_FIFO_INT(n)	(1 << n)
288 
289 /*
290  * *Interrupt Group 1 Register (offset = 404H)
291  * */
292 #define FUSB300_IGR1_INTGRP5		(1 << 31)
293 #define FUSB300_IGR1_VBUS_CHG_INT	(1 << 30)
294 #define FUSB300_IGR1_SYNF1_EMPTY_INT	(1 << 29)
295 #define FUSB300_IGR1_SYNF0_EMPTY_INT	(1 << 28)
296 #define FUSB300_IGR1_U3_EXIT_FAIL_INT	(1 << 27)
297 #define FUSB300_IGR1_U2_EXIT_FAIL_INT	(1 << 26)
298 #define FUSB300_IGR1_U1_EXIT_FAIL_INT	(1 << 25)
299 #define FUSB300_IGR1_U2_ENTRY_FAIL_INT	(1 << 24)
300 #define FUSB300_IGR1_U1_ENTRY_FAIL_INT	(1 << 23)
301 #define FUSB300_IGR1_U3_EXIT_INT	(1 << 22)
302 #define FUSB300_IGR1_U2_EXIT_INT	(1 << 21)
303 #define FUSB300_IGR1_U1_EXIT_INT	(1 << 20)
304 #define FUSB300_IGR1_U3_ENTRY_INT	(1 << 19)
305 #define FUSB300_IGR1_U2_ENTRY_INT	(1 << 18)
306 #define FUSB300_IGR1_U1_ENTRY_INT	(1 << 17)
307 #define FUSB300_IGR1_HOT_RST_INT	(1 << 16)
308 #define FUSB300_IGR1_WARM_RST_INT	(1 << 15)
309 #define FUSB300_IGR1_RESM_INT		(1 << 14)
310 #define FUSB300_IGR1_SUSP_INT		(1 << 13)
311 #define FUSB300_IGR1_HS_LPM_INT		(1 << 12)
312 #define FUSB300_IGR1_USBRST_INT		(1 << 11)
313 #define FUSB300_IGR1_DEV_MODE_CHG_INT	(1 << 9)
314 #define FUSB300_IGR1_CX_COMABT_INT	(1 << 8)
315 #define FUSB300_IGR1_CX_COMFAIL_INT	(1 << 7)
316 #define FUSB300_IGR1_CX_CMDEND_INT	(1 << 6)
317 #define FUSB300_IGR1_CX_OUT_INT		(1 << 5)
318 #define FUSB300_IGR1_CX_IN_INT		(1 << 4)
319 #define FUSB300_IGR1_CX_SETUP_INT	(1 << 3)
320 #define FUSB300_IGR1_INTGRP4		(1 << 2)
321 #define FUSB300_IGR1_INTGRP3		(1 << 1)
322 #define FUSB300_IGR1_INTGRP2		(1 << 0)
323 
324 /*
325  * *Interrupt Group 2 Register (offset = 408H)
326  * */
327 #define FUSB300_IGR2_EP6_STR_ACCEPT_INT		(1 << 29)
328 #define FUSB300_IGR2_EP6_STR_RESUME_INT		(1 << 28)
329 #define FUSB300_IGR2_EP6_STR_REQ_INT		(1 << 27)
330 #define FUSB300_IGR2_EP6_STR_NOTRDY_INT		(1 << 26)
331 #define FUSB300_IGR2_EP6_STR_PRIME_INT		(1 << 25)
332 #define FUSB300_IGR2_EP5_STR_ACCEPT_INT		(1 << 24)
333 #define FUSB300_IGR2_EP5_STR_RESUME_INT		(1 << 23)
334 #define FUSB300_IGR2_EP5_STR_REQ_INT		(1 << 22)
335 #define FUSB300_IGR2_EP5_STR_NOTRDY_INT		(1 << 21)
336 #define FUSB300_IGR2_EP5_STR_PRIME_INT		(1 << 20)
337 #define FUSB300_IGR2_EP4_STR_ACCEPT_INT		(1 << 19)
338 #define FUSB300_IGR2_EP4_STR_RESUME_INT		(1 << 18)
339 #define FUSB300_IGR2_EP4_STR_REQ_INT		(1 << 17)
340 #define FUSB300_IGR2_EP4_STR_NOTRDY_INT		(1 << 16)
341 #define FUSB300_IGR2_EP4_STR_PRIME_INT		(1 << 15)
342 #define FUSB300_IGR2_EP3_STR_ACCEPT_INT		(1 << 14)
343 #define FUSB300_IGR2_EP3_STR_RESUME_INT		(1 << 13)
344 #define FUSB300_IGR2_EP3_STR_REQ_INT		(1 << 12)
345 #define FUSB300_IGR2_EP3_STR_NOTRDY_INT		(1 << 11)
346 #define FUSB300_IGR2_EP3_STR_PRIME_INT		(1 << 10)
347 #define FUSB300_IGR2_EP2_STR_ACCEPT_INT		(1 << 9)
348 #define FUSB300_IGR2_EP2_STR_RESUME_INT		(1 << 8)
349 #define FUSB300_IGR2_EP2_STR_REQ_INT		(1 << 7)
350 #define FUSB300_IGR2_EP2_STR_NOTRDY_INT		(1 << 6)
351 #define FUSB300_IGR2_EP2_STR_PRIME_INT		(1 << 5)
352 #define FUSB300_IGR2_EP1_STR_ACCEPT_INT		(1 << 4)
353 #define FUSB300_IGR2_EP1_STR_RESUME_INT		(1 << 3)
354 #define FUSB300_IGR2_EP1_STR_REQ_INT		(1 << 2)
355 #define FUSB300_IGR2_EP1_STR_NOTRDY_INT		(1 << 1)
356 #define FUSB300_IGR2_EP1_STR_PRIME_INT		(1 << 0)
357 
358 #define FUSB300_IGR2_EP_STR_ACCEPT_INT(n)	(1 << (5 * n - 1))
359 #define FUSB300_IGR2_EP_STR_RESUME_INT(n)	(1 << (5 * n - 2))
360 #define FUSB300_IGR2_EP_STR_REQ_INT(n)		(1 << (5 * n - 3))
361 #define FUSB300_IGR2_EP_STR_NOTRDY_INT(n)	(1 << (5 * n - 4))
362 #define FUSB300_IGR2_EP_STR_PRIME_INT(n)	(1 << (5 * n - 5))
363 
364 /*
365  * *Interrupt Group 3 Register (offset = 40CH)
366  * */
367 #define FUSB300_IGR3_EP12_STR_ACCEPT_INT	(1 << 29)
368 #define FUSB300_IGR3_EP12_STR_RESUME_INT	(1 << 28)
369 #define FUSB300_IGR3_EP12_STR_REQ_INT		(1 << 27)
370 #define FUSB300_IGR3_EP12_STR_NOTRDY_INT	(1 << 26)
371 #define FUSB300_IGR3_EP12_STR_PRIME_INT		(1 << 25)
372 #define FUSB300_IGR3_EP11_STR_ACCEPT_INT	(1 << 24)
373 #define FUSB300_IGR3_EP11_STR_RESUME_INT	(1 << 23)
374 #define FUSB300_IGR3_EP11_STR_REQ_INT		(1 << 22)
375 #define FUSB300_IGR3_EP11_STR_NOTRDY_INT	(1 << 21)
376 #define FUSB300_IGR3_EP11_STR_PRIME_INT		(1 << 20)
377 #define FUSB300_IGR3_EP10_STR_ACCEPT_INT	(1 << 19)
378 #define FUSB300_IGR3_EP10_STR_RESUME_INT	(1 << 18)
379 #define FUSB300_IGR3_EP10_STR_REQ_INT		(1 << 17)
380 #define FUSB300_IGR3_EP10_STR_NOTRDY_INT	(1 << 16)
381 #define FUSB300_IGR3_EP10_STR_PRIME_INT		(1 << 15)
382 #define FUSB300_IGR3_EP9_STR_ACCEPT_INT		(1 << 14)
383 #define FUSB300_IGR3_EP9_STR_RESUME_INT		(1 << 13)
384 #define FUSB300_IGR3_EP9_STR_REQ_INT		(1 << 12)
385 #define FUSB300_IGR3_EP9_STR_NOTRDY_INT		(1 << 11)
386 #define FUSB300_IGR3_EP9_STR_PRIME_INT		(1 << 10)
387 #define FUSB300_IGR3_EP8_STR_ACCEPT_INT		(1 << 9)
388 #define FUSB300_IGR3_EP8_STR_RESUME_INT		(1 << 8)
389 #define FUSB300_IGR3_EP8_STR_REQ_INT		(1 << 7)
390 #define FUSB300_IGR3_EP8_STR_NOTRDY_INT		(1 << 6)
391 #define FUSB300_IGR3_EP8_STR_PRIME_INT		(1 << 5)
392 #define FUSB300_IGR3_EP7_STR_ACCEPT_INT		(1 << 4)
393 #define FUSB300_IGR3_EP7_STR_RESUME_INT		(1 << 3)
394 #define FUSB300_IGR3_EP7_STR_REQ_INT		(1 << 2)
395 #define FUSB300_IGR3_EP7_STR_NOTRDY_INT		(1 << 1)
396 #define FUSB300_IGR3_EP7_STR_PRIME_INT		(1 << 0)
397 
398 #define FUSB300_IGR3_EP_STR_ACCEPT_INT(n)	(1 << (5 * (n - 6) - 1))
399 #define FUSB300_IGR3_EP_STR_RESUME_INT(n)	(1 << (5 * (n - 6) - 2))
400 #define FUSB300_IGR3_EP_STR_REQ_INT(n)		(1 << (5 * (n - 6) - 3))
401 #define FUSB300_IGR3_EP_STR_NOTRDY_INT(n)	(1 << (5 * (n - 6) - 4))
402 #define FUSB300_IGR3_EP_STR_PRIME_INT(n)	(1 << (5 * (n - 6) - 5))
403 
404 /*
405  * *Interrupt Group 4 Register (offset = 410H)
406  * */
407 #define FUSB300_IGR4_EP15_RX0_INT		(1 << 31)
408 #define FUSB300_IGR4_EP14_RX0_INT		(1 << 30)
409 #define FUSB300_IGR4_EP13_RX0_INT		(1 << 29)
410 #define FUSB300_IGR4_EP12_RX0_INT		(1 << 28)
411 #define FUSB300_IGR4_EP11_RX0_INT		(1 << 27)
412 #define FUSB300_IGR4_EP10_RX0_INT		(1 << 26)
413 #define FUSB300_IGR4_EP9_RX0_INT		(1 << 25)
414 #define FUSB300_IGR4_EP8_RX0_INT		(1 << 24)
415 #define FUSB300_IGR4_EP7_RX0_INT		(1 << 23)
416 #define FUSB300_IGR4_EP6_RX0_INT		(1 << 22)
417 #define FUSB300_IGR4_EP5_RX0_INT		(1 << 21)
418 #define FUSB300_IGR4_EP4_RX0_INT		(1 << 20)
419 #define FUSB300_IGR4_EP3_RX0_INT		(1 << 19)
420 #define FUSB300_IGR4_EP2_RX0_INT		(1 << 18)
421 #define FUSB300_IGR4_EP1_RX0_INT		(1 << 17)
422 #define FUSB300_IGR4_EP_RX0_INT(x)		(1 << (x + 16))
423 #define FUSB300_IGR4_EP15_STR_ACCEPT_INT	(1 << 14)
424 #define FUSB300_IGR4_EP15_STR_RESUME_INT	(1 << 13)
425 #define FUSB300_IGR4_EP15_STR_REQ_INT		(1 << 12)
426 #define FUSB300_IGR4_EP15_STR_NOTRDY_INT	(1 << 11)
427 #define FUSB300_IGR4_EP15_STR_PRIME_INT		(1 << 10)
428 #define FUSB300_IGR4_EP14_STR_ACCEPT_INT	(1 << 9)
429 #define FUSB300_IGR4_EP14_STR_RESUME_INT	(1 << 8)
430 #define FUSB300_IGR4_EP14_STR_REQ_INT		(1 << 7)
431 #define FUSB300_IGR4_EP14_STR_NOTRDY_INT	(1 << 6)
432 #define FUSB300_IGR4_EP14_STR_PRIME_INT		(1 << 5)
433 #define FUSB300_IGR4_EP13_STR_ACCEPT_INT	(1 << 4)
434 #define FUSB300_IGR4_EP13_STR_RESUME_INT	(1 << 3)
435 #define FUSB300_IGR4_EP13_STR_REQ_INT		(1 << 2)
436 #define FUSB300_IGR4_EP13_STR_NOTRDY_INT	(1 << 1)
437 #define FUSB300_IGR4_EP13_STR_PRIME_INT		(1 << 0)
438 
439 #define FUSB300_IGR4_EP_STR_ACCEPT_INT(n)	(1 << (5 * (n - 12) - 1))
440 #define FUSB300_IGR4_EP_STR_RESUME_INT(n)	(1 << (5 * (n - 12) - 2))
441 #define FUSB300_IGR4_EP_STR_REQ_INT(n)		(1 << (5 * (n - 12) - 3))
442 #define FUSB300_IGR4_EP_STR_NOTRDY_INT(n)	(1 << (5 * (n - 12) - 4))
443 #define FUSB300_IGR4_EP_STR_PRIME_INT(n)	(1 << (5 * (n - 12) - 5))
444 
445 /*
446  * *Interrupt Group 5 Register (offset = 414H)
447  * */
448 #define FUSB300_IGR5_EP_STL_INT(n)	(1 << n)
449 
450 /*
451  * *Interrupt Enable Group 0 Register (offset = 420H)
452  * */
453 #define FUSB300_IGER0_EEP15_PRD_INT	(1 << 31)
454 #define FUSB300_IGER0_EEP14_PRD_INT	(1 << 30)
455 #define FUSB300_IGER0_EEP13_PRD_INT	(1 << 29)
456 #define FUSB300_IGER0_EEP12_PRD_INT	(1 << 28)
457 #define FUSB300_IGER0_EEP11_PRD_INT	(1 << 27)
458 #define FUSB300_IGER0_EEP10_PRD_INT	(1 << 26)
459 #define FUSB300_IGER0_EEP9_PRD_INT	(1 << 25)
460 #define FUSB300_IGER0_EP8_PRD_INT	(1 << 24)
461 #define FUSB300_IGER0_EEP7_PRD_INT	(1 << 23)
462 #define FUSB300_IGER0_EEP6_PRD_INT	(1 << 22)
463 #define FUSB300_IGER0_EEP5_PRD_INT	(1 << 21)
464 #define FUSB300_IGER0_EEP4_PRD_INT	(1 << 20)
465 #define FUSB300_IGER0_EEP3_PRD_INT	(1 << 19)
466 #define FUSB300_IGER0_EEP2_PRD_INT	(1 << 18)
467 #define FUSB300_IGER0_EEP1_PRD_INT	(1 << 17)
468 #define FUSB300_IGER0_EEPn_PRD_INT(n)	(1 << (n + 16))
469 
470 #define FUSB300_IGER0_EEP15_FIFO_INT	(1 << 15)
471 #define FUSB300_IGER0_EEP14_FIFO_INT	(1 << 14)
472 #define FUSB300_IGER0_EEP13_FIFO_INT	(1 << 13)
473 #define FUSB300_IGER0_EEP12_FIFO_INT	(1 << 12)
474 #define FUSB300_IGER0_EEP11_FIFO_INT	(1 << 11)
475 #define FUSB300_IGER0_EEP10_FIFO_INT	(1 << 10)
476 #define FUSB300_IGER0_EEP9_FIFO_INT	(1 << 9)
477 #define FUSB300_IGER0_EEP8_FIFO_INT	(1 << 8)
478 #define FUSB300_IGER0_EEP7_FIFO_INT	(1 << 7)
479 #define FUSB300_IGER0_EEP6_FIFO_INT	(1 << 6)
480 #define FUSB300_IGER0_EEP5_FIFO_INT	(1 << 5)
481 #define FUSB300_IGER0_EEP4_FIFO_INT	(1 << 4)
482 #define FUSB300_IGER0_EEP3_FIFO_INT	(1 << 3)
483 #define FUSB300_IGER0_EEP2_FIFO_INT	(1 << 2)
484 #define FUSB300_IGER0_EEP1_FIFO_INT	(1 << 1)
485 #define FUSB300_IGER0_EEPn_FIFO_INT(n)	(1 << n)
486 
487 /*
488  * *Interrupt Enable Group 1 Register (offset = 424H)
489  * */
490 #define FUSB300_IGER1_EINT_GRP5		(1 << 31)
491 #define FUSB300_IGER1_VBUS_CHG_INT	(1 << 30)
492 #define FUSB300_IGER1_SYNF1_EMPTY_INT	(1 << 29)
493 #define FUSB300_IGER1_SYNF0_EMPTY_INT	(1 << 28)
494 #define FUSB300_IGER1_U3_EXIT_FAIL_INT	(1 << 27)
495 #define FUSB300_IGER1_U2_EXIT_FAIL_INT	(1 << 26)
496 #define FUSB300_IGER1_U1_EXIT_FAIL_INT	(1 << 25)
497 #define FUSB300_IGER1_U2_ENTRY_FAIL_INT	(1 << 24)
498 #define FUSB300_IGER1_U1_ENTRY_FAIL_INT	(1 << 23)
499 #define FUSB300_IGER1_U3_EXIT_INT	(1 << 22)
500 #define FUSB300_IGER1_U2_EXIT_INT	(1 << 21)
501 #define FUSB300_IGER1_U1_EXIT_INT	(1 << 20)
502 #define FUSB300_IGER1_U3_ENTRY_INT	(1 << 19)
503 #define FUSB300_IGER1_U2_ENTRY_INT	(1 << 18)
504 #define FUSB300_IGER1_U1_ENTRY_INT	(1 << 17)
505 #define FUSB300_IGER1_HOT_RST_INT	(1 << 16)
506 #define FUSB300_IGER1_WARM_RST_INT	(1 << 15)
507 #define FUSB300_IGER1_RESM_INT		(1 << 14)
508 #define FUSB300_IGER1_SUSP_INT		(1 << 13)
509 #define FUSB300_IGER1_LPM_INT		(1 << 12)
510 #define FUSB300_IGER1_HS_RST_INT	(1 << 11)
511 #define FUSB300_IGER1_EDEV_MODE_CHG_INT	(1 << 9)
512 #define FUSB300_IGER1_CX_COMABT_INT	(1 << 8)
513 #define FUSB300_IGER1_CX_COMFAIL_INT	(1 << 7)
514 #define FUSB300_IGER1_CX_CMDEND_INT	(1 << 6)
515 #define FUSB300_IGER1_CX_OUT_INT	(1 << 5)
516 #define FUSB300_IGER1_CX_IN_INT		(1 << 4)
517 #define FUSB300_IGER1_CX_SETUP_INT	(1 << 3)
518 #define FUSB300_IGER1_INTGRP4		(1 << 2)
519 #define FUSB300_IGER1_INTGRP3		(1 << 1)
520 #define FUSB300_IGER1_INTGRP2		(1 << 0)
521 
522 /*
523  * *Interrupt Enable Group 2 Register (offset = 428H)
524  * */
525 #define FUSB300_IGER2_EEP_STR_ACCEPT_INT(n)	(1 << (5 * n - 1))
526 #define FUSB300_IGER2_EEP_STR_RESUME_INT(n)	(1 << (5 * n - 2))
527 #define FUSB300_IGER2_EEP_STR_REQ_INT(n)	(1 << (5 * n - 3))
528 #define FUSB300_IGER2_EEP_STR_NOTRDY_INT(n)	(1 << (5 * n - 4))
529 #define FUSB300_IGER2_EEP_STR_PRIME_INT(n)	(1 << (5 * n - 5))
530 
531 /*
532  * *Interrupt Enable Group 3 Register (offset = 42CH)
533  * */
534 
535 #define FUSB300_IGER3_EEP_STR_ACCEPT_INT(n)	(1 << (5 * (n - 6) - 1))
536 #define FUSB300_IGER3_EEP_STR_RESUME_INT(n)	(1 << (5 * (n - 6) - 2))
537 #define FUSB300_IGER3_EEP_STR_REQ_INT(n)	(1 << (5 * (n - 6) - 3))
538 #define FUSB300_IGER3_EEP_STR_NOTRDY_INT(n)	(1 << (5 * (n - 6) - 4))
539 #define FUSB300_IGER3_EEP_STR_PRIME_INT(n)	(1 << (5 * (n - 6) - 5))
540 
541 /*
542  * *Interrupt Enable Group 4 Register (offset = 430H)
543  * */
544 
545 #define FUSB300_IGER4_EEP_RX0_INT(n)		(1 << (n + 16))
546 #define FUSB300_IGER4_EEP_STR_ACCEPT_INT(n)	(1 << (5 * (n - 6) - 1))
547 #define FUSB300_IGER4_EEP_STR_RESUME_INT(n)	(1 << (5 * (n - 6) - 2))
548 #define FUSB300_IGER4_EEP_STR_REQ_INT(n)	(1 << (5 * (n - 6) - 3))
549 #define FUSB300_IGER4_EEP_STR_NOTRDY_INT(n)	(1 << (5 * (n - 6) - 4))
550 #define FUSB300_IGER4_EEP_STR_PRIME_INT(n)	(1 << (5 * (n - 6) - 5))
551 
552 /* EP PRD Ready (EP_PRD_RDY, offset = 504H) */
553 
554 #define FUSB300_EPPRDR_EP15_PRD_RDY		(1 << 15)
555 #define FUSB300_EPPRDR_EP14_PRD_RDY		(1 << 14)
556 #define FUSB300_EPPRDR_EP13_PRD_RDY		(1 << 13)
557 #define FUSB300_EPPRDR_EP12_PRD_RDY		(1 << 12)
558 #define FUSB300_EPPRDR_EP11_PRD_RDY		(1 << 11)
559 #define FUSB300_EPPRDR_EP10_PRD_RDY		(1 << 10)
560 #define FUSB300_EPPRDR_EP9_PRD_RDY		(1 << 9)
561 #define FUSB300_EPPRDR_EP8_PRD_RDY		(1 << 8)
562 #define FUSB300_EPPRDR_EP7_PRD_RDY		(1 << 7)
563 #define FUSB300_EPPRDR_EP6_PRD_RDY		(1 << 6)
564 #define FUSB300_EPPRDR_EP5_PRD_RDY		(1 << 5)
565 #define FUSB300_EPPRDR_EP4_PRD_RDY		(1 << 4)
566 #define FUSB300_EPPRDR_EP3_PRD_RDY		(1 << 3)
567 #define FUSB300_EPPRDR_EP2_PRD_RDY		(1 << 2)
568 #define FUSB300_EPPRDR_EP1_PRD_RDY		(1 << 1)
569 #define FUSB300_EPPRDR_EP_PRD_RDY(n)		(1 << n)
570 
571 /* AHB Bus Control Register (offset = 514H) */
572 #define FUSB300_AHBBCR_S1_SPLIT_ON		(1 << 17)
573 #define FUSB300_AHBBCR_S0_SPLIT_ON		(1 << 16)
574 #define FUSB300_AHBBCR_S1_1entry		(0 << 12)
575 #define FUSB300_AHBBCR_S1_4entry		(3 << 12)
576 #define FUSB300_AHBBCR_S1_8entry		(5 << 12)
577 #define FUSB300_AHBBCR_S1_16entry		(7 << 12)
578 #define FUSB300_AHBBCR_S0_1entry		(0 << 8)
579 #define FUSB300_AHBBCR_S0_4entry		(3 << 8)
580 #define FUSB300_AHBBCR_S0_8entry		(5 << 8)
581 #define FUSB300_AHBBCR_S0_16entry		(7 << 8)
582 #define FUSB300_AHBBCR_M1_BURST_SINGLE		(0 << 4)
583 #define FUSB300_AHBBCR_M1_BURST_INCR		(1 << 4)
584 #define FUSB300_AHBBCR_M1_BURST_INCR4		(3 << 4)
585 #define FUSB300_AHBBCR_M1_BURST_INCR8		(5 << 4)
586 #define FUSB300_AHBBCR_M1_BURST_INCR16		(7 << 4)
587 #define FUSB300_AHBBCR_M0_BURST_SINGLE		0
588 #define FUSB300_AHBBCR_M0_BURST_INCR		1
589 #define FUSB300_AHBBCR_M0_BURST_INCR4		3
590 #define FUSB300_AHBBCR_M0_BURST_INCR8		5
591 #define FUSB300_AHBBCR_M0_BURST_INCR16		7
592 #define FUSB300_IGER5_EEP_STL_INT(n)		(1 << n)
593 
594 /* WORD 0 Data Structure of PRD Table */
595 #define FUSB300_EPPRD0_M			(1 << 30)
596 #define FUSB300_EPPRD0_O			(1 << 29)
597 /* The finished prd */
598 #define FUSB300_EPPRD0_F			(1 << 28)
599 #define FUSB300_EPPRD0_I			(1 << 27)
600 #define FUSB300_EPPRD0_A			(1 << 26)
601 /* To decide HW point to first prd at next time */
602 #define FUSB300_EPPRD0_L			(1 << 25)
603 #define FUSB300_EPPRD0_H			(1 << 24)
604 #define FUSB300_EPPRD0_BTC(n)			(n & 0xFFFFFF)
605 
606 /*----------------------------------------------------------------------*/
607 #define FUSB300_MAX_NUM_EP		16
608 
609 #define FUSB300_FIFO_ENTRY_NUM		8
610 #define FUSB300_MAX_FIFO_ENTRY		8
611 
612 #define SS_CTL_MAX_PACKET_SIZE		0x200
613 #define SS_BULK_MAX_PACKET_SIZE		0x400
614 #define SS_INT_MAX_PACKET_SIZE		0x400
615 #define SS_ISO_MAX_PACKET_SIZE		0x400
616 
617 #define HS_BULK_MAX_PACKET_SIZE		0x200
618 #define HS_CTL_MAX_PACKET_SIZE		0x40
619 #define HS_INT_MAX_PACKET_SIZE		0x400
620 #define HS_ISO_MAX_PACKET_SIZE		0x400
621 
622 struct fusb300_ep_info {
623 	u8	epnum;
624 	u8	type;
625 	u8	interval;
626 	u8	dir_in;
627 	u16	maxpacket;
628 	u16	addrofs;
629 	u16	bw_num;
630 };
631 
632 struct fusb300_request {
633 
634 	struct usb_request	req;
635 	struct list_head	queue;
636 };
637 
638 
639 struct fusb300_ep {
640 	struct usb_ep		ep;
641 	struct fusb300		*fusb300;
642 
643 	struct list_head	queue;
644 	unsigned		stall:1;
645 	unsigned		wedged:1;
646 	unsigned		use_dma:1;
647 
648 	unsigned char		epnum;
649 	unsigned char		type;
650 };
651 
652 struct fusb300 {
653 	spinlock_t		lock;
654 	void __iomem		*reg;
655 
656 	unsigned long		irq_trigger;
657 
658 	struct usb_gadget		gadget;
659 	struct usb_gadget_driver	*driver;
660 
661 	struct fusb300_ep	*ep[FUSB300_MAX_NUM_EP];
662 
663 	struct usb_request	*ep0_req;	/* for internal request */
664 	__le16			ep0_data;
665 	u32			ep0_length;	/* for internal request */
666 	u8			ep0_dir;	/* 0/0x80  out/in */
667 
668 	u8			fifo_entry_num;	/* next start fifo entry */
669 	u32			addrofs;	/* next fifo address offset */
670 	u8			reenum;		/* if re-enumeration */
671 };
672 
673 #define to_fusb300(g)		(container_of((g), struct fusb300, gadget))
674 
675 #endif
676