xref: /openbmc/u-boot/include/faraday/ftahbc020s.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011 Andes Technology Corporation
4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5  */
6 
7 /* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
8 #ifndef __FTAHBC020S_H
9 #define __FTAHBC202S_H
10 
11 /* Registers Offsets */
12 
13 /*
14  * AHB Slave BSR, offset: n * 4, n=0~31
15  */
16 #ifndef __ASSEMBLY__
17 struct ftahbc02s {
18 	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
19 	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
20 	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
21 	unsigned int	cr;		/* 0x88	- Ctrl Reg */
22 };
23 #endif /* __ASSEMBLY__ */
24 
25 /*
26  * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
27  */
28 #define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
29 #define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
30 /* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
31 #define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
32 
33 /*
34  * FTAHBC020S_PCR - Priority Control Register
35  */
36 #define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
37 
38 /*
39  * FTAHBC020S_CR - Interrupt Control Register
40  */
41 #define FTAHBC020S_CR_INTSTS	(1 << 24)
42 #define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
43 #define FTAHBC020S_CR_INTSMASK	(1 << 16)
44 #define FTAHBC020S_CR_REMAP	(1 << 0)
45 
46 #endif	/* __FTAHBC020S_H */
47