1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * LayerScape Internal Memory Map 4 * 5 * Copyright 2017-2019 NXP 6 * Copyright 2014 Freescale Semiconductor, Inc. 7 */ 8 9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ 10 #define __ARCH_FSL_LSCH3_IMMAP_H_ 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) 15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) 17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) 18 #ifdef CONFIG_ARCH_LX2160A 19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) 20 #else 21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) 22 #endif 23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) 24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) 25 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) 26 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) 27 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) 28 #ifndef CONFIG_NXP_LSCH3_2 29 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) 30 #endif 31 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) 32 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) 33 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 34 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 35 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 36 0x18A0) 37 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) 38 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) 39 40 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) 41 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) 42 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) 43 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) 44 45 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL 46 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL 47 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL 48 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL 49 50 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) 51 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) 52 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) 53 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) 54 #ifdef CONFIG_NXP_LSCH3_2 55 #define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) 56 #define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) 57 #define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) 58 #define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) 59 #endif 60 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) 61 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) 62 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) 63 64 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 65 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) 66 67 /* TZ Address Space Controller Definitions */ 68 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 69 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 70 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 71 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 72 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 73 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 74 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 75 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 76 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 77 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 78 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 79 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 80 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 81 82 /* SATA */ 83 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) 84 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) 85 86 /* SFP */ 87 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 88 89 /* SEC */ 90 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull 91 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull 92 #define CONFIG_SYS_FSL_SEC_ADDR \ 93 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 94 #define CONFIG_SYS_FSL_JR0_ADDR \ 95 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 96 97 #ifdef CONFIG_TFABOOT 98 #ifdef CONFIG_NXP_LSCH3_2 99 /* RCW_SRC field in Power-On Reset Control Register 1 */ 100 #define RCW_SRC_MASK 0x07800000 101 #define RCW_SRC_BIT 23 102 103 /* CFG_RCW_SRC[3:0] */ 104 #define RCW_SRC_TYPE_MASK 0x8 105 #define RCW_SRC_ADDR_OFFSET_8MB 0x800000 106 107 /* RCW SRC HARDCODED */ 108 #define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ 109 110 #define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ 111 #define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ 112 #define RCW_SRC_I2C1_VAL 0xa /* 0xa */ 113 #define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ 114 #define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ 115 #define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ 116 #define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ 117 #define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ 118 #else 119 #define RCW_SRC_MASK (0xFF800000) 120 #define RCW_SRC_BIT 23 121 /* CFG_RCW_SRC[6:0] */ 122 #define RCW_SRC_TYPE_MASK (0x70) 123 124 /* RCW SRC HARDCODED */ 125 #define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ 126 /* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ 127 128 /* RCW SRC NOR */ 129 #define RCW_SRC_NOR_VAL (0x20) 130 #define NOR_TYPE_MASK (0x10) 131 #define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ 132 #define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ 133 134 /* RCW SRC Serial Flash 135 * 1. SERIAL NOR (QSPI) 136 * 2. OTHERS (SD/MMC, SPI, I2C1 137 */ 138 #define RCW_SRC_SERIAL_MASK (0x7F) 139 #define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ 140 #define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ 141 #define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ 142 #define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ 143 #endif 144 #endif 145 146 /* Security Monitor */ 147 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 148 149 /* MMU 500 */ 150 #define SMMU_SCR0 (SMMU_BASE + 0x0) 151 #define SMMU_SCR1 (SMMU_BASE + 0x4) 152 #define SMMU_SCR2 (SMMU_BASE + 0x8) 153 #define SMMU_SACR (SMMU_BASE + 0x10) 154 #define SMMU_IDR0 (SMMU_BASE + 0x20) 155 #define SMMU_IDR1 (SMMU_BASE + 0x24) 156 157 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 158 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 159 #define SMMU_NSACR (SMMU_BASE + 0x410) 160 161 #define SCR0_CLIENTPD_MASK 0x00000001 162 #define SCR0_USFCFG_MASK 0x00000400 163 164 165 /* PCIe */ 166 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 167 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 168 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 169 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) 170 #ifdef CONFIG_ARCH_LS1088A 171 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL 172 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL 173 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL 174 #else 175 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL 176 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL 177 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL 178 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL 179 #endif 180 181 /* Device Configuration */ 182 #define DCFG_BASE 0x01e00000 183 #define DCFG_PORSR1 0x000 184 #define DCFG_PORSR1_RCW_SRC 0xff800000 185 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 186 #define DCFG_RCWSR13 0x130 187 #define DCFG_RCWSR13_DSPI (0 << 8) 188 #define DCFG_RCWSR15 0x138 189 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 190 191 #define DCFG_DCSR_BASE 0X700100000ULL 192 #define DCFG_DCSR_PORCR1 0x000 193 194 /* Interrupt Sampling Control */ 195 #define ISC_BASE 0x01F70000 196 #define IRQCR_OFFSET 0x14 197 198 /* Supplemental Configuration */ 199 #define SCFG_BASE 0x01fc0000 200 #define SCFG_USB3PRM1CR 0x000 201 #define SCFG_USB3PRM1CR_INIT 0x27672b2a 202 #define SCFG_USB_TXVREFTUNE 0x9 203 #define SCFG_USB_SQRXTUNE_MASK 0x7 204 #define SCFG_QSPICLKCTLR 0x10 205 206 #define DCSR_BASE 0x700000000ULL 207 #define DCSR_USB_PHY1 0x4600000 208 #define DCSR_USB_PHY2 0x4610000 209 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C 210 #define USB_PHY_RX_EQ_VAL_1 0x0000 211 #define USB_PHY_RX_EQ_VAL_2 0x0080 212 #define USB_PHY_RX_EQ_VAL_3 0x0380 213 #define USB_PHY_RX_EQ_VAL_4 0x0b80 214 215 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 216 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 217 #define TP_ITYP_TYPE_ARM 0x0 218 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 219 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 220 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 221 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 222 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 223 #define TY_ITYP_VER_A7 0x1 224 #define TY_ITYP_VER_A53 0x2 225 #define TY_ITYP_VER_A57 0x3 226 #define TY_ITYP_VER_A72 0x4 227 228 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 229 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 230 #define TP_INIT_PER_CLUSTER 4 231 /* This is chassis generation 3 */ 232 #ifndef __ASSEMBLY__ 233 struct sys_info { 234 unsigned long freq_processor[CONFIG_MAX_CPUS]; 235 /* frequency of platform PLL */ 236 unsigned long freq_systembus; 237 unsigned long freq_ddrbus; 238 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 239 unsigned long freq_ddrbus2; 240 #endif 241 unsigned long freq_localbus; 242 unsigned long freq_qe; 243 #ifdef CONFIG_SYS_DPAA_FMAN 244 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 245 #endif 246 #ifdef CONFIG_SYS_DPAA_QBMAN 247 unsigned long freq_qman; 248 #endif 249 #ifdef CONFIG_SYS_DPAA_PME 250 unsigned long freq_pme; 251 #endif 252 }; 253 254 /* Global Utilities Block */ 255 struct ccsr_gur { 256 u32 porsr1; /* POR status 1 */ 257 u32 porsr2; /* POR status 2 */ 258 u8 res_008[0x20-0x8]; 259 u32 gpporcr1; /* General-purpose POR configuration */ 260 u32 gpporcr2; /* General-purpose POR configuration 2 */ 261 u32 gpporcr3; 262 u32 gpporcr4; 263 u8 res_030[0x60-0x30]; 264 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F 265 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F 266 #if defined(CONFIG_ARCH_LS1088A) 267 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 268 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 269 #else 270 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 271 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 272 #endif 273 u32 dcfg_fusesr; /* Fuse status register */ 274 u8 res_064[0x70-0x64]; 275 u32 devdisr; /* Device disable control 1 */ 276 u32 devdisr2; /* Device disable control 2 */ 277 u32 devdisr3; /* Device disable control 3 */ 278 u32 devdisr4; /* Device disable control 4 */ 279 u32 devdisr5; /* Device disable control 5 */ 280 u32 devdisr6; /* Device disable control 6 */ 281 u8 res_088[0x94-0x88]; 282 u32 coredisr; /* Device disable control 7 */ 283 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 284 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 285 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 286 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 287 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 288 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 289 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 290 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 291 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 292 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 293 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 294 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 295 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 296 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 297 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 298 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 299 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 300 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 301 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 302 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 303 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 304 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 305 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 306 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 307 u8 res_098[0xa0-0x98]; 308 u32 pvr; /* Processor version */ 309 u32 svr; /* System version */ 310 u8 res_0a8[0x100-0xa8]; 311 u32 rcwsr[30]; /* Reset control word status */ 312 313 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 314 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f 315 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 316 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f 317 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 318 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f 319 320 #if defined(CONFIG_ARCH_LS2080A) 321 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 322 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 323 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 324 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 325 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 326 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 327 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 328 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 329 #define FSL_CHASSIS3_SRDS1_REGSR 29 330 #define FSL_CHASSIS3_SRDS2_REGSR 29 331 #elif defined(CONFIG_ARCH_LX2160A) 332 #define FSL_CHASSIS3_EC1_REGSR 27 333 #define FSL_CHASSIS3_EC2_REGSR 27 334 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 335 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 336 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 337 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 338 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 339 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 340 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 341 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 342 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 343 #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 344 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 345 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 346 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 347 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 348 #define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 349 #define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 350 #define FSL_CHASSIS3_SRDS1_REGSR 29 351 #define FSL_CHASSIS3_SRDS2_REGSR 29 352 #define FSL_CHASSIS3_SRDS3_REGSR 29 353 #define FSL_CHASSIS3_RCWSR12_REGSR 12 354 #define FSL_CHASSIS3_RCWSR13_REGSR 13 355 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 356 #define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 357 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 358 #define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 359 #define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 360 #define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 361 #elif defined(CONFIG_ARCH_LS1088A) 362 #define FSL_CHASSIS3_EC1_REGSR 26 363 #define FSL_CHASSIS3_EC2_REGSR 26 364 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 365 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 366 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 367 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 368 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 369 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 370 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF 371 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 372 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 373 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 374 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 375 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 376 #define FSL_CHASSIS3_SRDS1_REGSR 29 377 #define FSL_CHASSIS3_SRDS2_REGSR 30 378 #endif 379 #define RCW_SB_EN_REG_INDEX 9 380 #define RCW_SB_EN_MASK 0x00000400 381 382 u8 res_178[0x200-0x178]; 383 u32 scratchrw[16]; /* Scratch Read/Write */ 384 u8 res_240[0x300-0x240]; 385 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 386 u8 res_310[0x400-0x310]; 387 u32 bootlocptrl; /* Boot location pointer low-order addr */ 388 u32 bootlocptrh; /* Boot location pointer high-order addr */ 389 u8 res_408[0x520-0x408]; 390 u32 usb1_amqr; 391 u32 usb2_amqr; 392 u8 res_528[0x530-0x528]; /* add more registers when needed */ 393 u32 sdmm1_amqr; 394 u8 res_534[0x550-0x534]; /* add more registers when needed */ 395 u32 sata1_amqr; 396 u32 sata2_amqr; 397 u8 res_558[0x570-0x558]; /* add more registers when needed */ 398 u32 misc1_amqr; 399 u8 res_574[0x590-0x574]; /* add more registers when needed */ 400 u32 spare1_amqr; 401 u32 spare2_amqr; 402 u8 res_598[0x620-0x598]; /* add more registers when needed */ 403 u32 gencr[7]; /* General Control Registers */ 404 u8 res_63c[0x640-0x63c]; /* add more registers when needed */ 405 u32 cgensr1; /* Core General Status Register */ 406 u8 res_644[0x660-0x644]; /* add more registers when needed */ 407 u32 cgencr1; /* Core General Control Register */ 408 u8 res_664[0x740-0x664]; /* add more registers when needed */ 409 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 410 struct { 411 u32 upper; 412 u32 lower; 413 } tp_cluster[4]; /* Core cluster n Topology Register */ 414 u8 res_864[0x920-0x864]; /* add more registers when needed */ 415 u32 ioqoscr[8]; /*I/O Quality of Services Register */ 416 u32 uccr; 417 u8 res_944[0x960-0x944]; /* add more registers when needed */ 418 u32 ftmcr; 419 u8 res_964[0x990-0x964]; /* add more registers when needed */ 420 u32 coredisablesr; 421 u8 res_994[0xa00-0x994]; /* add more registers when needed */ 422 u32 sdbgcr; /*Secure Debug Confifuration Register */ 423 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ 424 u32 ipbrr1; 425 u32 ipbrr2; 426 u8 res_858[0x1000-0xc00]; 427 }; 428 429 struct ccsr_clk_cluster_group { 430 struct { 431 u8 res_00[0x10]; 432 u32 csr; 433 u8 res_14[0x20-0x14]; 434 } hwncsr[3]; 435 u8 res_60[0x80-0x60]; 436 struct { 437 u32 gsr; 438 u8 res_84[0xa0-0x84]; 439 } pllngsr[3]; 440 u8 res_e0[0x100-0xe0]; 441 }; 442 443 struct ccsr_clk_ctrl { 444 struct { 445 u32 csr; /* core cluster n clock control status */ 446 u8 res_04[0x20-0x04]; 447 } clkcncsr[8]; 448 }; 449 450 struct ccsr_reset { 451 u32 rstcr; /* 0x000 */ 452 u32 rstcrsp; /* 0x004 */ 453 u8 res_008[0x10-0x08]; /* 0x008 */ 454 u32 rstrqmr1; /* 0x010 */ 455 u32 rstrqmr2; /* 0x014 */ 456 u32 rstrqsr1; /* 0x018 */ 457 u32 rstrqsr2; /* 0x01c */ 458 u32 rstrqwdtmrl; /* 0x020 */ 459 u32 rstrqwdtmru; /* 0x024 */ 460 u8 res_028[0x30-0x28]; /* 0x028 */ 461 u32 rstrqwdtsrl; /* 0x030 */ 462 u32 rstrqwdtsru; /* 0x034 */ 463 u8 res_038[0x60-0x38]; /* 0x038 */ 464 u32 brrl; /* 0x060 */ 465 u32 brru; /* 0x064 */ 466 u8 res_068[0x80-0x68]; /* 0x068 */ 467 u32 pirset; /* 0x080 */ 468 u32 pirclr; /* 0x084 */ 469 u8 res_088[0x90-0x88]; /* 0x088 */ 470 u32 brcorenbr; /* 0x090 */ 471 u8 res_094[0x100-0x94]; /* 0x094 */ 472 u32 rcw_reqr; /* 0x100 */ 473 u32 rcw_completion; /* 0x104 */ 474 u8 res_108[0x110-0x108]; /* 0x108 */ 475 u32 pbi_reqr; /* 0x110 */ 476 u32 pbi_completion; /* 0x114 */ 477 u8 res_118[0xa00-0x118]; /* 0x118 */ 478 u32 qmbm_warmrst; /* 0xa00 */ 479 u32 soc_warmrst; /* 0xa04 */ 480 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ 481 u32 ip_rev1; /* 0xbf8 */ 482 u32 ip_rev2; /* 0xbfc */ 483 }; 484 485 struct ccsr_serdes { 486 struct { 487 u32 rstctl; /* Reset Control Register */ 488 u32 pllcr0; /* PLL Control Register 0 */ 489 u32 pllcr1; /* PLL Control Register 1 */ 490 u32 pllcr2; /* PLL Control Register 2 */ 491 u32 pllcr3; /* PLL Control Register 3 */ 492 u32 pllcr4; /* PLL Control Register 4 */ 493 u32 pllcr5; /* PLL Control Register 5 */ 494 u8 res[0x20 - 0x1c]; 495 } bank[2]; 496 u8 res1[0x90 - 0x40]; 497 u32 srdstcalcr; /* TX Calibration Control */ 498 u32 srdstcalcr1; /* TX Calibration Control1 */ 499 u8 res2[0xa0 - 0x98]; 500 u32 srdsrcalcr; /* RX Calibration Control */ 501 u32 srdsrcalcr1; /* RX Calibration Control1 */ 502 u8 res3[0xb0 - 0xa8]; 503 u32 srdsgr0; /* General Register 0 */ 504 u8 res4[0x800 - 0xb4]; 505 struct serdes_lane { 506 u32 gcr0; /* General Control Register 0 */ 507 u32 gcr1; /* General Control Register 1 */ 508 u32 gcr2; /* General Control Register 2 */ 509 u32 ssc0; /* Speed Switch Control 0 */ 510 u32 rec0; /* Receive Equalization Control 0 */ 511 u32 rec1; /* Receive Equalization Control 1 */ 512 u32 tec0; /* Transmit Equalization Control 0 */ 513 u32 ssc1; /* Speed Switch Control 1 */ 514 u8 res1[0x840 - 0x820]; 515 } lane[8]; 516 u8 res5[0x19fc - 0xa00]; 517 }; 518 519 #endif /*__ASSEMBLY__*/ 520 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ 521