1 /*
2 * SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2023 IBM Corp.
4 *
5 * IBM Flexible Service Interface master
6 */
7
8 #include "qemu/osdep.h"
9 #include "qapi/error.h"
10 #include "qemu/log.h"
11 #include "trace.h"
12
13 #include "hw/fsi/fsi-master.h"
14
15 #define TYPE_OP_BUS "opb"
16
17 #define TO_REG(x) ((x) >> 2)
18
19 #define FSI_MENP0 TO_REG(0x010)
20 #define FSI_MENP32 TO_REG(0x014)
21 #define FSI_MSENP0 TO_REG(0x018)
22 #define FSI_MLEVP0 TO_REG(0x018)
23 #define FSI_MSENP32 TO_REG(0x01c)
24 #define FSI_MLEVP32 TO_REG(0x01c)
25 #define FSI_MCENP0 TO_REG(0x020)
26 #define FSI_MREFP0 TO_REG(0x020)
27 #define FSI_MCENP32 TO_REG(0x024)
28 #define FSI_MREFP32 TO_REG(0x024)
29
30 #define FSI_MVER TO_REG(0x074)
31 #define FSI_MRESP0 TO_REG(0x0d0)
32
33 #define FSI_MRESB0 TO_REG(0x1d0)
34 #define FSI_MRESB0_RESET_GENERAL BE_BIT(0)
35 #define FSI_MRESB0_RESET_ERROR BE_BIT(1)
36
fsi_master_read(void * opaque,hwaddr addr,unsigned size)37 static uint64_t fsi_master_read(void *opaque, hwaddr addr, unsigned size)
38 {
39 FSIMasterState *s = FSI_MASTER(opaque);
40
41 trace_fsi_master_read(addr, size);
42
43 if (addr + size > sizeof(s->regs)) {
44 qemu_log_mask(LOG_GUEST_ERROR,
45 "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n",
46 __func__, addr, size);
47 return 0;
48 }
49
50 return s->regs[TO_REG(addr)];
51 }
52
fsi_master_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)53 static void fsi_master_write(void *opaque, hwaddr addr, uint64_t data,
54 unsigned size)
55 {
56 FSIMasterState *s = FSI_MASTER(opaque);
57
58 trace_fsi_master_write(addr, size, data);
59
60 if (addr + size > sizeof(s->regs)) {
61 qemu_log_mask(LOG_GUEST_ERROR,
62 "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n",
63 __func__, addr, size);
64 return;
65 }
66
67 switch (TO_REG(addr)) {
68 case FSI_MENP0:
69 s->regs[FSI_MENP0] = data;
70 break;
71 case FSI_MENP32:
72 s->regs[FSI_MENP32] = data;
73 break;
74 case FSI_MSENP0:
75 s->regs[FSI_MENP0] |= data;
76 break;
77 case FSI_MSENP32:
78 s->regs[FSI_MENP32] |= data;
79 break;
80 case FSI_MCENP0:
81 s->regs[FSI_MENP0] &= ~data;
82 break;
83 case FSI_MCENP32:
84 s->regs[FSI_MENP32] &= ~data;
85 break;
86 case FSI_MRESP0:
87 /* Perform necessary resets leave register 0 to indicate no errors */
88 break;
89 case FSI_MRESB0:
90 if (data & FSI_MRESB0_RESET_GENERAL) {
91 device_cold_reset(DEVICE(opaque));
92 }
93 if (data & FSI_MRESB0_RESET_ERROR) {
94 /* FIXME: this seems dubious */
95 device_cold_reset(DEVICE(opaque));
96 }
97 break;
98 default:
99 s->regs[TO_REG(addr)] = data;
100 }
101 }
102
103 static const struct MemoryRegionOps fsi_master_ops = {
104 .read = fsi_master_read,
105 .write = fsi_master_write,
106 .endianness = DEVICE_BIG_ENDIAN,
107 };
108
fsi_master_init(Object * o)109 static void fsi_master_init(Object *o)
110 {
111 FSIMasterState *s = FSI_MASTER(o);
112
113 object_initialize_child(o, "cfam", &s->cfam, TYPE_FSI_CFAM);
114
115 qbus_init(&s->bus, sizeof(s->bus), TYPE_FSI_BUS, DEVICE(s), NULL);
116
117 memory_region_init_io(&s->iomem, OBJECT(s), &fsi_master_ops, s,
118 TYPE_FSI_MASTER, 0x10000000);
119 memory_region_init(&s->opb2fsi, OBJECT(s), "fsi.opb2fsi", 0x10000000);
120 }
121
fsi_master_realize(DeviceState * dev,Error ** errp)122 static void fsi_master_realize(DeviceState *dev, Error **errp)
123 {
124 FSIMasterState *s = FSI_MASTER(dev);
125
126 if (!qdev_realize(DEVICE(&s->cfam), BUS(&s->bus), errp)) {
127 return;
128 }
129
130 /* address ? */
131 memory_region_add_subregion(&s->opb2fsi, 0, &s->cfam.mr);
132 }
133
fsi_master_reset(DeviceState * dev)134 static void fsi_master_reset(DeviceState *dev)
135 {
136 FSIMasterState *s = FSI_MASTER(dev);
137
138 /* ASPEED default */
139 s->regs[FSI_MVER] = 0xe0050101;
140 }
141
fsi_master_class_init(ObjectClass * klass,void * data)142 static void fsi_master_class_init(ObjectClass *klass, void *data)
143 {
144 DeviceClass *dc = DEVICE_CLASS(klass);
145
146 dc->bus_type = TYPE_OP_BUS;
147 dc->desc = "FSI Master";
148 dc->realize = fsi_master_realize;
149 dc->reset = fsi_master_reset;
150 }
151
152 static const TypeInfo fsi_master_info = {
153 .name = TYPE_FSI_MASTER,
154 .parent = TYPE_DEVICE,
155 .instance_init = fsi_master_init,
156 .instance_size = sizeof(FSIMasterState),
157 .class_init = fsi_master_class_init,
158 };
159
fsi_register_types(void)160 static void fsi_register_types(void)
161 {
162 type_register_static(&fsi_master_info);
163 }
164
165 type_init(fsi_register_types);
166