xref: /openbmc/linux/sound/soc/amd/acp.h (revision 3eb8440d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ACP_HW_H
3 #define __ACP_HW_H
4 
5 #include "include/acp_2_2_d.h"
6 #include "include/acp_2_2_sh_mask.h"
7 
8 #define ACP_PAGE_SIZE_4K_ENABLE			0x02
9 
10 #define ACP_PLAYBACK_PTE_OFFSET			10
11 #define ACP_CAPTURE_PTE_OFFSET			0
12 
13 /* Playback and Capture Offset for Stoney */
14 #define ACP_ST_PLAYBACK_PTE_OFFSET	0x04
15 #define ACP_ST_CAPTURE_PTE_OFFSET	0x00
16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET	0x08
17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET	0x0c
18 
19 #define ACP_GARLIC_CNTL_DEFAULT			0x00000FB4
20 #define ACP_ONION_CNTL_DEFAULT			0x00000FB4
21 
22 #define ACP_PHYSICAL_BASE			0x14000
23 
24 /*
25  * In case of I2S SP controller instance, Stoney uses SRAM bank 1 for
26  * playback and SRAM Bank 2 for capture where as in case of BT I2S
27  * Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will
28  * be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks
29  * 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used
30  * for capture scenario.
31  */
32 #define ACP_SRAM_BANK_1_ADDRESS		0x4002000
33 #define ACP_SRAM_BANK_2_ADDRESS		0x4004000
34 #define ACP_SRAM_BANK_3_ADDRESS		0x4006000
35 #define ACP_SRAM_BANK_4_ADDRESS		0x4008000
36 #define ACP_SRAM_BANK_5_ADDRESS		0x400A000
37 
38 #define ACP_DMA_RESET_TIME			10000
39 #define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
40 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF
41 #define ACP_DMA_COMPLETE_TIME_OUT_VALUE		0x000000FF
42 
43 #define ACP_SRAM_BASE_ADDRESS			0x4000000
44 #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS		0x4001000
45 #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET	0x1000
46 #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS	0x00000000
47 #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS	0x01800000
48 
49 #define TO_ACP_I2S_1   0x2
50 #define TO_ACP_I2S_2   0x4
51 #define TO_BLUETOOTH   0x3
52 #define FROM_ACP_I2S_1 0xa
53 #define FROM_ACP_I2S_2 0xb
54 #define FROM_BLUETOOTH 0xb
55 
56 #define I2S_SP_INSTANCE                 0x01
57 #define I2S_BT_INSTANCE                 0x02
58 #define I2S_MICSP_INSTANCE		0x03
59 #define CAP_CHANNEL0			0x00
60 #define CAP_CHANNEL1			0x01
61 
62 #define ACP_TILE_ON_MASK                0x03
63 #define ACP_TILE_OFF_MASK               0x02
64 #define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
65 #define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
66 
67 #define ACP_TILE_P1_MASK                0x3e
68 #define ACP_TILE_P2_MASK                0x3d
69 #define ACP_TILE_DSP0_MASK              0x3b
70 #define ACP_TILE_DSP1_MASK              0x37
71 
72 #define ACP_TILE_DSP2_MASK              0x2f
73 /* Playback DMA channels */
74 #define SYSRAM_TO_ACP_CH_NUM 12
75 #define ACP_TO_I2S_DMA_CH_NUM 13
76 
77 /* Capture DMA channels */
78 #define I2S_TO_ACP_DMA_CH_NUM 14
79 #define ACP_TO_SYSRAM_CH_NUM 15
80 
81 /* Playback DMA Channels for I2S BT instance */
82 #define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM  8
83 #define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9
84 
85 /* Capture DMA Channels for I2S BT Instance */
86 #define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 10
87 #define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 11
88 
89 /* Playback DMA channels for I2S MICSP instance */
90 #define SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM  4
91 #define ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM 5
92 
93 #define NUM_DSCRS_PER_CHANNEL 2
94 
95 #define PLAYBACK_START_DMA_DESCR_CH12 0
96 #define PLAYBACK_END_DMA_DESCR_CH12 1
97 #define PLAYBACK_START_DMA_DESCR_CH13 2
98 #define PLAYBACK_END_DMA_DESCR_CH13 3
99 
100 #define CAPTURE_START_DMA_DESCR_CH14 4
101 #define CAPTURE_END_DMA_DESCR_CH14 5
102 #define CAPTURE_START_DMA_DESCR_CH15 6
103 #define CAPTURE_END_DMA_DESCR_CH15 7
104 
105 /* I2S BT Instance DMA Descriptors */
106 #define PLAYBACK_START_DMA_DESCR_CH8 8
107 #define PLAYBACK_END_DMA_DESCR_CH8 9
108 #define PLAYBACK_START_DMA_DESCR_CH9 10
109 #define PLAYBACK_END_DMA_DESCR_CH9 11
110 
111 #define CAPTURE_START_DMA_DESCR_CH10 12
112 #define CAPTURE_END_DMA_DESCR_CH10 13
113 #define CAPTURE_START_DMA_DESCR_CH11 14
114 #define CAPTURE_END_DMA_DESCR_CH11 15
115 
116 /* I2S MICSP Instance DMA Descriptors */
117 #define PLAYBACK_START_DMA_DESCR_CH4 0
118 #define PLAYBACK_END_DMA_DESCR_CH4 1
119 #define PLAYBACK_START_DMA_DESCR_CH5 2
120 #define PLAYBACK_END_DMA_DESCR_CH5 3
121 
122 #define mmACP_I2S_16BIT_RESOLUTION_EN       0x5209
123 #define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01
124 #define ACP_I2S_MICSP_16BIT_RESOLUTION_EN 0x01
125 #define ACP_I2S_SP_16BIT_RESOLUTION_EN	0x02
126 #define ACP_I2S_BT_16BIT_RESOLUTION_EN	0x04
127 #define ACP_BT_UART_PAD_SELECT_MASK	0x1
128 
129 enum acp_dma_priority_level {
130 	/* 0x0 Specifies the DMA channel is given normal priority */
131 	ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
132 	/* 0x1 Specifies the DMA channel is given high priority */
133 	ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
134 	ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
135 };
136 
137 struct audio_substream_data {
138 	dma_addr_t dma_addr;
139 	unsigned int order;
140 	u16 num_of_pages;
141 	u16 i2s_instance;
142 	u16 capture_channel;
143 	u16 direction;
144 	u16 ch1;
145 	u16 ch2;
146 	u16 destination;
147 	u16 dma_dscr_idx_1;
148 	u16 dma_dscr_idx_2;
149 	u32 pte_offset;
150 	u32 sram_bank;
151 	u32 byte_cnt_high_reg_offset;
152 	u32 byte_cnt_low_reg_offset;
153 	u32 dma_curr_dscr;
154 	uint64_t size;
155 	u64 bytescount;
156 	void __iomem *acp_mmio;
157 };
158 
159 struct audio_drv_data {
160 	struct snd_pcm_substream *play_i2ssp_stream;
161 	struct snd_pcm_substream *capture_i2ssp_stream;
162 	struct snd_pcm_substream *play_i2sbt_stream;
163 	struct snd_pcm_substream *capture_i2sbt_stream;
164 	struct snd_pcm_substream *play_i2s_micsp_stream;
165 	void __iomem *acp_mmio;
166 	u32 asic_type;
167 	snd_pcm_sframes_t delay;
168 };
169 
170 /*
171  * this structure used for platform data transfer between machine driver
172  * and dma driver
173  */
174 struct acp_platform_info {
175 	u16 play_i2s_instance;
176 	u16 cap_i2s_instance;
177 	u16 capture_channel;
178 };
179 
180 union acp_dma_count {
181 	struct {
182 	u32 low;
183 	u32 high;
184 	} bcount;
185 	u64 bytescount;
186 };
187 
188 enum {
189 	ACP_TILE_P1 = 0,
190 	ACP_TILE_P2,
191 	ACP_TILE_DSP0,
192 	ACP_TILE_DSP1,
193 	ACP_TILE_DSP2,
194 };
195 
196 enum {
197 	ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION = 0x0,
198 	ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
199 	ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM = 0x8,
200 	ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
201 	ACP_DMA_ATTR_FORCE_SIZE = 0xF
202 };
203 
204 typedef struct acp_dma_dscr_transfer {
205 	/* Specifies the source memory location for the DMA data transfer. */
206 	u32 src;
207 	/*
208 	 * Specifies the destination memory location to where the data will
209 	 * be transferred.
210 	 */
211 	u32 dest;
212 	/*
213 	 * Specifies the number of bytes need to be transferred
214 	 * from source to destination memory.Transfer direction & IOC enable
215 	 */
216 	u32 xfer_val;
217 	/* Reserved for future use */
218 	u32 reserved;
219 } acp_dma_dscr_transfer_t;
220 
221 extern bool acp_bt_uart_enable;
222 
223 #endif /*__ACP_HW_H */
224