xref: /openbmc/linux/drivers/misc/hpilo.h (revision 23d51b81)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * linux/drivers/char/hpilo.h
4  *
5  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
6  *	David Altobelli <david.altobelli@hp.com>
7  */
8 #ifndef __HPILO_H
9 #define __HPILO_H
10 
11 #define ILO_NAME "hpilo"
12 
13 /* iLO ASIC PCI revision id */
14 #define PCI_REV_ID_NECHES	7
15 
16 /* max number of open channel control blocks per device, hw limited to 32 */
17 #define MAX_CCB	       24
18 /* min number of open channel control blocks per device, hw limited to 32 */
19 #define MIN_CCB		8
20 /* max number of supported devices */
21 #define MAX_ILO_DEV	1
22 /* max number of files */
23 #define MAX_OPEN	(MAX_CCB * MAX_ILO_DEV)
24 /* total wait time in usec */
25 #define MAX_WAIT_TIME	10000
26 /* per spin wait time in usec */
27 #define WAIT_TIME	10
28 /* spin counter for open/close delay */
29 #define MAX_WAIT	(MAX_WAIT_TIME / WAIT_TIME)
30 
31 /*
32  * Per device, used to track global memory allocations.
33  */
34 struct ilo_hwinfo {
35 	/* mmio registers on device */
36 	char __iomem *mmio_vaddr;
37 
38 	/* doorbell registers on device */
39 	char __iomem *db_vaddr;
40 
41 	/* shared memory on device used for channel control blocks */
42 	char __iomem *ram_vaddr;
43 
44 	/* files corresponding to this device */
45 	struct ccb_data *ccb_alloc[MAX_CCB];
46 
47 	struct pci_dev *ilo_dev;
48 
49 	/*
50 	 * open_lock      serializes ccb_cnt during open and close
51 	 * [ irq disabled ]
52 	 * -> alloc_lock  used when adding/removing/searching ccb_alloc,
53 	 *                which represents all ccbs open on the device
54 	 * --> fifo_lock  controls access to fifo queues shared with hw
55 	 *
56 	 * Locks must be taken in this order, but open_lock and alloc_lock
57 	 * are optional, they do not need to be held in order to take a
58 	 * lower level lock.
59 	 */
60 	spinlock_t open_lock;
61 	spinlock_t alloc_lock;
62 	spinlock_t fifo_lock;
63 
64 	struct cdev cdev;
65 };
66 
67 /* offset from mmio_vaddr for enabling doorbell interrupts */
68 #define DB_IRQ		0xB2
69 /* offset from mmio_vaddr for outbound communications */
70 #define DB_OUT		0xD4
71 /* DB_OUT reset bit */
72 #define DB_RESET	26
73 
74 /*
75  * Channel control block. Used to manage hardware queues.
76  * The format must match hw's version.  The hw ccb is 128 bytes,
77  * but the context area shouldn't be touched by the driver.
78  */
79 #define ILOSW_CCB_SZ	64
80 #define ILOHW_CCB_SZ 	128
81 struct ccb {
82 	union {
83 		char *send_fifobar;
84 		u64 send_fifobar_pa;
85 	} ccb_u1;
86 	union {
87 		char *send_desc;
88 		u64 send_desc_pa;
89 	} ccb_u2;
90 	u64 send_ctrl;
91 
92 	union {
93 		char *recv_fifobar;
94 		u64 recv_fifobar_pa;
95 	} ccb_u3;
96 	union {
97 		char *recv_desc;
98 		u64 recv_desc_pa;
99 	} ccb_u4;
100 	u64 recv_ctrl;
101 
102 	union {
103 		char __iomem *db_base;
104 		u64 padding5;
105 	} ccb_u5;
106 
107 	u64 channel;
108 
109 	/* unused context area (64 bytes) */
110 };
111 
112 /* ccb queue parameters */
113 #define SENDQ		1
114 #define RECVQ 		2
115 #define NR_QENTRY    	4
116 #define L2_QENTRY_SZ 	12
117 
118 /* ccb ctrl bitfields */
119 #define CTRL_BITPOS_L2SZ             0
120 #define CTRL_BITPOS_FIFOINDEXMASK    4
121 #define CTRL_BITPOS_DESCLIMIT        18
122 #define CTRL_BITPOS_A                30
123 #define CTRL_BITPOS_G                31
124 
125 /* ccb doorbell macros */
126 #define L2_DB_SIZE		14
127 #define ONE_DB_SIZE		(1 << L2_DB_SIZE)
128 
129 /*
130  * Per fd structure used to track the ccb allocated to that dev file.
131  */
132 struct ccb_data {
133 	/* software version of ccb, using virtual addrs */
134 	struct ccb  driver_ccb;
135 
136 	/* hardware version of ccb, using physical addrs */
137 	struct ccb  ilo_ccb;
138 
139 	/* hardware ccb is written to this shared mapped device memory */
140 	struct ccb __iomem *mapped_ccb;
141 
142 	/* dma'able memory used for send/recv queues */
143 	void       *dma_va;
144 	dma_addr_t  dma_pa;
145 	size_t      dma_size;
146 
147 	/* pointer to hardware device info */
148 	struct ilo_hwinfo *ilo_hw;
149 
150 	/* queue for this ccb to wait for recv data */
151 	wait_queue_head_t ccb_waitq;
152 
153 	/* usage count, to allow for shared ccb's */
154 	int	    ccb_cnt;
155 
156 	/* open wanted exclusive access to this ccb */
157 	int	    ccb_excl;
158 };
159 
160 /*
161  * FIFO queue structure, shared with hw.
162  */
163 #define ILO_START_ALIGN	4096
164 #define ILO_CACHE_SZ 	 128
165 struct fifo {
166 	u64 nrents;	/* user requested number of fifo entries */
167 	u64 imask;  /* mask to extract valid fifo index */
168 	u64 merge;	/*  O/C bits to merge in during enqueue operation */
169 	u64 reset;	/* set to non-zero when the target device resets */
170 	u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
171 
172 	u64 head;
173 	u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
174 
175 	u64 tail;
176 	u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
177 
178 	u64 fifobar[];
179 };
180 
181 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
182 #define FIFOHANDLESIZE (sizeof(struct fifo))
183 #define FIFOBARTOHANDLE(_fifo) \
184 	((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
185 
186 /* the number of qwords to consume from the entry descriptor */
187 #define ENTRY_BITPOS_QWORDS      0
188 /* descriptor index number (within a specified queue) */
189 #define ENTRY_BITPOS_DESCRIPTOR  10
190 /* state bit, fifo entry consumed by consumer */
191 #define ENTRY_BITPOS_C           22
192 /* state bit, fifo entry is occupied */
193 #define ENTRY_BITPOS_O           23
194 
195 #define ENTRY_BITS_QWORDS        10
196 #define ENTRY_BITS_DESCRIPTOR    12
197 #define ENTRY_BITS_C             1
198 #define ENTRY_BITS_O             1
199 #define ENTRY_BITS_TOTAL	\
200 	(ENTRY_BITS_C + ENTRY_BITS_O + \
201 	 ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
202 
203 /* extract various entry fields */
204 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
205 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
206 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
207 #define ENTRY_MASK_QWORDS \
208 	(((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
209 #define ENTRY_MASK_DESCRIPTOR \
210 	(((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
211 
212 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
213 
214 #endif /* __HPILO_H */
215