1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-common.h" 28 #include "exec/cpu-defs.h" 29 #include "exec/cpu-interrupt.h" 30 #include "exec/gdbstub.h" 31 #include "exec/page-protection.h" 32 #include "qapi/qapi-types-common.h" 33 #include "target/arm/multiprocessing.h" 34 #include "target/arm/gtimer.h" 35 #include "target/arm/cpu-sysregs.h" 36 #include "target/arm/mmuidx.h" 37 38 #define EXCP_UDEF 1 /* undefined instruction */ 39 #define EXCP_SWI 2 /* software interrupt */ 40 #define EXCP_PREFETCH_ABORT 3 41 #define EXCP_DATA_ABORT 4 42 #define EXCP_IRQ 5 43 #define EXCP_FIQ 6 44 #define EXCP_BKPT 7 45 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 46 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 47 #define EXCP_HVC 11 /* HyperVisor Call */ 48 #define EXCP_HYP_TRAP 12 49 #define EXCP_SMC 13 /* Secure Monitor Call */ 50 #define EXCP_VIRQ 14 51 #define EXCP_VFIQ 15 52 #define EXCP_SEMIHOST 16 /* semihosting call */ 53 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 54 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 55 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 56 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 57 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 58 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 59 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 60 #define EXCP_VSERR 24 61 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 62 #define EXCP_NMI 26 63 #define EXCP_VINMI 27 64 #define EXCP_VFNMI 28 65 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ 66 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 67 68 #define ARMV7M_EXCP_RESET 1 69 #define ARMV7M_EXCP_NMI 2 70 #define ARMV7M_EXCP_HARD 3 71 #define ARMV7M_EXCP_MEM 4 72 #define ARMV7M_EXCP_BUS 5 73 #define ARMV7M_EXCP_USAGE 6 74 #define ARMV7M_EXCP_SECURE 7 75 #define ARMV7M_EXCP_SVC 11 76 #define ARMV7M_EXCP_DEBUG 12 77 #define ARMV7M_EXCP_PENDSV 14 78 #define ARMV7M_EXCP_SYSTICK 15 79 80 /* ARM-specific interrupt pending bits. */ 81 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 82 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 83 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 84 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 85 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4 86 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0 87 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1 88 89 /* The usual mapping for an AArch64 system register to its AArch32 90 * counterpart is for the 32 bit world to have access to the lower 91 * half only (with writes leaving the upper half untouched). It's 92 * therefore useful to be able to pass TCG the offset of the least 93 * significant half of a uint64_t struct member. 94 */ 95 #if HOST_BIG_ENDIAN 96 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 97 #define offsetofhigh32(S, M) offsetof(S, M) 98 #else 99 #define offsetoflow32(S, M) offsetof(S, M) 100 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 101 #endif 102 103 /* The 2nd extra word holding syndrome info for data aborts does not use 104 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 105 * help the sleb128 encoder do a better job. 106 * When restoring the CPU state, we shift it back up. 107 */ 108 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 109 #define ARM_INSN_START_WORD2_SHIFT 13 110 111 /* We currently assume float and double are IEEE single and double 112 precision respectively. 113 Doing runtime conversions is tricky because VFP registers may contain 114 integer values (eg. as the result of a FTOSI instruction). 115 s<2n> maps to the least significant half of d<n> 116 s<2n+1> maps to the most significant half of d<n> 117 */ 118 119 /** 120 * DynamicGDBFeatureInfo: 121 * @desc: Contains the feature descriptions. 122 * @data: A union with data specific to the set of registers 123 * @cpregs_keys: Array that contains the corresponding Key of 124 * a given cpreg with the same order of the cpreg 125 * in the XML description. 126 */ 127 typedef struct DynamicGDBFeatureInfo { 128 GDBFeature desc; 129 union { 130 struct { 131 uint32_t *keys; 132 } cpregs; 133 } data; 134 } DynamicGDBFeatureInfo; 135 136 /* CPU state for each instance of a generic timer (in cp15 c14) */ 137 typedef struct ARMGenericTimer { 138 uint64_t cval; /* Timer CompareValue register */ 139 uint64_t ctl; /* Timer Control register */ 140 } ARMGenericTimer; 141 142 /* Define a maximum sized vector register. 143 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 144 * For 64-bit, this is a 2048-bit SVE register. 145 * 146 * Note that the mapping between S, D, and Q views of the register bank 147 * differs between AArch64 and AArch32. 148 * In AArch32: 149 * Qn = regs[n].d[1]:regs[n].d[0] 150 * Dn = regs[n / 2].d[n & 1] 151 * Sn = regs[n / 4].d[n % 4 / 2], 152 * bits 31..0 for even n, and bits 63..32 for odd n 153 * (and regs[16] to regs[31] are inaccessible) 154 * In AArch64: 155 * Zn = regs[n].d[*] 156 * Qn = regs[n].d[1]:regs[n].d[0] 157 * Dn = regs[n].d[0] 158 * Sn = regs[n].d[0] bits 31..0 159 * Hn = regs[n].d[0] bits 15..0 160 * 161 * This corresponds to the architecturally defined mapping between 162 * the two execution states, and means we do not need to explicitly 163 * map these registers when changing states. 164 * 165 * Align the data for use with TCG host vector operations. 166 */ 167 168 #define ARM_MAX_VQ 16 169 170 typedef struct ARMVectorReg { 171 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 172 } ARMVectorReg; 173 174 /* In AArch32 mode, predicate registers do not exist at all. */ 175 typedef struct ARMPredicateReg { 176 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 177 } ARMPredicateReg; 178 179 /* In AArch32 mode, PAC keys do not exist at all. */ 180 typedef struct ARMPACKey { 181 uint64_t lo, hi; 182 } ARMPACKey; 183 184 /* See the commentary above the TBFLAG field definitions. */ 185 typedef struct CPUARMTBFlags { 186 uint32_t flags; 187 uint64_t flags2; 188 } CPUARMTBFlags; 189 190 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 191 192 typedef struct NVICState NVICState; 193 194 /* 195 * Enum for indexing vfp.fp_status[]. 196 * 197 * FPST_A32: is the "normal" fp status for AArch32 insns 198 * FPST_A64: is the "normal" fp status for AArch64 insns 199 * FPST_A32_F16: used for AArch32 half-precision calculations 200 * FPST_A64_F16: used for AArch64 half-precision calculations 201 * FPST_STD: the ARM "Standard FPSCR Value" 202 * FPST_STD_F16: used for half-precision 203 * calculations with the ARM "Standard FPSCR Value" 204 * FPST_AH: used for the A64 insns which change behaviour 205 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 206 * and the reciprocal and square root estimate/step insns) 207 * FPST_AH_F16: used for the A64 insns which change behaviour 208 * when FPCR.AH == 1 (bfloat16 conversions and multiplies, 209 * and the reciprocal and square root estimate/step insns); 210 * for half-precision 211 * ZA: the "streaming sve" fp status. 212 * ZA_F16: likewise for half-precision. 213 * 214 * Half-precision operations are governed by a separate 215 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 216 * status structure to control this. 217 * 218 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 219 * round-to-nearest and is used by any operations (generally 220 * Neon) which the architecture defines as controlled by the 221 * standard FPSCR value rather than the FPSCR. 222 * 223 * The "standard FPSCR but for fp16 ops" is needed because 224 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 225 * using a fixed value for it. 226 * 227 * FPST_AH is needed because some insns have different 228 * behaviour when FPCR.AH == 1: they don't update cumulative 229 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and 230 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, 231 * which means we need an FPST_AH_F16 as well. 232 * 233 * The "ZA" float_status are for Streaming SVE operations which use 234 * default-NaN and do not generate fp exceptions, which means that they 235 * do not accumulate exception bits back into FPCR. 236 * See e.g. FPAdd vs FPAdd_ZA pseudocode functions, and the setting 237 * of fpcr.DN and fpexec parameters. 238 * 239 * To avoid having to transfer exception bits around, we simply 240 * say that the FPSCR cumulative exception flags are the logical 241 * OR of the flags in the four fp statuses. This relies on the 242 * only thing which needs to read the exception flags being 243 * an explicit FPSCR read. 244 */ 245 typedef enum ARMFPStatusFlavour { 246 FPST_A32, 247 FPST_A64, 248 FPST_A32_F16, 249 FPST_A64_F16, 250 FPST_AH, 251 FPST_AH_F16, 252 FPST_ZA, 253 FPST_ZA_F16, 254 FPST_STD, 255 FPST_STD_F16, 256 } ARMFPStatusFlavour; 257 #define FPST_COUNT 10 258 259 typedef struct CPUArchState { 260 /* Regs for current mode. */ 261 uint32_t regs[16]; 262 263 /* 32/64 switch only happens when taking and returning from 264 * exceptions so the overlap semantics are taken care of then 265 * instead of having a complicated union. 266 */ 267 /* Regs for A64 mode. */ 268 uint64_t xregs[32]; 269 uint64_t pc; 270 /* PSTATE isn't an architectural register for ARMv8. However, it is 271 * convenient for us to assemble the underlying state into a 64 bit format 272 * identical to the architectural format used for the SPSR. (This is also 273 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 274 * 'pstate' register are.) Of the PSTATE bits: 275 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 276 * semantics as for AArch32, as described in the comments on each field) 277 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 278 * DAIF (exception masks) are kept in env->daif 279 * BTYPE is kept in env->btype 280 * SM and ZA are kept in env->svcr 281 * all other bits are stored in their correct places in env->pstate 282 */ 283 uint64_t pstate; 284 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 285 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 286 287 /* Cached TBFLAGS state. See below for which bits are included. */ 288 CPUARMTBFlags hflags; 289 290 /* Frequently accessed CPSR bits are stored separately for efficiency. 291 This contains all the other bits. Use cpsr_{read,write} to access 292 the whole CPSR. */ 293 uint32_t uncached_cpsr; 294 uint32_t spsr; 295 296 /* Banked registers. */ 297 uint64_t banked_spsr[8]; 298 uint32_t banked_r13[8]; 299 uint32_t banked_r14[8]; 300 301 /* These hold r8-r12. */ 302 uint32_t usr_regs[5]; 303 uint32_t fiq_regs[5]; 304 305 /* cpsr flag cache for faster execution */ 306 uint32_t CF; /* 0 or 1 */ 307 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 308 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 309 uint32_t ZF; /* Z set if zero. */ 310 uint32_t QF; /* 0 or 1 */ 311 uint32_t GE; /* cpsr[19:16] */ 312 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 313 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 314 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 315 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 316 317 uint64_t elr_el[4]; /* AArch64 exception link regs */ 318 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 319 320 /* System control coprocessor (cp15) */ 321 struct { 322 uint32_t c0_cpuid; 323 union { /* Cache size selection */ 324 struct { 325 uint64_t _unused_csselr0; 326 uint64_t csselr_ns; 327 uint64_t _unused_csselr1; 328 uint64_t csselr_s; 329 }; 330 uint64_t csselr_el[4]; 331 }; 332 union { /* System control register. */ 333 struct { 334 uint64_t _unused_sctlr; 335 uint64_t sctlr_ns; 336 uint64_t hsctlr; 337 uint64_t sctlr_s; 338 }; 339 uint64_t sctlr_el[4]; 340 }; 341 uint64_t sctlr2_el[4]; /* Extension to System control register. */ 342 uint64_t vsctlr; /* Virtualization System control register. */ 343 uint64_t cpacr_el1; /* Architectural feature access control register */ 344 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 345 uint64_t sder; /* Secure debug enable register. */ 346 uint32_t nsacr; /* Non-secure access control register. */ 347 union { /* MMU translation table base 0. */ 348 struct { 349 uint64_t _unused_ttbr0_0; 350 uint64_t ttbr0_ns; 351 uint64_t _unused_ttbr0_1; 352 uint64_t ttbr0_s; 353 }; 354 uint64_t ttbr0_el[4]; 355 }; 356 union { /* MMU translation table base 1. */ 357 struct { 358 uint64_t _unused_ttbr1_0; 359 uint64_t ttbr1_ns; 360 uint64_t _unused_ttbr1_1; 361 uint64_t ttbr1_s; 362 }; 363 uint64_t ttbr1_el[4]; 364 }; 365 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 366 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 367 /* MMU translation table base control. */ 368 uint64_t tcr_el[4]; 369 uint64_t tcr2_el[3]; 370 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 371 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 372 uint64_t pir_el[4]; /* PIRE0_EL1, PIR_EL1, PIR_EL2, PIR_EL3 */ 373 uint64_t pire0_el2; 374 uint64_t s2pir_el2; 375 uint32_t c2_data; /* MPU data cacheable bits. */ 376 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 377 union { /* MMU domain access control register 378 * MPU write buffer control. 379 */ 380 struct { 381 uint64_t dacr_ns; 382 uint64_t dacr_s; 383 }; 384 struct { 385 uint64_t dacr32_el2; 386 }; 387 }; 388 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 389 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 390 uint64_t hcr_el2; /* Hypervisor configuration register */ 391 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 392 uint64_t scr_el3; /* Secure configuration register. */ 393 union { /* Fault status registers. */ 394 struct { 395 uint64_t ifsr_ns; 396 uint64_t ifsr_s; 397 }; 398 struct { 399 uint64_t ifsr32_el2; 400 }; 401 }; 402 union { 403 struct { 404 uint64_t _unused_dfsr; 405 uint64_t dfsr_ns; 406 uint64_t hsr; 407 uint64_t dfsr_s; 408 }; 409 uint64_t esr_el[4]; 410 }; 411 uint32_t c6_region[8]; /* MPU base/size registers. */ 412 union { /* Fault address registers. */ 413 struct { 414 uint64_t _unused_far0; 415 #if HOST_BIG_ENDIAN 416 uint32_t ifar_ns; 417 uint32_t dfar_ns; 418 uint32_t ifar_s; 419 uint32_t dfar_s; 420 #else 421 uint32_t dfar_ns; 422 uint32_t ifar_ns; 423 uint32_t dfar_s; 424 uint32_t ifar_s; 425 #endif 426 uint64_t _unused_far3; 427 }; 428 uint64_t far_el[4]; 429 }; 430 uint64_t hpfar_el2; 431 uint64_t hstr_el2; 432 union { /* Translation result. */ 433 struct { 434 uint64_t _unused_par_0; 435 uint64_t par_ns; 436 uint64_t _unused_par_1; 437 uint64_t par_s; 438 }; 439 uint64_t par_el[4]; 440 }; 441 442 uint32_t c9_insn; /* Cache lockdown registers. */ 443 uint32_t c9_data; 444 uint64_t c9_pmcr; /* performance monitor control register */ 445 uint64_t c9_pmcnten; /* perf monitor counter enables */ 446 uint64_t c9_pmovsr; /* perf monitor overflow status */ 447 uint64_t c9_pmuserenr; /* perf monitor user enable */ 448 uint64_t c9_pmselr; /* perf monitor counter selection register */ 449 uint64_t c9_pminten; /* perf monitor interrupt enables */ 450 /* Memory attribute redirection */ 451 union { 452 struct { 453 #if HOST_BIG_ENDIAN 454 uint64_t _unused_mair_0; 455 uint32_t mair1_ns; 456 uint32_t mair0_ns; 457 uint64_t _unused_mair_1; 458 uint32_t mair1_s; 459 uint32_t mair0_s; 460 #else 461 uint64_t _unused_mair_0; 462 uint32_t mair0_ns; 463 uint32_t mair1_ns; 464 uint64_t _unused_mair_1; 465 uint32_t mair0_s; 466 uint32_t mair1_s; 467 #endif 468 }; 469 uint64_t mair_el[4]; 470 }; 471 uint64_t mair2_el[4]; 472 union { /* vector base address register */ 473 struct { 474 uint64_t _unused_vbar; 475 uint64_t vbar_ns; 476 uint64_t hvbar; 477 uint64_t vbar_s; 478 }; 479 uint64_t vbar_el[4]; 480 }; 481 uint32_t mvbar; /* (monitor) vector base address register */ 482 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 483 struct { /* FCSE PID. */ 484 uint32_t fcseidr_ns; 485 uint32_t fcseidr_s; 486 }; 487 union { /* Context ID. */ 488 struct { 489 uint64_t _unused_contextidr_0; 490 uint64_t contextidr_ns; 491 uint64_t _unused_contextidr_1; 492 uint64_t contextidr_s; 493 }; 494 uint64_t contextidr_el[4]; 495 }; 496 union { /* User RW Thread register. */ 497 struct { 498 uint64_t tpidrurw_ns; 499 uint64_t tpidrprw_ns; 500 uint64_t htpidr; 501 uint64_t _tpidr_el3; 502 }; 503 uint64_t tpidr_el[4]; 504 }; 505 uint64_t tpidr2_el0; 506 /* The secure banks of these registers don't map anywhere */ 507 uint64_t tpidrurw_s; 508 uint64_t tpidrprw_s; 509 uint64_t tpidruro_s; 510 511 union { /* User RO Thread register. */ 512 uint64_t tpidruro_ns; 513 uint64_t tpidrro_el[1]; 514 }; 515 uint64_t c14_cntfrq; /* Counter Frequency register */ 516 uint64_t c14_cntkctl; /* Timer Control register */ 517 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 518 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 519 uint64_t cntpoff_el2; /* Counter Physical Offset register */ 520 ARMGenericTimer c14_timer[NUM_GTIMERS]; 521 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 522 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 523 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 524 uint32_t c15_threadid; /* TI debugger thread-ID. */ 525 uint32_t c15_config_base_address; /* SCU base address. */ 526 uint32_t c15_diagnostic; /* diagnostic register */ 527 uint32_t c15_power_diagnostic; 528 uint32_t c15_power_control; /* power control */ 529 uint64_t dbgbvr[16]; /* breakpoint value registers */ 530 uint64_t dbgbcr[16]; /* breakpoint control registers */ 531 uint64_t dbgwvr[16]; /* watchpoint value registers */ 532 uint64_t dbgwcr[16]; /* watchpoint control registers */ 533 uint64_t dbgclaim; /* DBGCLAIM bits */ 534 uint64_t mdscr_el1; 535 uint64_t oslsr_el1; /* OS Lock Status */ 536 uint64_t osdlr_el1; /* OS DoubleLock status */ 537 uint64_t mdcr_el2; 538 uint64_t mdcr_el3; 539 /* Stores the architectural value of the counter *the last time it was 540 * updated* by pmccntr_op_start. Accesses should always be surrounded 541 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 542 * architecturally-correct value is being read/set. 543 */ 544 uint64_t c15_ccnt; 545 /* Stores the delta between the architectural value and the underlying 546 * cycle count during normal operation. It is used to update c15_ccnt 547 * to be the correct architectural value before accesses. During 548 * accesses, c15_ccnt_delta contains the underlying count being used 549 * for the access, after which it reverts to the delta value in 550 * pmccntr_op_finish. 551 */ 552 uint64_t c15_ccnt_delta; 553 uint64_t c14_pmevcntr[31]; 554 uint64_t c14_pmevcntr_delta[31]; 555 uint64_t c14_pmevtyper[31]; 556 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 557 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 558 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 559 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 560 uint64_t gcr_el1; 561 uint64_t rgsr_el1; 562 563 /* Minimal RAS registers */ 564 uint64_t disr_el1; 565 uint64_t vdisr_el2; 566 uint64_t vsesr_el2; 567 568 /* 569 * Fine-Grained Trap registers. We store these as arrays so the 570 * access checking code doesn't have to manually select 571 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 572 * FEAT_FGT2 will add more elements to these arrays. 573 */ 574 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 575 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 576 uint64_t fgt_exec[1]; /* HFGITR */ 577 578 /* RME registers */ 579 uint64_t gpccr_el3; 580 uint64_t gptbr_el3; 581 uint64_t mfar_el3; 582 583 /* NV2 register */ 584 uint64_t vncr_el2; 585 586 uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */ 587 uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */ 588 589 /* MEC registers */ 590 uint64_t mecid_p0_el2; 591 uint64_t mecid_a0_el2; 592 uint64_t mecid_p1_el2; 593 uint64_t mecid_a1_el2; 594 uint64_t mecid_rl_a_el3; 595 uint64_t vmecid_p_el2; 596 uint64_t vmecid_a_el2; 597 } cp15; 598 599 struct { 600 /* M profile has up to 4 stack pointers: 601 * a Main Stack Pointer and a Process Stack Pointer for each 602 * of the Secure and Non-Secure states. (If the CPU doesn't support 603 * the security extension then it has only two SPs.) 604 * In QEMU we always store the currently active SP in regs[13], 605 * and the non-active SP for the current security state in 606 * v7m.other_sp. The stack pointers for the inactive security state 607 * are stored in other_ss_msp and other_ss_psp. 608 * switch_v7m_security_state() is responsible for rearranging them 609 * when we change security state. 610 */ 611 uint32_t other_sp; 612 uint32_t other_ss_msp; 613 uint32_t other_ss_psp; 614 uint32_t vecbase[M_REG_NUM_BANKS]; 615 uint32_t basepri[M_REG_NUM_BANKS]; 616 uint32_t control[M_REG_NUM_BANKS]; 617 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 618 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 619 uint32_t hfsr; /* HardFault Status */ 620 uint32_t dfsr; /* Debug Fault Status Register */ 621 uint32_t sfsr; /* Secure Fault Status Register */ 622 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 623 uint32_t bfar; /* BusFault Address */ 624 uint32_t sfar; /* Secure Fault Address Register */ 625 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 626 int exception; 627 uint32_t primask[M_REG_NUM_BANKS]; 628 uint32_t faultmask[M_REG_NUM_BANKS]; 629 uint32_t aircr; /* only holds r/w state if security extn implemented */ 630 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 631 uint32_t csselr[M_REG_NUM_BANKS]; 632 uint32_t scr[M_REG_NUM_BANKS]; 633 uint32_t msplim[M_REG_NUM_BANKS]; 634 uint32_t psplim[M_REG_NUM_BANKS]; 635 uint32_t fpcar[M_REG_NUM_BANKS]; 636 uint32_t fpccr[M_REG_NUM_BANKS]; 637 uint32_t fpdscr[M_REG_NUM_BANKS]; 638 uint32_t cpacr[M_REG_NUM_BANKS]; 639 uint32_t nsacr; 640 uint32_t ltpsize; 641 uint32_t vpr; 642 } v7m; 643 644 /* Information associated with an exception about to be taken: 645 * code which raises an exception must set cs->exception_index and 646 * the relevant parts of this structure; the cpu_do_interrupt function 647 * will then set the guest-visible registers as part of the exception 648 * entry process. 649 */ 650 struct { 651 uint64_t syndrome; /* AArch64 format syndrome register */ 652 uint64_t vaddress; /* virtual addr associated with exception, if any */ 653 uint32_t fsr; /* AArch32 format fault status register info */ 654 uint32_t target_el; /* EL the exception should be targeted for */ 655 } exception; 656 657 /* Information associated with an SError */ 658 struct { 659 uint8_t pending; 660 uint8_t has_esr; 661 uint64_t esr; 662 } serror; 663 664 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 665 666 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 667 uint32_t irq_line_state; 668 669 /* Thumb-2 EE state. */ 670 uint32_t teecr; 671 uint32_t teehbr; 672 673 /* VFP coprocessor state. */ 674 struct { 675 ARMVectorReg zregs[32]; 676 677 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 678 #define FFR_PRED_NUM 16 679 ARMPredicateReg pregs[17]; 680 /* Scratch space for aa64 sve predicate temporary. */ 681 ARMPredicateReg preg_tmp; 682 683 /* We store these fpcsr fields separately for convenience. */ 684 uint32_t qc[4] QEMU_ALIGNED(16); 685 int vec_len; 686 int vec_stride; 687 688 /* 689 * Floating point status and control registers. Some bits are 690 * stored separately in other fields or in the float_status below. 691 */ 692 uint64_t fpsr; 693 uint64_t fpcr; 694 695 uint32_t xregs[16]; 696 697 /* There are a number of distinct float control structures. */ 698 float_status fp_status[FPST_COUNT]; 699 700 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 701 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 702 } vfp; 703 704 uint64_t exclusive_addr; 705 uint64_t exclusive_val; 706 /* 707 * Contains the 'val' for the second 64-bit register of LDXP, which comes 708 * from the higher address, not the high part of a complete 128-bit value. 709 * In some ways it might be more convenient to record the exclusive value 710 * as the low and high halves of a 128 bit data value, but the current 711 * semantics of these fields are baked into the migration format. 712 */ 713 uint64_t exclusive_high; 714 715 struct { 716 ARMPACKey apia; 717 ARMPACKey apib; 718 ARMPACKey apda; 719 ARMPACKey apdb; 720 ARMPACKey apga; 721 } keys; 722 723 uint64_t scxtnum_el[4]; 724 725 struct { 726 /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */ 727 uint64_t zt0[512 / 64] QEMU_ALIGNED(16); 728 729 /* 730 * SME ZA storage -- 256 x 256 byte array, with bytes in host 731 * word order, as we do with vfp.zregs[]. This corresponds to 732 * the architectural ZA array, where ZA[N] is in the least 733 * significant bytes of env->za_state.za[N]. 734 * 735 * When SVL is less than the architectural maximum, the accessible 736 * storage is restricted, such that if the SVL is X bytes the guest 737 * can see only the bottom X elements of zarray[], and only the least 738 * significant X bytes of each element of the array. (In other words, 739 * the observable part is always square.) 740 * 741 * The ZA storage can also be considered as a set of square tiles of 742 * elements of different sizes. The mapping from tiles to the ZA array 743 * is architecturally defined, such that for tiles of elements of esz 744 * bytes, the Nth row (or "horizontal slice") of tile T is in 745 * ZA[T + N * esz]. Note that this means that each tile is not 746 * contiguous in the ZA storage, because its rows are striped through 747 * the ZA array. 748 * 749 * Because this is so large, keep this toward the end of the 750 * reset area, to keep the offsets into the rest of the structure 751 * smaller. 752 */ 753 ARMVectorReg za[ARM_MAX_VQ * 16]; 754 } za_state; 755 756 struct CPUBreakpoint *cpu_breakpoint[16]; 757 struct CPUWatchpoint *cpu_watchpoint[16]; 758 759 /* Optional fault info across tlb lookup. */ 760 ARMMMUFaultInfo *tlb_fi; 761 762 /* Fields up to this point are cleared by a CPU reset */ 763 struct {} end_reset_fields; 764 765 /* Fields after this point are preserved across CPU reset. */ 766 767 /* Internal CPU feature flags. */ 768 uint64_t features; 769 770 /* PMSAv7 MPU */ 771 struct { 772 uint32_t *drbar; 773 uint32_t *drsr; 774 uint32_t *dracr; 775 uint32_t rnr[M_REG_NUM_BANKS]; 776 } pmsav7; 777 778 /* PMSAv8 MPU */ 779 struct { 780 /* The PMSAv8 implementation also shares some PMSAv7 config 781 * and state: 782 * pmsav7.rnr (region number register) 783 * pmsav7_dregion (number of configured regions) 784 */ 785 uint32_t *rbar[M_REG_NUM_BANKS]; 786 uint32_t *rlar[M_REG_NUM_BANKS]; 787 uint32_t *hprbar; 788 uint32_t *hprlar; 789 uint32_t mair0[M_REG_NUM_BANKS]; 790 uint32_t mair1[M_REG_NUM_BANKS]; 791 uint32_t hprselr; 792 } pmsav8; 793 794 /* v8M SAU */ 795 struct { 796 uint32_t *rbar; 797 uint32_t *rlar; 798 uint32_t rnr; 799 uint32_t ctrl; 800 } sau; 801 802 #if !defined(CONFIG_USER_ONLY) 803 NVICState *nvic; 804 const struct arm_boot_info *boot_info; 805 /* Store GICv3CPUState to access from this struct */ 806 void *gicv3state; 807 #else /* CONFIG_USER_ONLY */ 808 /* For usermode syscall translation. */ 809 bool eabi; 810 /* Linux syscall tagged address support */ 811 bool tagged_addr_enable; 812 #endif /* CONFIG_USER_ONLY */ 813 } CPUARMState; 814 815 static inline void set_feature(CPUARMState *env, int feature) 816 { 817 env->features |= 1ULL << feature; 818 } 819 820 static inline void unset_feature(CPUARMState *env, int feature) 821 { 822 env->features &= ~(1ULL << feature); 823 } 824 825 /** 826 * ARMELChangeHookFn: 827 * type of a function which can be registered via arm_register_el_change_hook() 828 * to get callbacks when the CPU changes its exception level or mode. 829 */ 830 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 831 typedef struct ARMELChangeHook ARMELChangeHook; 832 struct ARMELChangeHook { 833 ARMELChangeHookFn *hook; 834 void *opaque; 835 QLIST_ENTRY(ARMELChangeHook) node; 836 }; 837 838 /* These values map onto the return values for 839 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 840 typedef enum ARMPSCIState { 841 PSCI_ON = 0, 842 PSCI_OFF = 1, 843 PSCI_ON_PENDING = 2 844 } ARMPSCIState; 845 846 typedef struct ARMISARegisters ARMISARegisters; 847 848 /* 849 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 850 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 851 * 852 * While processing properties during initialization, corresponding init bits 853 * are set for bits in sve_vq_map that have been set by properties. 854 * 855 * Bits set in supported represent valid vector lengths for the CPU type. 856 */ 857 typedef struct { 858 uint32_t map, init, supported; 859 } ARMVQMap; 860 861 /* REG is ID_XXX */ 862 #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ 863 ({ \ 864 ARMISARegisters *i_ = (ISAR); \ 865 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 866 regval = FIELD_DP64(regval, REG, FIELD, VALUE); \ 867 i_->idregs[REG ## _EL1_IDX] = regval; \ 868 }) 869 870 #define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \ 871 ({ \ 872 ARMISARegisters *i_ = (ISAR); \ 873 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \ 874 regval = FIELD_DP32(regval, REG, FIELD, VALUE); \ 875 i_->idregs[REG ## _EL1_IDX] = regval; \ 876 }) 877 878 #define FIELD_EX64_IDREG(ISAR, REG, FIELD) \ 879 ({ \ 880 const ARMISARegisters *i_ = (ISAR); \ 881 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 882 }) 883 884 #define FIELD_EX32_IDREG(ISAR, REG, FIELD) \ 885 ({ \ 886 const ARMISARegisters *i_ = (ISAR); \ 887 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 888 }) 889 890 #define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \ 891 ({ \ 892 const ARMISARegisters *i_ = (ISAR); \ 893 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ 894 }) 895 896 #define SET_IDREG(ISAR, REG, VALUE) \ 897 ({ \ 898 ARMISARegisters *i_ = (ISAR); \ 899 i_->idregs[REG ## _EL1_IDX] = VALUE; \ 900 }) 901 902 #define GET_IDREG(ISAR, REG) \ 903 ({ \ 904 const ARMISARegisters *i_ = (ISAR); \ 905 i_->idregs[REG ## _EL1_IDX]; \ 906 }) 907 908 /** 909 * ARMCPU: 910 * @env: #CPUARMState 911 * 912 * An ARM CPU core. 913 */ 914 struct ArchCPU { 915 CPUState parent_obj; 916 917 CPUARMState env; 918 919 /* Coprocessor information */ 920 GHashTable *cp_regs; 921 /* For marshalling (mostly coprocessor) register state between the 922 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 923 * we use these arrays. 924 */ 925 /* List of register indexes managed via these arrays; (full KVM style 926 * 64 bit indexes, not CPRegInfo 32 bit indexes) 927 */ 928 uint64_t *cpreg_indexes; 929 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 930 uint64_t *cpreg_values; 931 /* Length of the indexes, values, reset_values arrays */ 932 int32_t cpreg_array_len; 933 /* These are used only for migration: incoming data arrives in 934 * these fields and is sanity checked in post_load before copying 935 * to the working data structures above. 936 */ 937 uint64_t *cpreg_vmstate_indexes; 938 uint64_t *cpreg_vmstate_values; 939 int32_t cpreg_vmstate_array_len; 940 941 DynamicGDBFeatureInfo dyn_sysreg_feature; 942 DynamicGDBFeatureInfo dyn_svereg_feature; 943 DynamicGDBFeatureInfo dyn_smereg_feature; 944 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 945 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 946 DynamicGDBFeatureInfo dyn_tls_feature; 947 948 /* Timers used by the generic (architected) timer */ 949 QEMUTimer *gt_timer[NUM_GTIMERS]; 950 /* 951 * Timer used by the PMU. Its state is restored after migration by 952 * pmu_op_finish() - it does not need other handling during migration 953 */ 954 QEMUTimer *pmu_timer; 955 /* Timer used for WFxT timeouts */ 956 QEMUTimer *wfxt_timer; 957 958 /* GPIO outputs for generic timer */ 959 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 960 /* GPIO output for GICv3 maintenance interrupt signal */ 961 qemu_irq gicv3_maintenance_interrupt; 962 /* GPIO output for the PMU interrupt */ 963 qemu_irq pmu_interrupt; 964 965 /* MemoryRegion to use for secure physical accesses */ 966 MemoryRegion *secure_memory; 967 968 /* MemoryRegion to use for allocation tag accesses */ 969 MemoryRegion *tag_memory; 970 MemoryRegion *secure_tag_memory; 971 972 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 973 Object *idau; 974 975 /* 'compatible' string for this CPU for Linux device trees */ 976 const char *dtb_compatible; 977 978 /* PSCI version for this CPU 979 * Bits[31:16] = Major Version 980 * Bits[15:0] = Minor Version 981 */ 982 uint32_t psci_version; 983 984 /* Current power state, access guarded by BQL */ 985 ARMPSCIState power_state; 986 987 /* CPU has virtualization extension */ 988 bool has_el2; 989 /* CPU has security extension */ 990 bool has_el3; 991 /* CPU has PMU (Performance Monitor Unit) */ 992 bool has_pmu; 993 /* CPU has VFP */ 994 bool has_vfp; 995 /* CPU has 32 VFP registers */ 996 bool has_vfp_d32; 997 /* CPU has Neon */ 998 bool has_neon; 999 /* CPU has M-profile DSP extension */ 1000 bool has_dsp; 1001 1002 /* CPU has memory protection unit */ 1003 bool has_mpu; 1004 /* CPU has MTE enabled in KVM mode */ 1005 bool kvm_mte; 1006 /* PMSAv7 MPU number of supported regions */ 1007 uint32_t pmsav7_dregion; 1008 /* PMSAv8 MPU number of supported hyp regions */ 1009 uint32_t pmsav8r_hdregion; 1010 /* v8M SAU number of supported regions */ 1011 uint32_t sau_sregion; 1012 1013 /* PSCI conduit used to invoke PSCI methods 1014 * 0 - disabled, 1 - smc, 2 - hvc 1015 */ 1016 uint32_t psci_conduit; 1017 1018 /* For v8M, initial value of the Secure VTOR */ 1019 uint32_t init_svtor; 1020 /* For v8M, initial value of the Non-secure VTOR */ 1021 uint32_t init_nsvtor; 1022 1023 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 1024 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 1025 */ 1026 uint32_t kvm_target; 1027 1028 /* KVM init features for this CPU */ 1029 uint32_t kvm_init_features[7]; 1030 1031 /* KVM CPU state */ 1032 1033 /* KVM virtual time adjustment */ 1034 bool kvm_adjvtime; 1035 bool kvm_vtime_dirty; 1036 uint64_t kvm_vtime; 1037 1038 /* KVM steal time */ 1039 OnOffAuto kvm_steal_time; 1040 1041 /* Uniprocessor system with MP extensions */ 1042 bool mp_is_up; 1043 1044 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 1045 * and the probe failed (so we need to report the error in realize) 1046 */ 1047 bool host_cpu_probe_failed; 1048 1049 /* QOM property to indicate we should use the back-compat CNTFRQ default */ 1050 bool backcompat_cntfrq; 1051 1052 /* QOM property to indicate we should use the back-compat QARMA5 default */ 1053 bool backcompat_pauth_default_use_qarma5; 1054 1055 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 1056 * register. 1057 */ 1058 int32_t core_count; 1059 1060 /* The instance init functions for implementation-specific subclasses 1061 * set these fields to specify the implementation-dependent values of 1062 * various constant registers and reset values of non-constant 1063 * registers. 1064 * Some of these might become QOM properties eventually. 1065 * Field names match the official register names as defined in the 1066 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 1067 * is used for reset values of non-constant registers; no reset_ 1068 * prefix means a constant register. 1069 * Some of these registers are split out into a substructure that 1070 * is shared with the translators to control the ISA. 1071 * 1072 * Note that if you add an ID register to the ARMISARegisters struct 1073 * you need to also update the 32-bit and 64-bit versions of the 1074 * kvm_arm_get_host_cpu_features() function to correctly populate the 1075 * field by reading the value from the KVM vCPU. 1076 */ 1077 struct ARMISARegisters { 1078 uint32_t mvfr0; 1079 uint32_t mvfr1; 1080 uint32_t mvfr2; 1081 uint32_t dbgdidr; 1082 uint32_t dbgdevid; 1083 uint32_t dbgdevid1; 1084 uint64_t reset_pmcr_el0; 1085 uint64_t idregs[NUM_ID_IDX]; 1086 } isar; 1087 uint64_t midr; 1088 uint32_t revidr; 1089 uint32_t reset_fpsid; 1090 uint64_t ctr; 1091 uint32_t reset_sctlr; 1092 uint64_t pmceid0; 1093 uint64_t pmceid1; 1094 uint64_t mp_affinity; /* MP ID without feature bits */ 1095 /* The elements of this array are the CCSIDR values for each cache, 1096 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1097 */ 1098 uint64_t ccsidr[16]; 1099 uint64_t reset_cbar; 1100 uint32_t reset_auxcr; 1101 bool reset_hivecs; 1102 uint8_t reset_l0gptsz; 1103 1104 /* 1105 * Intermediate values used during property parsing. 1106 * Once finalized, the values should be read from ID_AA64*. 1107 */ 1108 bool prop_pauth; 1109 bool prop_pauth_impdef; 1110 bool prop_pauth_qarma3; 1111 bool prop_pauth_qarma5; 1112 bool prop_lpa2; 1113 1114 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1115 uint8_t dcz_blocksize; 1116 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1117 uint8_t gm_blocksize; 1118 1119 uint64_t rvbar_prop; /* Property/input signals. */ 1120 1121 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1122 int gic_num_lrs; /* number of list registers */ 1123 int gic_vpribits; /* number of virtual priority bits */ 1124 int gic_vprebits; /* number of virtual preemption bits */ 1125 int gic_pribits; /* number of physical priority bits */ 1126 1127 /* Whether the cfgend input is high (i.e. this CPU should reset into 1128 * big-endian mode). This setting isn't used directly: instead it modifies 1129 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1130 * architecture version. 1131 */ 1132 bool cfgend; 1133 1134 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1135 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1136 1137 int32_t node_id; /* NUMA node this CPU belongs to */ 1138 1139 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1140 uint8_t device_irq_level; 1141 1142 /* Used to set the maximum vector length the cpu will support. */ 1143 uint32_t sve_max_vq; 1144 uint32_t sme_max_vq; 1145 1146 #ifdef CONFIG_USER_ONLY 1147 /* Used to set the default vector length at process start. */ 1148 uint32_t sve_default_vq; 1149 uint32_t sme_default_vq; 1150 #endif 1151 1152 ARMVQMap sve_vq; 1153 ARMVQMap sme_vq; 1154 1155 /* Generic timer counter frequency, in Hz */ 1156 uint64_t gt_cntfrq_hz; 1157 }; 1158 1159 typedef struct ARMCPUInfo { 1160 const char *name; 1161 const char *deprecation_note; 1162 void (*initfn)(Object *obj); 1163 void (*class_init)(ObjectClass *oc, const void *data); 1164 } ARMCPUInfo; 1165 1166 /** 1167 * ARMCPUClass: 1168 * @parent_realize: The parent class' realize handler. 1169 * @parent_phases: The parent class' reset phase handlers. 1170 * 1171 * An ARM CPU model. 1172 */ 1173 struct ARMCPUClass { 1174 CPUClass parent_class; 1175 1176 const ARMCPUInfo *info; 1177 DeviceRealize parent_realize; 1178 ResettablePhases parent_phases; 1179 }; 1180 1181 /* Callback functions for the generic timer's timers. */ 1182 void arm_gt_ptimer_cb(void *opaque); 1183 void arm_gt_vtimer_cb(void *opaque); 1184 void arm_gt_htimer_cb(void *opaque); 1185 void arm_gt_stimer_cb(void *opaque); 1186 void arm_gt_hvtimer_cb(void *opaque); 1187 void arm_gt_sel2timer_cb(void *opaque); 1188 void arm_gt_sel2vtimer_cb(void *opaque); 1189 1190 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1191 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1192 1193 #define ARM_AFF0_SHIFT 0 1194 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1195 #define ARM_AFF1_SHIFT 8 1196 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1197 #define ARM_AFF2_SHIFT 16 1198 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1199 #define ARM_AFF3_SHIFT 32 1200 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1201 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1202 1203 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1204 #define ARM64_AFFINITY_MASK \ 1205 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1206 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1207 1208 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1209 1210 #ifndef CONFIG_USER_ONLY 1211 extern const VMStateDescription vmstate_arm_cpu; 1212 1213 void arm_cpu_do_interrupt(CPUState *cpu); 1214 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1215 1216 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1217 MemTxAttrs *attrs); 1218 #endif /* !CONFIG_USER_ONLY */ 1219 1220 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1221 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1222 1223 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1224 int cpuid, DumpState *s); 1225 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1226 int cpuid, DumpState *s); 1227 1228 /** 1229 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1230 * @cpu: CPU (which must have been freshly reset) 1231 * @target_el: exception level to put the CPU into 1232 * @secure: whether to put the CPU in secure state 1233 * 1234 * When QEMU is directly running a guest kernel at a lower level than 1235 * EL3 it implicitly emulates some aspects of the guest firmware. 1236 * This includes that on reset we need to configure the parts of the 1237 * CPU corresponding to EL3 so that the real guest code can run at its 1238 * lower exception level. This function does that post-reset CPU setup, 1239 * for when we do direct boot of a guest kernel, and for when we 1240 * emulate PSCI and similar firmware interfaces starting a CPU at a 1241 * lower exception level. 1242 * 1243 * @target_el must be an EL implemented by the CPU between 1 and 3. 1244 * We do not support dropping into a Secure EL other than 3. 1245 * 1246 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1247 */ 1248 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1249 1250 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1251 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1252 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1253 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1254 int new_el, bool el0_a64); 1255 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1256 1257 /* 1258 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1259 * The byte at offset i from the start of the in-memory representation contains 1260 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1261 * lowest offsets are stored in the lowest memory addresses, then that nearly 1262 * matches QEMU's representation, which is to use an array of host-endian 1263 * uint64_t's, where the lower offsets are at the lower indices. To complete 1264 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1265 */ 1266 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1267 { 1268 #if HOST_BIG_ENDIAN 1269 int i; 1270 1271 for (i = 0; i < nr; ++i) { 1272 dst[i] = bswap64(src[i]); 1273 } 1274 1275 return dst; 1276 #else 1277 return src; 1278 #endif 1279 } 1280 1281 void aarch64_sync_32_to_64(CPUARMState *env); 1282 void aarch64_sync_64_to_32(CPUARMState *env); 1283 1284 int fp_exception_el(CPUARMState *env, int cur_el); 1285 int sve_exception_el(CPUARMState *env, int cur_el); 1286 int sme_exception_el(CPUARMState *env, int cur_el); 1287 1288 /** 1289 * sve_vqm1_for_el_sm: 1290 * @env: CPUARMState 1291 * @el: exception level 1292 * @sm: streaming mode 1293 * 1294 * Compute the current vector length for @el & @sm, in units of 1295 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1296 * If @sm, compute for SVL, otherwise NVL. 1297 */ 1298 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1299 1300 /* Likewise, but using @sm = PSTATE.SM. */ 1301 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1302 1303 static inline bool is_a64(CPUARMState *env) 1304 { 1305 return env->aarch64; 1306 } 1307 1308 /** 1309 * pmu_op_start/finish 1310 * @env: CPUARMState 1311 * 1312 * Convert all PMU counters between their delta form (the typical mode when 1313 * they are enabled) and the guest-visible values. These two calls must 1314 * surround any action which might affect the counters. 1315 */ 1316 void pmu_op_start(CPUARMState *env); 1317 void pmu_op_finish(CPUARMState *env); 1318 1319 /* 1320 * Called when a PMU counter is due to overflow 1321 */ 1322 void arm_pmu_timer_cb(void *opaque); 1323 1324 /** 1325 * Functions to register as EL change hooks for PMU mode filtering 1326 */ 1327 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1328 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1329 1330 /* 1331 * pmu_init 1332 * @cpu: ARMCPU 1333 * 1334 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1335 * for the current configuration 1336 */ 1337 void pmu_init(ARMCPU *cpu); 1338 1339 /* SCTLR bit meanings. Several bits have been reused in newer 1340 * versions of the architecture; in that case we define constants 1341 * for both old and new bit meanings. Code which tests against those 1342 * bits should probably check or otherwise arrange that the CPU 1343 * is the architectural version it expects. 1344 */ 1345 #define SCTLR_M (1U << 0) 1346 #define SCTLR_A (1U << 1) 1347 #define SCTLR_C (1U << 2) 1348 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1349 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1350 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1351 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1352 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1353 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1354 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1355 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1356 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1357 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1358 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1359 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1360 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1361 #define SCTLR_SED (1U << 8) /* v8 onward */ 1362 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1363 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1364 #define SCTLR_F (1U << 10) /* up to v6 */ 1365 #define SCTLR_SW (1U << 10) /* v7 */ 1366 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1367 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1368 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1369 #define SCTLR_I (1U << 12) 1370 #define SCTLR_V (1U << 13) /* AArch32 only */ 1371 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1372 #define SCTLR_RR (1U << 14) /* up to v7 */ 1373 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1374 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1375 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1376 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1377 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1378 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1379 #define SCTLR_BR (1U << 17) /* PMSA only */ 1380 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1381 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1382 #define SCTLR_WXN (1U << 19) 1383 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1384 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1385 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1386 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1387 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1388 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1389 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1390 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1391 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1392 #define SCTLR_VE (1U << 24) /* up to v7 */ 1393 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1394 #define SCTLR_EE (1U << 25) 1395 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1396 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1397 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1398 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1399 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1400 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1401 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1402 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1403 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1404 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1405 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1406 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1407 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */ 1408 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1409 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1410 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1411 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1412 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1413 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1414 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1415 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1416 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1417 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1418 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1419 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1420 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1421 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1422 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1423 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1424 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1425 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1426 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1427 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1428 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1429 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1430 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1431 1432 #define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ 1433 #define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ 1434 #define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ 1435 #define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ 1436 #define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ 1437 #define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ 1438 #define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ 1439 #define SCTLR2_ENPACM0 (1ULL << 8) /* FEAT_PAuth_LR */ 1440 #define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ 1441 #define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ 1442 #define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ 1443 #define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ 1444 1445 #define CPSR_M (0x1fU) 1446 #define CPSR_T (1U << 5) 1447 #define CPSR_F (1U << 6) 1448 #define CPSR_I (1U << 7) 1449 #define CPSR_A (1U << 8) 1450 #define CPSR_E (1U << 9) 1451 #define CPSR_IT_2_7 (0xfc00U) 1452 #define CPSR_GE (0xfU << 16) 1453 #define CPSR_IL (1U << 20) 1454 #define CPSR_DIT (1U << 21) 1455 #define CPSR_PAN (1U << 22) 1456 #define CPSR_SSBS (1U << 23) 1457 #define CPSR_J (1U << 24) 1458 #define CPSR_IT_0_1 (3U << 25) 1459 #define CPSR_Q (1U << 27) 1460 #define CPSR_V (1U << 28) 1461 #define CPSR_C (1U << 29) 1462 #define CPSR_Z (1U << 30) 1463 #define CPSR_N (1U << 31) 1464 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1465 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1466 #define ISR_FS (1U << 9) 1467 #define ISR_IS (1U << 10) 1468 1469 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1470 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1471 | CPSR_NZCV) 1472 /* Bits writable in user mode. */ 1473 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1474 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1475 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1476 1477 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1478 #define XPSR_EXCP 0x1ffU 1479 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1480 #define XPSR_IT_2_7 CPSR_IT_2_7 1481 #define XPSR_GE CPSR_GE 1482 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1483 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1484 #define XPSR_IT_0_1 CPSR_IT_0_1 1485 #define XPSR_Q CPSR_Q 1486 #define XPSR_V CPSR_V 1487 #define XPSR_C CPSR_C 1488 #define XPSR_Z CPSR_Z 1489 #define XPSR_N CPSR_N 1490 #define XPSR_NZCV CPSR_NZCV 1491 #define XPSR_IT CPSR_IT 1492 1493 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1494 * Only these are valid when in AArch64 mode; in 1495 * AArch32 mode SPSRs are basically CPSR-format. 1496 */ 1497 #define PSTATE_SP (1U) 1498 #define PSTATE_M (0xFU) 1499 #define PSTATE_nRW (1U << 4) 1500 #define PSTATE_F (1U << 6) 1501 #define PSTATE_I (1U << 7) 1502 #define PSTATE_A (1U << 8) 1503 #define PSTATE_D (1U << 9) 1504 #define PSTATE_BTYPE (3U << 10) 1505 #define PSTATE_SSBS (1U << 12) 1506 #define PSTATE_ALLINT (1U << 13) 1507 #define PSTATE_IL (1U << 20) 1508 #define PSTATE_SS (1U << 21) 1509 #define PSTATE_PAN (1U << 22) 1510 #define PSTATE_UAO (1U << 23) 1511 #define PSTATE_DIT (1U << 24) 1512 #define PSTATE_TCO (1U << 25) 1513 #define PSTATE_V (1U << 28) 1514 #define PSTATE_C (1U << 29) 1515 #define PSTATE_Z (1U << 30) 1516 #define PSTATE_N (1U << 31) 1517 #define PSTATE_EXLOCK (1ULL << 34) 1518 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1519 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1520 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1521 /* Mode values for AArch64 */ 1522 #define PSTATE_MODE_EL3h 13 1523 #define PSTATE_MODE_EL3t 12 1524 #define PSTATE_MODE_EL2h 9 1525 #define PSTATE_MODE_EL2t 8 1526 #define PSTATE_MODE_EL1h 5 1527 #define PSTATE_MODE_EL1t 4 1528 #define PSTATE_MODE_EL0t 0 1529 1530 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1531 FIELD(SVCR, SM, 0, 1) 1532 FIELD(SVCR, ZA, 1, 1) 1533 1534 /* Fields for SMCR_ELx. */ 1535 FIELD(SMCR, LEN, 0, 4) 1536 FIELD(SMCR, EZT0, 30, 1) 1537 FIELD(SMCR, FA64, 31, 1) 1538 1539 /* Write a new value to v7m.exception, thus transitioning into or out 1540 * of Handler mode; this may result in a change of active stack pointer. 1541 */ 1542 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1543 1544 /* Map EL and handler into a PSTATE_MODE. */ 1545 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1546 { 1547 return (el << 2) | handler; 1548 } 1549 1550 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1551 * interprocessing, so we don't attempt to sync with the cpsr state used by 1552 * the 32 bit decoder. 1553 */ 1554 static inline uint64_t pstate_read(CPUARMState *env) 1555 { 1556 int ZF; 1557 1558 ZF = (env->ZF == 0); 1559 return (env->NF & 0x80000000) | (ZF << 30) 1560 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1561 | env->pstate | env->daif | (env->btype << 10); 1562 } 1563 1564 static inline void pstate_write(CPUARMState *env, uint64_t val) 1565 { 1566 env->ZF = (~val) & PSTATE_Z; 1567 env->NF = val; 1568 env->CF = (val >> 29) & 1; 1569 env->VF = (val << 3) & 0x80000000; 1570 env->daif = val & PSTATE_DAIF; 1571 env->btype = (val >> 10) & 3; 1572 env->pstate = val & ~CACHED_PSTATE_BITS; 1573 } 1574 1575 /* Return the current CPSR value. */ 1576 uint32_t cpsr_read(CPUARMState *env); 1577 1578 typedef enum CPSRWriteType { 1579 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1580 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1581 CPSRWriteRaw = 2, 1582 /* trust values, no reg bank switch, no hflags rebuild */ 1583 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1584 } CPSRWriteType; 1585 1586 /* 1587 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1588 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1589 * correspond to TB flags bits cached in the hflags, unless @write_type 1590 * is CPSRWriteRaw. 1591 */ 1592 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1593 CPSRWriteType write_type); 1594 1595 /* Return the current xPSR value. */ 1596 static inline uint32_t xpsr_read(CPUARMState *env) 1597 { 1598 int ZF; 1599 ZF = (env->ZF == 0); 1600 return (env->NF & 0x80000000) | (ZF << 30) 1601 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1602 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1603 | ((env->condexec_bits & 0xfc) << 8) 1604 | (env->GE << 16) 1605 | env->v7m.exception; 1606 } 1607 1608 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1609 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1610 { 1611 if (mask & XPSR_NZCV) { 1612 env->ZF = (~val) & XPSR_Z; 1613 env->NF = val; 1614 env->CF = (val >> 29) & 1; 1615 env->VF = (val << 3) & 0x80000000; 1616 } 1617 if (mask & XPSR_Q) { 1618 env->QF = ((val & XPSR_Q) != 0); 1619 } 1620 if (mask & XPSR_GE) { 1621 env->GE = (val & XPSR_GE) >> 16; 1622 } 1623 #ifndef CONFIG_USER_ONLY 1624 if (mask & XPSR_T) { 1625 env->thumb = ((val & XPSR_T) != 0); 1626 } 1627 if (mask & XPSR_IT_0_1) { 1628 env->condexec_bits &= ~3; 1629 env->condexec_bits |= (val >> 25) & 3; 1630 } 1631 if (mask & XPSR_IT_2_7) { 1632 env->condexec_bits &= 3; 1633 env->condexec_bits |= (val >> 8) & 0xfc; 1634 } 1635 if (mask & XPSR_EXCP) { 1636 /* Note that this only happens on exception exit */ 1637 write_v7m_exception(env, val & XPSR_EXCP); 1638 } 1639 #endif 1640 } 1641 1642 #define HCR_VM (1ULL << 0) 1643 #define HCR_SWIO (1ULL << 1) 1644 #define HCR_PTW (1ULL << 2) 1645 #define HCR_FMO (1ULL << 3) 1646 #define HCR_IMO (1ULL << 4) 1647 #define HCR_AMO (1ULL << 5) 1648 #define HCR_VF (1ULL << 6) 1649 #define HCR_VI (1ULL << 7) 1650 #define HCR_VSE (1ULL << 8) 1651 #define HCR_FB (1ULL << 9) 1652 #define HCR_BSU_MASK (3ULL << 10) 1653 #define HCR_DC (1ULL << 12) 1654 #define HCR_TWI (1ULL << 13) 1655 #define HCR_TWE (1ULL << 14) 1656 #define HCR_TID0 (1ULL << 15) 1657 #define HCR_TID1 (1ULL << 16) 1658 #define HCR_TID2 (1ULL << 17) 1659 #define HCR_TID3 (1ULL << 18) 1660 #define HCR_TSC (1ULL << 19) 1661 #define HCR_TIDCP (1ULL << 20) 1662 #define HCR_TACR (1ULL << 21) 1663 #define HCR_TSW (1ULL << 22) 1664 #define HCR_TPCP (1ULL << 23) 1665 #define HCR_TPU (1ULL << 24) 1666 #define HCR_TTLB (1ULL << 25) 1667 #define HCR_TVM (1ULL << 26) 1668 #define HCR_TGE (1ULL << 27) 1669 #define HCR_TDZ (1ULL << 28) 1670 #define HCR_HCD (1ULL << 29) 1671 #define HCR_TRVM (1ULL << 30) 1672 #define HCR_RW (1ULL << 31) 1673 #define HCR_CD (1ULL << 32) 1674 #define HCR_ID (1ULL << 33) 1675 #define HCR_E2H (1ULL << 34) 1676 #define HCR_TLOR (1ULL << 35) 1677 #define HCR_TERR (1ULL << 36) 1678 #define HCR_TEA (1ULL << 37) 1679 #define HCR_MIOCNCE (1ULL << 38) 1680 #define HCR_TME (1ULL << 39) 1681 #define HCR_APK (1ULL << 40) 1682 #define HCR_API (1ULL << 41) 1683 #define HCR_NV (1ULL << 42) 1684 #define HCR_NV1 (1ULL << 43) 1685 #define HCR_AT (1ULL << 44) 1686 #define HCR_NV2 (1ULL << 45) 1687 #define HCR_FWB (1ULL << 46) 1688 #define HCR_FIEN (1ULL << 47) 1689 #define HCR_GPF (1ULL << 48) 1690 #define HCR_TID4 (1ULL << 49) 1691 #define HCR_TICAB (1ULL << 50) 1692 #define HCR_AMVOFFEN (1ULL << 51) 1693 #define HCR_TOCU (1ULL << 52) 1694 #define HCR_ENSCXT (1ULL << 53) 1695 #define HCR_TTLBIS (1ULL << 54) 1696 #define HCR_TTLBOS (1ULL << 55) 1697 #define HCR_ATA (1ULL << 56) 1698 #define HCR_DCT (1ULL << 57) 1699 #define HCR_TID5 (1ULL << 58) 1700 #define HCR_TWEDEN (1ULL << 59) 1701 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1702 1703 #define SCR_NS (1ULL << 0) 1704 #define SCR_IRQ (1ULL << 1) 1705 #define SCR_FIQ (1ULL << 2) 1706 #define SCR_EA (1ULL << 3) 1707 #define SCR_FW (1ULL << 4) 1708 #define SCR_AW (1ULL << 5) 1709 #define SCR_NET (1ULL << 6) 1710 #define SCR_SMD (1ULL << 7) 1711 #define SCR_HCE (1ULL << 8) 1712 #define SCR_SIF (1ULL << 9) 1713 #define SCR_RW (1ULL << 10) 1714 #define SCR_ST (1ULL << 11) 1715 #define SCR_TWI (1ULL << 12) 1716 #define SCR_TWE (1ULL << 13) 1717 #define SCR_TLOR (1ULL << 14) 1718 #define SCR_TERR (1ULL << 15) 1719 #define SCR_APK (1ULL << 16) 1720 #define SCR_API (1ULL << 17) 1721 #define SCR_EEL2 (1ULL << 18) 1722 #define SCR_EASE (1ULL << 19) 1723 #define SCR_NMEA (1ULL << 20) 1724 #define SCR_FIEN (1ULL << 21) 1725 #define SCR_ENSCXT (1ULL << 25) 1726 #define SCR_ATA (1ULL << 26) 1727 #define SCR_FGTEN (1ULL << 27) 1728 #define SCR_ECVEN (1ULL << 28) 1729 #define SCR_TWEDEN (1ULL << 29) 1730 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1731 #define SCR_TME (1ULL << 34) 1732 #define SCR_AMVOFFEN (1ULL << 35) 1733 #define SCR_ENAS0 (1ULL << 36) 1734 #define SCR_ADEN (1ULL << 37) 1735 #define SCR_HXEN (1ULL << 38) 1736 #define SCR_GCSEN (1ULL << 39) 1737 #define SCR_TRNDR (1ULL << 40) 1738 #define SCR_ENTP2 (1ULL << 41) 1739 #define SCR_TCR2EN (1ULL << 43) 1740 #define SCR_SCTLR2EN (1ULL << 44) 1741 #define SCR_PIEN (1ULL << 45) 1742 #define SCR_AIEN (1ULL << 46) 1743 #define SCR_GPF (1ULL << 48) 1744 #define SCR_MECEN (1ULL << 49) 1745 #define SCR_NSE (1ULL << 62) 1746 1747 /* GCSCR_ELx fields */ 1748 #define GCSCR_PCRSEL (1ULL << 0) 1749 #define GCSCR_RVCHKEN (1ULL << 5) 1750 #define GCSCR_EXLOCKEN (1ULL << 6) 1751 #define GCSCR_PUSHMEN (1ULL << 8) 1752 #define GCSCR_STREN (1ULL << 9) 1753 #define GCSCRE0_NTR (1ULL << 10) 1754 1755 /* Return the current FPSCR value. */ 1756 uint32_t vfp_get_fpscr(CPUARMState *env); 1757 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1758 1759 /* 1760 * FPCR, Floating Point Control Register 1761 * FPSR, Floating Point Status Register 1762 * 1763 * For A64 floating point control and status bits are stored in 1764 * two logically distinct registers, FPCR and FPSR. We store these 1765 * in QEMU in vfp.fpcr and vfp.fpsr. 1766 * For A32 there was only one register, FPSCR. The bits are arranged 1767 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions, 1768 * so we can use appropriate masking to handle FPSCR reads and writes. 1769 * Note that the FPCR has some bits which are not visible in the 1770 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged. 1771 */ 1772 1773 /* FPCR bits */ 1774 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */ 1775 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */ 1776 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */ 1777 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1778 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1779 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1780 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1781 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1782 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */ 1783 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1784 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */ 1785 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1786 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */ 1787 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1788 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1789 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1790 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1791 1792 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1793 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1794 #define FPCR_LTPSIZE_LENGTH 3 1795 1796 /* Cumulative exception trap enable bits */ 1797 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE) 1798 1799 /* FPSR bits */ 1800 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */ 1801 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */ 1802 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */ 1803 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */ 1804 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */ 1805 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */ 1806 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */ 1807 #define FPSR_V (1 << 28) /* FP overflow flag */ 1808 #define FPSR_C (1 << 29) /* FP carry flag */ 1809 #define FPSR_Z (1 << 30) /* FP zero flag */ 1810 #define FPSR_N (1 << 31) /* FP negative flag */ 1811 1812 /* Cumulative exception status bits */ 1813 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC) 1814 1815 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V) 1816 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC) 1817 1818 /* A32 FPSCR bits which architecturally map to FPSR bits */ 1819 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK) 1820 /* A32 FPSCR bits which architecturally map to FPCR bits */ 1821 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \ 1822 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \ 1823 FPCR_FZ | FPCR_DN | FPCR_AHP) 1824 /* These masks don't overlap: each bit lives in only one place */ 1825 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK); 1826 1827 /** 1828 * vfp_get_fpsr: read the AArch64 FPSR 1829 * @env: CPU context 1830 * 1831 * Return the current AArch64 FPSR value 1832 */ 1833 uint32_t vfp_get_fpsr(CPUARMState *env); 1834 1835 /** 1836 * vfp_get_fpcr: read the AArch64 FPCR 1837 * @env: CPU context 1838 * 1839 * Return the current AArch64 FPCR value 1840 */ 1841 uint32_t vfp_get_fpcr(CPUARMState *env); 1842 1843 /** 1844 * vfp_set_fpsr: write the AArch64 FPSR 1845 * @env: CPU context 1846 * @value: new value 1847 */ 1848 void vfp_set_fpsr(CPUARMState *env, uint32_t value); 1849 1850 /** 1851 * vfp_set_fpcr: write the AArch64 FPCR 1852 * @env: CPU context 1853 * @value: new value 1854 */ 1855 void vfp_set_fpcr(CPUARMState *env, uint32_t value); 1856 1857 enum arm_cpu_mode { 1858 ARM_CPU_MODE_USR = 0x10, 1859 ARM_CPU_MODE_FIQ = 0x11, 1860 ARM_CPU_MODE_IRQ = 0x12, 1861 ARM_CPU_MODE_SVC = 0x13, 1862 ARM_CPU_MODE_MON = 0x16, 1863 ARM_CPU_MODE_ABT = 0x17, 1864 ARM_CPU_MODE_HYP = 0x1a, 1865 ARM_CPU_MODE_UND = 0x1b, 1866 ARM_CPU_MODE_SYS = 0x1f 1867 }; 1868 1869 /* VFP system registers. */ 1870 #define ARM_VFP_FPSID 0 1871 #define ARM_VFP_FPSCR 1 1872 #define ARM_VFP_MVFR2 5 1873 #define ARM_VFP_MVFR1 6 1874 #define ARM_VFP_MVFR0 7 1875 #define ARM_VFP_FPEXC 8 1876 #define ARM_VFP_FPINST 9 1877 #define ARM_VFP_FPINST2 10 1878 /* These ones are M-profile only */ 1879 #define ARM_VFP_FPSCR_NZCVQC 2 1880 #define ARM_VFP_VPR 12 1881 #define ARM_VFP_P0 13 1882 #define ARM_VFP_FPCXT_NS 14 1883 #define ARM_VFP_FPCXT_S 15 1884 1885 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1886 #define QEMU_VFP_FPSCR_NZCV 0xffff 1887 1888 /* V7M CCR bits */ 1889 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1890 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1891 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1892 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1893 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1894 FIELD(V7M_CCR, STKALIGN, 9, 1) 1895 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1896 FIELD(V7M_CCR, DC, 16, 1) 1897 FIELD(V7M_CCR, IC, 17, 1) 1898 FIELD(V7M_CCR, BP, 18, 1) 1899 FIELD(V7M_CCR, LOB, 19, 1) 1900 FIELD(V7M_CCR, TRD, 20, 1) 1901 1902 /* V7M SCR bits */ 1903 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1904 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1905 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1906 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1907 1908 /* V7M AIRCR bits */ 1909 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1910 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1911 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1912 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1913 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1914 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1915 FIELD(V7M_AIRCR, PRIS, 14, 1) 1916 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1917 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1918 1919 /* V7M CFSR bits for MMFSR */ 1920 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1921 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1922 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1923 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1924 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1925 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1926 1927 /* V7M CFSR bits for BFSR */ 1928 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1929 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1930 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1931 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1932 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1933 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1934 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1935 1936 /* V7M CFSR bits for UFSR */ 1937 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1938 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1939 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1940 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1941 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1942 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1943 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1944 1945 /* V7M CFSR bit masks covering all of the subregister bits */ 1946 FIELD(V7M_CFSR, MMFSR, 0, 8) 1947 FIELD(V7M_CFSR, BFSR, 8, 8) 1948 FIELD(V7M_CFSR, UFSR, 16, 16) 1949 1950 /* V7M HFSR bits */ 1951 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1952 FIELD(V7M_HFSR, FORCED, 30, 1) 1953 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1954 1955 /* V7M DFSR bits */ 1956 FIELD(V7M_DFSR, HALTED, 0, 1) 1957 FIELD(V7M_DFSR, BKPT, 1, 1) 1958 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1959 FIELD(V7M_DFSR, VCATCH, 3, 1) 1960 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1961 1962 /* V7M SFSR bits */ 1963 FIELD(V7M_SFSR, INVEP, 0, 1) 1964 FIELD(V7M_SFSR, INVIS, 1, 1) 1965 FIELD(V7M_SFSR, INVER, 2, 1) 1966 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1967 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1968 FIELD(V7M_SFSR, LSPERR, 5, 1) 1969 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1970 FIELD(V7M_SFSR, LSERR, 7, 1) 1971 1972 /* v7M MPU_CTRL bits */ 1973 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1974 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1975 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1976 1977 /* v7M CLIDR bits */ 1978 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1979 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1980 FIELD(V7M_CLIDR, LOC, 24, 3) 1981 FIELD(V7M_CLIDR, LOUU, 27, 3) 1982 FIELD(V7M_CLIDR, ICB, 30, 2) 1983 1984 FIELD(V7M_CSSELR, IND, 0, 1) 1985 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1986 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1987 * define a mask for this and check that it doesn't permit running off 1988 * the end of the array. 1989 */ 1990 FIELD(V7M_CSSELR, INDEX, 0, 4) 1991 1992 /* v7M FPCCR bits */ 1993 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1994 FIELD(V7M_FPCCR, USER, 1, 1) 1995 FIELD(V7M_FPCCR, S, 2, 1) 1996 FIELD(V7M_FPCCR, THREAD, 3, 1) 1997 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1998 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1999 FIELD(V7M_FPCCR, BFRDY, 6, 1) 2000 FIELD(V7M_FPCCR, SFRDY, 7, 1) 2001 FIELD(V7M_FPCCR, MONRDY, 8, 1) 2002 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 2003 FIELD(V7M_FPCCR, UFRDY, 10, 1) 2004 FIELD(V7M_FPCCR, RES0, 11, 15) 2005 FIELD(V7M_FPCCR, TS, 26, 1) 2006 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 2007 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 2008 FIELD(V7M_FPCCR, LSPENS, 29, 1) 2009 FIELD(V7M_FPCCR, LSPEN, 30, 1) 2010 FIELD(V7M_FPCCR, ASPEN, 31, 1) 2011 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2012 #define R_V7M_FPCCR_BANKED_MASK \ 2013 (R_V7M_FPCCR_LSPACT_MASK | \ 2014 R_V7M_FPCCR_USER_MASK | \ 2015 R_V7M_FPCCR_THREAD_MASK | \ 2016 R_V7M_FPCCR_MMRDY_MASK | \ 2017 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2018 R_V7M_FPCCR_UFRDY_MASK | \ 2019 R_V7M_FPCCR_ASPEN_MASK) 2020 2021 /* v7M VPR bits */ 2022 FIELD(V7M_VPR, P0, 0, 16) 2023 FIELD(V7M_VPR, MASK01, 16, 4) 2024 FIELD(V7M_VPR, MASK23, 20, 4) 2025 2026 FIELD(GPCCR, PPS, 0, 3) 2027 FIELD(GPCCR, RLPAD, 5, 1) 2028 FIELD(GPCCR, NSPAD, 6, 1) 2029 FIELD(GPCCR, SPAD, 7, 1) 2030 FIELD(GPCCR, IRGN, 8, 2) 2031 FIELD(GPCCR, ORGN, 10, 2) 2032 FIELD(GPCCR, SH, 12, 2) 2033 FIELD(GPCCR, PGS, 14, 2) 2034 FIELD(GPCCR, GPC, 16, 1) 2035 FIELD(GPCCR, GPCP, 17, 1) 2036 FIELD(GPCCR, TBGPCD, 18, 1) 2037 FIELD(GPCCR, NSO, 19, 1) 2038 FIELD(GPCCR, L0GPTSZ, 20, 4) 2039 FIELD(GPCCR, APPSAA, 24, 1) 2040 2041 FIELD(MFAR, FPA, 12, 40) 2042 FIELD(MFAR, NSE, 62, 1) 2043 FIELD(MFAR, NS, 63, 1) 2044 2045 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2046 2047 /* If adding a feature bit which corresponds to a Linux ELF 2048 * HWCAP bit, remember to update the feature-bit-to-hwcap 2049 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2050 */ 2051 enum arm_features { 2052 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2053 ARM_FEATURE_V6, 2054 ARM_FEATURE_V6K, 2055 ARM_FEATURE_V7, 2056 ARM_FEATURE_THUMB2, 2057 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2058 ARM_FEATURE_NEON, 2059 ARM_FEATURE_M, /* Microcontroller profile. */ 2060 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2061 ARM_FEATURE_THUMB2EE, 2062 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2063 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2064 ARM_FEATURE_V4T, 2065 ARM_FEATURE_V5, 2066 ARM_FEATURE_STRONGARM, 2067 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2068 ARM_FEATURE_GENERIC_TIMER, 2069 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2070 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2071 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2072 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2073 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2074 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2075 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2076 ARM_FEATURE_V8, 2077 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2078 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2079 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2080 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2081 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2082 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2083 ARM_FEATURE_PMU, /* has PMU support */ 2084 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2085 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2086 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2087 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2088 /* 2089 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz 2090 * if the board doesn't set a value, instead of 1GHz. It is for backwards 2091 * compatibility and used only with CPU definitions that were already 2092 * in QEMU before we changed the default. It should not be set on any 2093 * CPU types added in future. 2094 */ 2095 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ 2096 }; 2097 2098 static inline int arm_feature(CPUARMState *env, int feature) 2099 { 2100 return (env->features & (1ULL << feature)) != 0; 2101 } 2102 2103 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2104 2105 /* 2106 * ARM v9 security states. 2107 * The ordering of the enumeration corresponds to the low 2 bits 2108 * of the GPI value, and (except for Root) the concat of NSE:NS. 2109 */ 2110 2111 typedef enum ARMSecuritySpace { 2112 ARMSS_Secure = 0, 2113 ARMSS_NonSecure = 1, 2114 ARMSS_Root = 2, 2115 ARMSS_Realm = 3, 2116 } ARMSecuritySpace; 2117 2118 /* Return true if @space is secure, in the pre-v9 sense. */ 2119 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2120 { 2121 return space == ARMSS_Secure || space == ARMSS_Root; 2122 } 2123 2124 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2125 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2126 { 2127 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2128 } 2129 2130 #if !defined(CONFIG_USER_ONLY) 2131 /** 2132 * arm_security_space_below_el3: 2133 * @env: cpu context 2134 * 2135 * Return the security space of exception levels below EL3, following 2136 * an exception return to those levels. Unlike arm_security_space, 2137 * this doesn't care about the current EL. 2138 */ 2139 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2140 2141 /** 2142 * arm_is_secure_below_el3: 2143 * @env: cpu context 2144 * 2145 * Return true if exception levels below EL3 are in secure state, 2146 * or would be following an exception return to those levels. 2147 */ 2148 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2149 { 2150 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2151 return ss == ARMSS_Secure; 2152 } 2153 2154 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2155 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2156 { 2157 assert(!arm_feature(env, ARM_FEATURE_M)); 2158 if (arm_feature(env, ARM_FEATURE_EL3)) { 2159 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2160 /* CPU currently in AArch64 state and EL3 */ 2161 return true; 2162 } else if (!is_a64(env) && 2163 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2164 /* CPU currently in AArch32 state and monitor mode */ 2165 return true; 2166 } 2167 } 2168 return false; 2169 } 2170 2171 /** 2172 * arm_security_space: 2173 * @env: cpu context 2174 * 2175 * Return the current security space of the cpu. 2176 */ 2177 ARMSecuritySpace arm_security_space(CPUARMState *env); 2178 2179 /** 2180 * arm_is_secure: 2181 * @env: cpu context 2182 * 2183 * Return true if the processor is in secure state. 2184 */ 2185 static inline bool arm_is_secure(CPUARMState *env) 2186 { 2187 return arm_space_is_secure(arm_security_space(env)); 2188 } 2189 2190 /* 2191 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2192 * This corresponds to the pseudocode EL2Enabled(). 2193 */ 2194 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2195 ARMSecuritySpace space) 2196 { 2197 assert(space != ARMSS_Root); 2198 return arm_feature(env, ARM_FEATURE_EL2) 2199 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2200 } 2201 2202 static inline bool arm_is_el2_enabled(CPUARMState *env) 2203 { 2204 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2205 } 2206 2207 #else 2208 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2209 { 2210 return ARMSS_NonSecure; 2211 } 2212 2213 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2214 { 2215 return false; 2216 } 2217 2218 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2219 { 2220 return false; 2221 } 2222 2223 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2224 { 2225 return ARMSS_NonSecure; 2226 } 2227 2228 static inline bool arm_is_secure(CPUARMState *env) 2229 { 2230 return false; 2231 } 2232 2233 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2234 ARMSecuritySpace space) 2235 { 2236 return false; 2237 } 2238 2239 static inline bool arm_is_el2_enabled(CPUARMState *env) 2240 { 2241 return false; 2242 } 2243 #endif 2244 2245 /** 2246 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2247 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2248 * "for all purposes other than a direct read or write access of HCR_EL2." 2249 * Not included here is HCR_RW. 2250 */ 2251 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2252 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2253 uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env); 2254 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2255 2256 /* 2257 * Function for determining whether guest cp register reads and writes should 2258 * access the secure or non-secure bank of a cp register. When EL3 is 2259 * operating in AArch32 state, the NS-bit determines whether the secure 2260 * instance of a cp register should be used. When EL3 is AArch64 (or if 2261 * it doesn't exist at all) then there is no register banking, and all 2262 * accesses are to the non-secure version. 2263 */ 2264 bool access_secure_reg(CPUARMState *env); 2265 2266 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2267 uint32_t cur_el, bool secure); 2268 2269 /* Return the highest implemented Exception Level */ 2270 static inline int arm_highest_el(CPUARMState *env) 2271 { 2272 if (arm_feature(env, ARM_FEATURE_EL3)) { 2273 return 3; 2274 } 2275 if (arm_feature(env, ARM_FEATURE_EL2)) { 2276 return 2; 2277 } 2278 return 1; 2279 } 2280 2281 /* Return true if a v7M CPU is in Handler mode */ 2282 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2283 { 2284 return env->v7m.exception != 0; 2285 } 2286 2287 /** 2288 * write_list_to_cpustate 2289 * @cpu: ARMCPU 2290 * 2291 * For each register listed in the ARMCPU cpreg_indexes list, write 2292 * its value from the cpreg_values list into the ARMCPUState structure. 2293 * This updates TCG's working data structures from KVM data or 2294 * from incoming migration state. 2295 * 2296 * Returns: true if all register values were updated correctly, 2297 * false if some register was unknown or could not be written. 2298 * Note that we do not stop early on failure -- we will attempt 2299 * writing all registers in the list. 2300 */ 2301 bool write_list_to_cpustate(ARMCPU *cpu); 2302 2303 /** 2304 * write_cpustate_to_list: 2305 * @cpu: ARMCPU 2306 * @kvm_sync: true if this is for syncing back to KVM 2307 * 2308 * For each register listed in the ARMCPU cpreg_indexes list, write 2309 * its value from the ARMCPUState structure into the cpreg_values list. 2310 * This is used to copy info from TCG's working data structures into 2311 * KVM or for outbound migration. 2312 * 2313 * @kvm_sync is true if we are doing this in order to sync the 2314 * register state back to KVM. In this case we will only update 2315 * values in the list if the previous list->cpustate sync actually 2316 * successfully wrote the CPU state. Otherwise we will keep the value 2317 * that is in the list. 2318 * 2319 * Returns: true if all register values were read correctly, 2320 * false if some register was unknown or could not be read. 2321 * Note that we do not stop early on failure -- we will attempt 2322 * reading all registers in the list. 2323 */ 2324 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2325 2326 #define ARM_CPUID_TI915T 0x54029152 2327 #define ARM_CPUID_TI925T 0x54029252 2328 2329 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2330 2331 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2332 2333 /* Indexes used when registering address spaces with cpu_address_space_init */ 2334 typedef enum ARMASIdx { 2335 ARMASIdx_NS = 0, 2336 ARMASIdx_S = 1, 2337 ARMASIdx_TagNS = 2, 2338 ARMASIdx_TagS = 3, 2339 } ARMASIdx; 2340 2341 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2342 { 2343 /* Assert the relative order of the physical mmu indexes. */ 2344 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2345 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2346 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2347 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2348 2349 return ARMMMUIdx_Phys_S + space; 2350 } 2351 2352 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2353 { 2354 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2355 return idx - ARMMMUIdx_Phys_S; 2356 } 2357 2358 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2359 { 2360 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2361 * CSSELR is RAZ/WI. 2362 */ 2363 return (GET_IDREG(&cpu->isar, CLIDR) & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2364 } 2365 2366 static inline bool arm_sctlr_b(CPUARMState *env) 2367 { 2368 return 2369 /* We need not implement SCTLR.ITD in user-mode emulation, so 2370 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2371 * This lets people run BE32 binaries with "-cpu any". 2372 */ 2373 #ifndef CONFIG_USER_ONLY 2374 !arm_feature(env, ARM_FEATURE_V7) && 2375 #endif 2376 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2377 } 2378 2379 uint64_t arm_sctlr(CPUARMState *env, int el); 2380 2381 /* 2382 * We have more than 32-bits worth of state per TB, so we split the data 2383 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2384 * We collect these two parts in CPUARMTBFlags where they are named 2385 * flags and flags2 respectively. 2386 * 2387 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored 2388 * in flags. The flags that are specific to a given mode are stored in flags2. 2389 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32. 2390 * 2391 * The bits for 32-bit A-profile and M-profile partially overlap: 2392 * 2393 * 31 23 11 10 0 2394 * +-------------+----------+----------------+ 2395 * | | | TBFLAG_A32 | 2396 * | TBFLAG_AM32 | +-----+----------+ 2397 * | | |TBFLAG_M32| 2398 * +-------------+----------------+----------+ 2399 * 31 23 6 5 0 2400 * 2401 * Unless otherwise noted, these bits are cached in env->hflags. 2402 */ 2403 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2404 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2405 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2406 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2407 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2408 /* Target EL if we take a floating-point-disabled exception */ 2409 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2410 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2411 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2412 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 2413 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 2414 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 2415 2416 /* 2417 * Bit usage when in AArch32 state, both A- and M-profile. 2418 */ 2419 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 2420 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 2421 2422 /* 2423 * Bit usage when in AArch32 state, for A-profile only. 2424 */ 2425 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 2426 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 2427 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 2428 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 2429 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 2430 /* 2431 * Indicates whether cp register reads and writes by guest code should access 2432 * the secure or nonsecure bank of banked registers; note that this is not 2433 * the same thing as the current security state of the processor! 2434 */ 2435 FIELD(TBFLAG_A32, NS, 10, 1) 2436 /* 2437 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 2438 * This requires an SME trap from AArch32 mode when using NEON. 2439 */ 2440 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 2441 2442 /* 2443 * Bit usage when in AArch32 state, for M-profile only. 2444 */ 2445 /* Handler (ie not Thread) mode */ 2446 FIELD(TBFLAG_M32, HANDLER, 0, 1) 2447 /* Whether we should generate stack-limit checks */ 2448 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 2449 /* Set if FPCCR.LSPACT is set */ 2450 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 2451 /* Set if we must create a new FP context */ 2452 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 2453 /* Set if FPCCR.S does not match current security state */ 2454 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 2455 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 2456 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 2457 /* Set if in secure mode */ 2458 FIELD(TBFLAG_M32, SECURE, 6, 1) 2459 2460 /* 2461 * Bit usage when in AArch64 state 2462 */ 2463 FIELD(TBFLAG_A64, TBII, 0, 2) 2464 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 2465 /* The current vector length, either NVL or SVL. */ 2466 FIELD(TBFLAG_A64, VL, 4, 4) 2467 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 2468 FIELD(TBFLAG_A64, BT, 9, 1) 2469 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 2470 FIELD(TBFLAG_A64, TBID, 12, 2) 2471 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 2472 FIELD(TBFLAG_A64, ATA, 15, 1) 2473 FIELD(TBFLAG_A64, TCMA, 16, 2) 2474 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 2475 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 2476 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 2477 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 2478 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 2479 FIELD(TBFLAG_A64, SVL, 24, 4) 2480 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 2481 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 2482 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 2483 FIELD(TBFLAG_A64, NAA, 30, 1) 2484 FIELD(TBFLAG_A64, ATA0, 31, 1) 2485 FIELD(TBFLAG_A64, NV, 32, 1) 2486 FIELD(TBFLAG_A64, NV1, 33, 1) 2487 FIELD(TBFLAG_A64, NV2, 34, 1) 2488 FIELD(TBFLAG_A64, E2H, 35, 1) 2489 /* Set if FEAT_NV2 RAM accesses are big-endian */ 2490 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 2491 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ 2492 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ 2493 FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2) 2494 FIELD(TBFLAG_A64, GCS_EN, 41, 1) 2495 FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1) 2496 FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2) 2497 2498 /* 2499 * Helpers for using the above. Note that only the A64 accessors use 2500 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 2501 * word either is or might be 32 bits only. 2502 */ 2503 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 2504 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 2505 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 2506 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 2507 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 2508 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 2509 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 2510 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 2511 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 2512 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 2513 2514 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 2515 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 2516 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 2517 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 2518 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 2519 2520 /** 2521 * sve_vq 2522 * @env: the cpu context 2523 * 2524 * Return the VL cached within env->hflags, in units of quadwords. 2525 */ 2526 static inline int sve_vq(CPUARMState *env) 2527 { 2528 return EX_TBFLAG_A64(env->hflags, VL) + 1; 2529 } 2530 2531 /** 2532 * sme_vq 2533 * @env: the cpu context 2534 * 2535 * Return the SVL cached within env->hflags, in units of quadwords. 2536 */ 2537 static inline int sme_vq(CPUARMState *env) 2538 { 2539 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 2540 } 2541 2542 static inline bool bswap_code(bool sctlr_b) 2543 { 2544 #ifdef CONFIG_USER_ONLY 2545 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 2546 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 2547 * would also end up as a mixed-endian mode with BE code, LE data. 2548 */ 2549 return TARGET_BIG_ENDIAN ^ sctlr_b; 2550 #else 2551 /* All code access in ARM is little endian, and there are no loaders 2552 * doing swaps that need to be reversed 2553 */ 2554 return 0; 2555 #endif 2556 } 2557 2558 enum { 2559 QEMU_PSCI_CONDUIT_DISABLED = 0, 2560 QEMU_PSCI_CONDUIT_SMC = 1, 2561 QEMU_PSCI_CONDUIT_HVC = 2, 2562 }; 2563 2564 #ifndef CONFIG_USER_ONLY 2565 /* Return the address space index to use for a memory access */ 2566 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 2567 { 2568 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 2569 } 2570 2571 /* Return the AddressSpace to use for a memory access 2572 * (which depends on whether the access is S or NS, and whether 2573 * the board gave us a separate AddressSpace for S accesses). 2574 */ 2575 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 2576 { 2577 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 2578 } 2579 #endif 2580 2581 /** 2582 * arm_register_pre_el_change_hook: 2583 * Register a hook function which will be called immediately before this 2584 * CPU changes exception level or mode. The hook function will be 2585 * passed a pointer to the ARMCPU and the opaque data pointer passed 2586 * to this function when the hook was registered. 2587 * 2588 * Note that if a pre-change hook is called, any registered post-change hooks 2589 * are guaranteed to subsequently be called. 2590 */ 2591 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 2592 void *opaque); 2593 /** 2594 * arm_register_el_change_hook: 2595 * Register a hook function which will be called immediately after this 2596 * CPU changes exception level or mode. The hook function will be 2597 * passed a pointer to the ARMCPU and the opaque data pointer passed 2598 * to this function when the hook was registered. 2599 * 2600 * Note that any registered hooks registered here are guaranteed to be called 2601 * if pre-change hooks have been. 2602 */ 2603 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 2604 *opaque); 2605 2606 /** 2607 * arm_rebuild_hflags: 2608 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 2609 */ 2610 void arm_rebuild_hflags(CPUARMState *env); 2611 2612 /** 2613 * aa32_vfp_dreg: 2614 * Return a pointer to the Dn register within env in 32-bit mode. 2615 */ 2616 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 2617 { 2618 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 2619 } 2620 2621 /** 2622 * aa32_vfp_qreg: 2623 * Return a pointer to the Qn register within env in 32-bit mode. 2624 */ 2625 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 2626 { 2627 return &env->vfp.zregs[regno].d[0]; 2628 } 2629 2630 /** 2631 * aa64_vfp_qreg: 2632 * Return a pointer to the Qn register within env in 64-bit mode. 2633 */ 2634 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 2635 { 2636 return &env->vfp.zregs[regno].d[0]; 2637 } 2638 2639 /* Shared between translate-sve.c and sve_helper.c. */ 2640 extern const uint64_t pred_esz_masks[5]; 2641 2642 /* 2643 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 2644 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 2645 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 2646 */ 2647 #define PAGE_BTI PAGE_TARGET_1 2648 #define PAGE_MTE PAGE_TARGET_2 2649 2650 /* We associate one allocation tag per 16 bytes, the minimum. */ 2651 #define LOG2_TAG_GRANULE 4 2652 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 2653 2654 #endif 2655