1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU LoongArch CPU 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef LOONGARCH_CPU_H 9 #define LOONGARCH_CPU_H 10 11 #include "qemu/int128.h" 12 #include "exec/cpu-common.h" 13 #include "exec/cpu-defs.h" 14 #include "exec/cpu-interrupt.h" 15 #include "fpu/softfloat-types.h" 16 #include "hw/registerfields.h" 17 #include "qemu/timer.h" 18 #ifndef CONFIG_USER_ONLY 19 #include "system/memory.h" 20 #endif 21 #include "cpu-csr.h" 22 #include "cpu-qom.h" 23 24 #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ 25 #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ 26 #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ 27 #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ 28 29 FIELD(FCSR0, ENABLES, 0, 5) 30 FIELD(FCSR0, RM, 8, 2) 31 FIELD(FCSR0, FLAGS, 16, 5) 32 FIELD(FCSR0, CAUSE, 24, 5) 33 34 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) 35 #define SET_FP_CAUSE(REG, V) \ 36 do { \ 37 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ 38 } while (0) 39 #define UPDATE_FP_CAUSE(REG, V) \ 40 do { \ 41 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \ 42 } while (0) 43 44 #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) 45 #define SET_FP_ENABLES(REG, V) \ 46 do { \ 47 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ 48 } while (0) 49 50 #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) 51 #define SET_FP_FLAGS(REG, V) \ 52 do { \ 53 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ 54 } while (0) 55 56 #define UPDATE_FP_FLAGS(REG, V) \ 57 do { \ 58 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ 59 } while (0) 60 61 #define FP_INEXACT 1 62 #define FP_UNDERFLOW 2 63 #define FP_OVERFLOW 4 64 #define FP_DIV0 8 65 #define FP_INVALID 16 66 67 #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) 68 #define EXCODE_MCODE(code) ( (code) & 0x3f ) 69 #define EXCODE_SUBCODE(code) ( (code) >> 6 ) 70 71 #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ 72 #define EXCCODE_INT EXCODE(0, 0) 73 #define EXCCODE_PIL EXCODE(1, 0) 74 #define EXCCODE_PIS EXCODE(2, 0) 75 #define EXCCODE_PIF EXCODE(3, 0) 76 #define EXCCODE_PME EXCODE(4, 0) 77 #define EXCCODE_PNR EXCODE(5, 0) 78 #define EXCCODE_PNX EXCODE(6, 0) 79 #define EXCCODE_PPI EXCODE(7, 0) 80 #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ 81 #define EXCCODE_ADEM EXCODE(8, 1) 82 #define EXCCODE_ALE EXCODE(9, 0) 83 #define EXCCODE_BCE EXCODE(10, 0) 84 #define EXCCODE_SYS EXCODE(11, 0) 85 #define EXCCODE_BRK EXCODE(12, 0) 86 #define EXCCODE_INE EXCODE(13, 0) 87 #define EXCCODE_IPE EXCODE(14, 0) 88 #define EXCCODE_FPD EXCODE(15, 0) 89 #define EXCCODE_SXD EXCODE(16, 0) 90 #define EXCCODE_ASXD EXCODE(17, 0) 91 #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ 92 #define EXCCODE_VFPE EXCODE(18, 1) 93 #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ 94 #define EXCCODE_WPEM EXCODE(19, 1) 95 #define EXCCODE_BTD EXCODE(20, 0) 96 #define EXCCODE_BTE EXCODE(21, 0) 97 #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ 98 99 /* cpucfg[0] bits */ 100 FIELD(CPUCFG0, PRID, 0, 32) 101 102 /* cpucfg[1] bits */ 103 FIELD(CPUCFG1, ARCH, 0, 2) 104 FIELD(CPUCFG1, PGMMU, 2, 1) 105 FIELD(CPUCFG1, IOCSR, 3, 1) 106 FIELD(CPUCFG1, PALEN, 4, 8) 107 FIELD(CPUCFG1, VALEN, 12, 8) 108 FIELD(CPUCFG1, UAL, 20, 1) 109 FIELD(CPUCFG1, RI, 21, 1) 110 FIELD(CPUCFG1, EP, 22, 1) 111 FIELD(CPUCFG1, RPLV, 23, 1) 112 FIELD(CPUCFG1, HP, 24, 1) 113 FIELD(CPUCFG1, CRC, 25, 1) 114 FIELD(CPUCFG1, MSG_INT, 26, 1) 115 116 /* cpucfg[1].arch */ 117 #define CPUCFG1_ARCH_LA32R 0 118 #define CPUCFG1_ARCH_LA32 1 119 #define CPUCFG1_ARCH_LA64 2 120 121 /* cpucfg[2] bits */ 122 FIELD(CPUCFG2, FP, 0, 1) 123 FIELD(CPUCFG2, FP_SP, 1, 1) 124 FIELD(CPUCFG2, FP_DP, 2, 1) 125 FIELD(CPUCFG2, FP_VER, 3, 3) 126 FIELD(CPUCFG2, LSX, 6, 1) 127 FIELD(CPUCFG2, LASX, 7, 1) 128 FIELD(CPUCFG2, COMPLEX, 8, 1) 129 FIELD(CPUCFG2, CRYPTO, 9, 1) 130 FIELD(CPUCFG2, LVZ, 10, 1) 131 FIELD(CPUCFG2, LVZ_VER, 11, 3) 132 FIELD(CPUCFG2, LLFTP, 14, 1) 133 FIELD(CPUCFG2, LLFTP_VER, 15, 3) 134 FIELD(CPUCFG2, LBT_X86, 18, 1) 135 FIELD(CPUCFG2, LBT_ARM, 19, 1) 136 FIELD(CPUCFG2, LBT_MIPS, 20, 1) 137 FIELD(CPUCFG2, LBT_ALL, 18, 3) 138 FIELD(CPUCFG2, LSPW, 21, 1) 139 FIELD(CPUCFG2, LAM, 22, 1) 140 FIELD(CPUCFG2, HPTW, 24, 1) 141 142 /* cpucfg[3] bits */ 143 FIELD(CPUCFG3, CCDMA, 0, 1) 144 FIELD(CPUCFG3, SFB, 1, 1) 145 FIELD(CPUCFG3, UCACC, 2, 1) 146 FIELD(CPUCFG3, LLEXC, 3, 1) 147 FIELD(CPUCFG3, SCDLY, 4, 1) 148 FIELD(CPUCFG3, LLDBAR, 5, 1) 149 FIELD(CPUCFG3, ITLBHMC, 6, 1) 150 FIELD(CPUCFG3, ICHMC, 7, 1) 151 FIELD(CPUCFG3, SPW_LVL, 8, 3) 152 FIELD(CPUCFG3, SPW_HP_HF, 11, 1) 153 FIELD(CPUCFG3, RVA, 12, 1) 154 FIELD(CPUCFG3, RVAMAX, 13, 4) 155 156 /* cpucfg[4] bits */ 157 FIELD(CPUCFG4, CC_FREQ, 0, 32) 158 159 /* cpucfg[5] bits */ 160 FIELD(CPUCFG5, CC_MUL, 0, 16) 161 FIELD(CPUCFG5, CC_DIV, 16, 16) 162 163 /* cpucfg[6] bits */ 164 FIELD(CPUCFG6, PMP, 0, 1) 165 FIELD(CPUCFG6, PMVER, 1, 3) 166 FIELD(CPUCFG6, PMNUM, 4, 4) 167 FIELD(CPUCFG6, PMBITS, 8, 6) 168 FIELD(CPUCFG6, UPM, 14, 1) 169 170 /* cpucfg[16] bits */ 171 FIELD(CPUCFG16, L1_IUPRE, 0, 1) 172 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) 173 FIELD(CPUCFG16, L1_DPRE, 2, 1) 174 FIELD(CPUCFG16, L2_IUPRE, 3, 1) 175 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) 176 FIELD(CPUCFG16, L2_IUPRIV, 5, 1) 177 FIELD(CPUCFG16, L2_IUINCL, 6, 1) 178 FIELD(CPUCFG16, L2_DPRE, 7, 1) 179 FIELD(CPUCFG16, L2_DPRIV, 8, 1) 180 FIELD(CPUCFG16, L2_DINCL, 9, 1) 181 FIELD(CPUCFG16, L3_IUPRE, 10, 1) 182 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) 183 FIELD(CPUCFG16, L3_IUPRIV, 12, 1) 184 FIELD(CPUCFG16, L3_IUINCL, 13, 1) 185 FIELD(CPUCFG16, L3_DPRE, 14, 1) 186 FIELD(CPUCFG16, L3_DPRIV, 15, 1) 187 FIELD(CPUCFG16, L3_DINCL, 16, 1) 188 189 /* cpucfg[17] bits */ 190 FIELD(CPUCFG17, L1IU_WAYS, 0, 16) 191 FIELD(CPUCFG17, L1IU_SETS, 16, 8) 192 FIELD(CPUCFG17, L1IU_SIZE, 24, 7) 193 194 /* cpucfg[18] bits */ 195 FIELD(CPUCFG18, L1D_WAYS, 0, 16) 196 FIELD(CPUCFG18, L1D_SETS, 16, 8) 197 FIELD(CPUCFG18, L1D_SIZE, 24, 7) 198 199 /* cpucfg[19] bits */ 200 FIELD(CPUCFG19, L2IU_WAYS, 0, 16) 201 FIELD(CPUCFG19, L2IU_SETS, 16, 8) 202 FIELD(CPUCFG19, L2IU_SIZE, 24, 7) 203 204 /* cpucfg[20] bits */ 205 FIELD(CPUCFG20, L3IU_WAYS, 0, 16) 206 FIELD(CPUCFG20, L3IU_SETS, 16, 8) 207 FIELD(CPUCFG20, L3IU_SIZE, 24, 7) 208 209 /*CSR_CRMD */ 210 FIELD(CSR_CRMD, PLV, 0, 2) 211 FIELD(CSR_CRMD, IE, 2, 1) 212 FIELD(CSR_CRMD, DA, 3, 1) 213 FIELD(CSR_CRMD, PG, 4, 1) 214 FIELD(CSR_CRMD, DATF, 5, 2) 215 FIELD(CSR_CRMD, DATM, 7, 2) 216 FIELD(CSR_CRMD, WE, 9, 1) 217 218 extern const char * const regnames[32]; 219 extern const char * const fregnames[32]; 220 221 #define N_IRQS 15 222 #define IRQ_TIMER 11 223 #define IRQ_IPI 12 224 #define INT_DMSI 14 225 226 #define LOONGARCH_STLB 2048 /* 2048 STLB */ 227 #define LOONGARCH_MTLB 64 /* 64 MTLB */ 228 #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) 229 230 /* 231 * define the ASID PS E VPPN field of TLB 232 */ 233 FIELD(TLB_MISC, E, 0, 1) 234 FIELD(TLB_MISC, ASID, 1, 10) 235 FIELD(TLB_MISC, VPPN, 13, 35) 236 FIELD(TLB_MISC, PS, 48, 6) 237 238 /*Msg interrupt registers */ 239 #define N_MSGIS 4 240 FIELD(CSR_MSGIS, IS, 0, 63) 241 FIELD(CSR_MSGIR, INTNUM, 0, 8) 242 FIELD(CSR_MSGIR, ACTIVE, 31, 1) 243 FIELD(CSR_MSGIE, PT, 0, 8) 244 245 #define LSX_LEN (128) 246 #define LASX_LEN (256) 247 248 typedef union VReg { 249 int8_t B[LASX_LEN / 8]; 250 int16_t H[LASX_LEN / 16]; 251 int32_t W[LASX_LEN / 32]; 252 int64_t D[LASX_LEN / 64]; 253 uint8_t UB[LASX_LEN / 8]; 254 uint16_t UH[LASX_LEN / 16]; 255 uint32_t UW[LASX_LEN / 32]; 256 uint64_t UD[LASX_LEN / 64]; 257 Int128 Q[LASX_LEN / 128]; 258 } VReg; 259 260 typedef union fpr_t fpr_t; 261 union fpr_t { 262 VReg vreg; 263 }; 264 265 #ifdef CONFIG_TCG 266 struct LoongArchTLB { 267 uint64_t tlb_misc; 268 /* Fields corresponding to CSR_TLBELO0/1 */ 269 uint64_t tlb_entry0; 270 uint64_t tlb_entry1; 271 }; 272 typedef struct LoongArchTLB LoongArchTLB; 273 #endif 274 275 enum loongarch_features { 276 LOONGARCH_FEATURE_LSX, 277 LOONGARCH_FEATURE_LASX, 278 LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ 279 LOONGARCH_FEATURE_PMU, 280 LOONGARCH_FEATURE_PV_IPI, 281 LOONGARCH_FEATURE_STEALTIME, 282 LOONGARCH_FEATURE_PTW, 283 }; 284 285 typedef struct LoongArchBT { 286 /* scratch registers */ 287 uint64_t scr0; 288 uint64_t scr1; 289 uint64_t scr2; 290 uint64_t scr3; 291 /* loongarch eflags */ 292 uint32_t eflags; 293 uint32_t ftop; 294 } lbt_t; 295 296 typedef struct CPUArchState { 297 uint64_t gpr[32]; 298 uint64_t pc; 299 300 fpr_t fpr[32]; 301 bool cf[8]; 302 uint32_t fcsr0; 303 lbt_t lbt; 304 305 uint32_t cpucfg[21]; 306 uint32_t pv_features; 307 308 /* LoongArch CSRs */ 309 uint64_t CSR_CRMD; 310 uint64_t CSR_PRMD; 311 uint64_t CSR_EUEN; 312 uint64_t CSR_MISC; 313 uint64_t CSR_ECFG; 314 uint64_t CSR_ESTAT; 315 uint64_t CSR_ERA; 316 uint64_t CSR_BADV; 317 uint64_t CSR_BADI; 318 uint64_t CSR_EENTRY; 319 uint64_t CSR_TLBIDX; 320 uint64_t CSR_TLBEHI; 321 uint64_t CSR_TLBELO0; 322 uint64_t CSR_TLBELO1; 323 uint64_t CSR_ASID; 324 uint64_t CSR_PGDL; 325 uint64_t CSR_PGDH; 326 uint64_t CSR_PGD; 327 uint64_t CSR_PWCL; 328 uint64_t CSR_PWCH; 329 uint64_t CSR_STLBPS; 330 uint64_t CSR_RVACFG; 331 uint64_t CSR_CPUID; 332 uint64_t CSR_PRCFG1; 333 uint64_t CSR_PRCFG2; 334 uint64_t CSR_PRCFG3; 335 uint64_t CSR_SAVE[16]; 336 uint64_t CSR_TID; 337 uint64_t CSR_TCFG; 338 uint64_t CSR_TVAL; 339 uint64_t CSR_CNTC; 340 uint64_t CSR_TICLR; 341 uint64_t CSR_LLBCTL; 342 uint64_t CSR_IMPCTL1; 343 uint64_t CSR_IMPCTL2; 344 uint64_t CSR_TLBRENTRY; 345 uint64_t CSR_TLBRBADV; 346 uint64_t CSR_TLBRERA; 347 uint64_t CSR_TLBRSAVE; 348 uint64_t CSR_TLBRELO0; 349 uint64_t CSR_TLBRELO1; 350 uint64_t CSR_TLBREHI; 351 uint64_t CSR_TLBRPRMD; 352 uint64_t CSR_MERRCTL; 353 uint64_t CSR_MERRINFO1; 354 uint64_t CSR_MERRINFO2; 355 uint64_t CSR_MERRENTRY; 356 uint64_t CSR_MERRERA; 357 uint64_t CSR_MERRSAVE; 358 uint64_t CSR_CTAG; 359 uint64_t CSR_DMW[4]; 360 uint64_t CSR_DBG; 361 uint64_t CSR_DERA; 362 uint64_t CSR_DSAVE; 363 /* Msg interrupt registers */ 364 uint64_t CSR_MSGIS[N_MSGIS]; 365 uint64_t CSR_MSGIR; 366 uint64_t CSR_MSGIE; 367 struct { 368 uint64_t guest_addr; 369 } stealtime; 370 371 #ifdef CONFIG_TCG 372 float_status fp_status; 373 uint32_t fcsr0_mask; 374 uint64_t lladdr; /* LL virtual address compared against SC */ 375 uint64_t llval; 376 #endif 377 #ifndef CONFIG_USER_ONLY 378 #ifdef CONFIG_TCG 379 LoongArchTLB tlb[LOONGARCH_TLB_MAX]; 380 #endif 381 382 AddressSpace *address_space_iocsr; 383 uint32_t mp_state; 384 #endif 385 } CPULoongArchState; 386 387 typedef struct LoongArchCPUTopo { 388 int32_t socket_id; /* socket-id of this VCPU */ 389 int32_t core_id; /* core-id of this VCPU */ 390 int32_t thread_id; /* thread-id of this VCPU */ 391 } LoongArchCPUTopo; 392 393 /** 394 * LoongArchCPU: 395 * @env: #CPULoongArchState 396 * 397 * A LoongArch CPU. 398 */ 399 struct ArchCPU { 400 CPUState parent_obj; 401 402 CPULoongArchState env; 403 QEMUTimer timer; 404 uint32_t phy_id; 405 OnOffAuto lbt; 406 OnOffAuto pmu; 407 OnOffAuto ptw; 408 OnOffAuto lsx; 409 OnOffAuto lasx; 410 OnOffAuto msgint; 411 OnOffAuto kvm_pv_ipi; 412 OnOffAuto kvm_steal_time; 413 int32_t socket_id; /* socket-id of this CPU */ 414 int32_t core_id; /* core-id of this CPU */ 415 int32_t thread_id; /* thread-id of this CPU */ 416 int32_t node_id; /* NUMA node of this CPU */ 417 418 /* 'compatible' string for this CPU for Linux device trees */ 419 const char *dtb_compatible; 420 /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */ 421 uint64_t kvm_state_counter; 422 VMChangeStateEntry *vmsentry; 423 }; 424 425 /** 426 * LoongArchCPUClass: 427 * @parent_realize: The parent class' realize handler. 428 * @parent_phases: The parent class' reset phase handlers. 429 * 430 * A LoongArch CPU model. 431 */ 432 struct LoongArchCPUClass { 433 CPUClass parent_class; 434 435 DeviceRealize parent_realize; 436 DeviceUnrealize parent_unrealize; 437 ResettablePhases parent_phases; 438 }; 439 440 /* 441 * LoongArch CPUs has 4 privilege levels. 442 * 0 for kernel mode, 3 for user mode. 443 * Define an extra index for DA(direct addressing) mode. 444 */ 445 #define MMU_PLV_KERNEL 0 446 #define MMU_PLV_USER 3 447 #define MMU_KERNEL_IDX MMU_PLV_KERNEL 448 #define MMU_USER_IDX MMU_PLV_USER 449 #define MMU_DA_IDX 4 450 451 static inline bool is_la64(CPULoongArchState *env) 452 { 453 return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; 454 } 455 456 static inline bool is_va32(CPULoongArchState *env) 457 { 458 /* VA32 if !LA64 or VA32L[1-3] */ 459 bool va32 = !is_la64(env); 460 uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); 461 if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { 462 va32 = true; 463 } 464 return va32; 465 } 466 467 static inline void set_pc(CPULoongArchState *env, uint64_t value) 468 { 469 if (is_va32(env)) { 470 env->pc = (uint32_t)value; 471 } else { 472 env->pc = value; 473 } 474 } 475 476 /* 477 * LoongArch CPUs hardware flags. 478 */ 479 #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ 480 #define HW_FLAGS_EUEN_FPE 0x04 481 #define HW_FLAGS_EUEN_SXE 0x08 482 #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ 483 #define HW_FLAGS_VA32 0x20 484 #define HW_FLAGS_EUEN_ASXE 0x40 485 486 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU 487 488 #endif /* LOONGARCH_CPU_H */ 489