1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2018 Microchip Technology Inc. */
3 
4 #ifndef _LAN743X_ETHTOOL_H
5 #define _LAN743X_ETHTOOL_H
6 
7 #include "linux/ethtool.h"
8 
9 #define LAN743X_ETH_REG_VERSION         1
10 
11 enum {
12 	ETH_PRIV_FLAGS,
13 	ETH_ID_REV,
14 	ETH_FPGA_REV,
15 	ETH_STRAP_READ,
16 	ETH_INT_STS,
17 	ETH_HW_CFG,
18 	ETH_PMT_CTL,
19 	ETH_E2P_CMD,
20 	ETH_E2P_DATA,
21 	ETH_MAC_CR,
22 	ETH_MAC_RX,
23 	ETH_MAC_TX,
24 	ETH_FLOW,
25 	ETH_MII_ACC,
26 	ETH_MII_DATA,
27 	ETH_EEE_TX_LPI_REQ_DLY,
28 	ETH_WUCSR,
29 	ETH_WK_SRC,
30 
31 	/* Add new registers above */
32 	MAX_LAN743X_ETH_COMMON_REGS
33 };
34 
35 enum {
36 	/* SGMII Register */
37 	ETH_SR_VSMMD_DEV_ID1,
38 	ETH_SR_VSMMD_DEV_ID2,
39 	ETH_SR_VSMMD_PCS_ID1,
40 	ETH_SR_VSMMD_PCS_ID2,
41 	ETH_SR_VSMMD_STS,
42 	ETH_SR_VSMMD_CTRL,
43 	ETH_SR_MII_CTRL,
44 	ETH_SR_MII_STS,
45 	ETH_SR_MII_DEV_ID1,
46 	ETH_SR_MII_DEV_ID2,
47 	ETH_SR_MII_AN_ADV,
48 	ETH_SR_MII_LP_BABL,
49 	ETH_SR_MII_EXPN,
50 	ETH_SR_MII_EXT_STS,
51 	ETH_SR_MII_TIME_SYNC_ABL,
52 	ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,
53 	ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,
54 	ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,
55 	ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,
56 	ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,
57 	ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,
58 	ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,
59 	ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,
60 	ETH_VR_MII_DIG_CTRL1,
61 	ETH_VR_MII_AN_CTRL,
62 	ETH_VR_MII_AN_INTR_STS,
63 	ETH_VR_MII_TC,
64 	ETH_VR_MII_DBG_CTRL,
65 	ETH_VR_MII_EEE_MCTRL0,
66 	ETH_VR_MII_EEE_TXTIMER,
67 	ETH_VR_MII_EEE_RXTIMER,
68 	ETH_VR_MII_LINK_TIMER_CTRL,
69 	ETH_VR_MII_EEE_MCTRL1,
70 	ETH_VR_MII_DIG_STS,
71 	ETH_VR_MII_ICG_ERRCNT1,
72 	ETH_VR_MII_GPIO,
73 	ETH_VR_MII_EEE_LPI_STATUS,
74 	ETH_VR_MII_EEE_WKERR,
75 	ETH_VR_MII_MISC_STS,
76 	ETH_VR_MII_RX_LSTS,
77 	ETH_VR_MII_GEN2_GEN4_TX_BSTCTRL0,
78 	ETH_VR_MII_GEN2_GEN4_TX_LVLCTRL0,
79 	ETH_VR_MII_GEN2_GEN4_TXGENCTRL0,
80 	ETH_VR_MII_GEN2_GEN4_TXGENCTRL1,
81 	ETH_VR_MII_GEN4_TXGENCTRL2,
82 	ETH_VR_MII_GEN2_GEN4_TX_STS,
83 	ETH_VR_MII_GEN2_GEN4_RXGENCTRL0,
84 	ETH_VR_MII_GEN2_GEN4_RXGENCTRL1,
85 	ETH_VR_MII_GEN4_RXEQ_CTRL,
86 	ETH_VR_MII_GEN4_RXLOS_CTRL0,
87 	ETH_VR_MII_GEN2_GEN4_MPLL_CTRL0,
88 	ETH_VR_MII_GEN2_GEN4_MPLL_CTRL1,
89 	ETH_VR_MII_GEN2_GEN4_MPLL_STS,
90 	ETH_VR_MII_GEN2_GEN4_LVL_CTRL,
91 	ETH_VR_MII_GEN4_MISC_CTRL2,
92 	ETH_VR_MII_GEN2_GEN4_MISC_CTRL0,
93 	ETH_VR_MII_GEN2_GEN4_MISC_CTRL1,
94 	ETH_VR_MII_SNPS_CR_CTRL,
95 	ETH_VR_MII_SNPS_CR_ADDR,
96 	ETH_VR_MII_SNPS_CR_DATA,
97 	ETH_VR_MII_DIG_CTRL2,
98 	ETH_VR_MII_DIG_ERRCNT,
99 
100 	/* Add new registers above */
101 	MAX_LAN743X_ETH_SGMII_REGS
102 };
103 
104 extern const struct ethtool_ops lan743x_ethtool_ops;
105 
106 #endif /* _LAN743X_ETHTOOL_H */
107