xref: /openbmc/linux/arch/arm64/kvm/vgic/vgic-its.c (revision 3f70ed98)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GICv3 ITS emulation
4  *
5  * Copyright (C) 2015,2016 ARM Ltd.
6  * Author: Andre Przywara <andre.przywara@arm.com>
7  */
8 
9 #include <linux/cpu.h>
10 #include <linux/kvm.h>
11 #include <linux/kvm_host.h>
12 #include <linux/interrupt.h>
13 #include <linux/list.h>
14 #include <linux/uaccess.h>
15 #include <linux/list_sort.h>
16 
17 #include <linux/irqchip/arm-gic-v3.h>
18 
19 #include <asm/kvm_emulate.h>
20 #include <asm/kvm_arm.h>
21 #include <asm/kvm_mmu.h>
22 
23 #include "vgic.h"
24 #include "vgic-mmio.h"
25 
26 static int vgic_its_save_tables_v0(struct vgic_its *its);
27 static int vgic_its_restore_tables_v0(struct vgic_its *its);
28 static int vgic_its_commit_v0(struct vgic_its *its);
29 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
30 			     struct kvm_vcpu *filter_vcpu, bool needs_inv);
31 
32 /*
33  * Creates a new (reference to a) struct vgic_irq for a given LPI.
34  * If this LPI is already mapped on another ITS, we increase its refcount
35  * and return a pointer to the existing structure.
36  * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
37  * This function returns a pointer to the _unlocked_ structure.
38  */
vgic_add_lpi(struct kvm * kvm,u32 intid,struct kvm_vcpu * vcpu)39 static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
40 				     struct kvm_vcpu *vcpu)
41 {
42 	struct vgic_dist *dist = &kvm->arch.vgic;
43 	struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
44 	unsigned long flags;
45 	int ret;
46 
47 	/* In this case there is no put, since we keep the reference. */
48 	if (irq)
49 		return irq;
50 
51 	irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL_ACCOUNT);
52 	if (!irq)
53 		return ERR_PTR(-ENOMEM);
54 
55 	INIT_LIST_HEAD(&irq->lpi_list);
56 	INIT_LIST_HEAD(&irq->ap_list);
57 	raw_spin_lock_init(&irq->irq_lock);
58 
59 	irq->config = VGIC_CONFIG_EDGE;
60 	kref_init(&irq->refcount);
61 	irq->intid = intid;
62 	irq->target_vcpu = vcpu;
63 	irq->group = 1;
64 
65 	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
66 
67 	/*
68 	 * There could be a race with another vgic_add_lpi(), so we need to
69 	 * check that we don't add a second list entry with the same LPI.
70 	 */
71 	list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) {
72 		if (oldirq->intid != intid)
73 			continue;
74 
75 		/* Someone was faster with adding this LPI, lets use that. */
76 		kfree(irq);
77 		irq = oldirq;
78 
79 		/*
80 		 * This increases the refcount, the caller is expected to
81 		 * call vgic_put_irq() on the returned pointer once it's
82 		 * finished with the IRQ.
83 		 */
84 		vgic_get_irq_kref(irq);
85 
86 		goto out_unlock;
87 	}
88 
89 	list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
90 	dist->lpi_list_count++;
91 
92 out_unlock:
93 	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
94 
95 	/*
96 	 * We "cache" the configuration table entries in our struct vgic_irq's.
97 	 * However we only have those structs for mapped IRQs, so we read in
98 	 * the respective config data from memory here upon mapping the LPI.
99 	 *
100 	 * Should any of these fail, behave as if we couldn't create the LPI
101 	 * by dropping the refcount and returning the error.
102 	 */
103 	ret = update_lpi_config(kvm, irq, NULL, false);
104 	if (ret) {
105 		vgic_put_irq(kvm, irq);
106 		return ERR_PTR(ret);
107 	}
108 
109 	ret = vgic_v3_lpi_sync_pending_status(kvm, irq);
110 	if (ret) {
111 		vgic_put_irq(kvm, irq);
112 		return ERR_PTR(ret);
113 	}
114 
115 	return irq;
116 }
117 
118 struct its_device {
119 	struct list_head dev_list;
120 
121 	/* the head for the list of ITTEs */
122 	struct list_head itt_head;
123 	u32 num_eventid_bits;
124 	gpa_t itt_addr;
125 	u32 device_id;
126 };
127 
128 #define COLLECTION_NOT_MAPPED ((u32)~0)
129 
130 struct its_collection {
131 	struct list_head coll_list;
132 
133 	u32 collection_id;
134 	u32 target_addr;
135 };
136 
137 #define its_is_collection_mapped(coll) ((coll) && \
138 				((coll)->target_addr != COLLECTION_NOT_MAPPED))
139 
140 struct its_ite {
141 	struct list_head ite_list;
142 
143 	struct vgic_irq *irq;
144 	struct its_collection *collection;
145 	u32 event_id;
146 };
147 
148 struct vgic_translation_cache_entry {
149 	struct list_head	entry;
150 	phys_addr_t		db;
151 	u32			devid;
152 	u32			eventid;
153 	struct vgic_irq		*irq;
154 };
155 
156 /**
157  * struct vgic_its_abi - ITS abi ops and settings
158  * @cte_esz: collection table entry size
159  * @dte_esz: device table entry size
160  * @ite_esz: interrupt translation table entry size
161  * @save tables: save the ITS tables into guest RAM
162  * @restore_tables: restore the ITS internal structs from tables
163  *  stored in guest RAM
164  * @commit: initialize the registers which expose the ABI settings,
165  *  especially the entry sizes
166  */
167 struct vgic_its_abi {
168 	int cte_esz;
169 	int dte_esz;
170 	int ite_esz;
171 	int (*save_tables)(struct vgic_its *its);
172 	int (*restore_tables)(struct vgic_its *its);
173 	int (*commit)(struct vgic_its *its);
174 };
175 
176 #define ABI_0_ESZ	8
177 #define ESZ_MAX		ABI_0_ESZ
178 
179 static const struct vgic_its_abi its_table_abi_versions[] = {
180 	[0] = {
181 	 .cte_esz = ABI_0_ESZ,
182 	 .dte_esz = ABI_0_ESZ,
183 	 .ite_esz = ABI_0_ESZ,
184 	 .save_tables = vgic_its_save_tables_v0,
185 	 .restore_tables = vgic_its_restore_tables_v0,
186 	 .commit = vgic_its_commit_v0,
187 	},
188 };
189 
190 #define NR_ITS_ABIS	ARRAY_SIZE(its_table_abi_versions)
191 
vgic_its_get_abi(struct vgic_its * its)192 inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
193 {
194 	return &its_table_abi_versions[its->abi_rev];
195 }
196 
vgic_its_set_abi(struct vgic_its * its,u32 rev)197 static int vgic_its_set_abi(struct vgic_its *its, u32 rev)
198 {
199 	const struct vgic_its_abi *abi;
200 
201 	its->abi_rev = rev;
202 	abi = vgic_its_get_abi(its);
203 	return abi->commit(its);
204 }
205 
206 /*
207  * Find and returns a device in the device table for an ITS.
208  * Must be called with the its_lock mutex held.
209  */
find_its_device(struct vgic_its * its,u32 device_id)210 static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
211 {
212 	struct its_device *device;
213 
214 	list_for_each_entry(device, &its->device_list, dev_list)
215 		if (device_id == device->device_id)
216 			return device;
217 
218 	return NULL;
219 }
220 
221 /*
222  * Find and returns an interrupt translation table entry (ITTE) for a given
223  * Device ID/Event ID pair on an ITS.
224  * Must be called with the its_lock mutex held.
225  */
find_ite(struct vgic_its * its,u32 device_id,u32 event_id)226 static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
227 				  u32 event_id)
228 {
229 	struct its_device *device;
230 	struct its_ite *ite;
231 
232 	device = find_its_device(its, device_id);
233 	if (device == NULL)
234 		return NULL;
235 
236 	list_for_each_entry(ite, &device->itt_head, ite_list)
237 		if (ite->event_id == event_id)
238 			return ite;
239 
240 	return NULL;
241 }
242 
243 /* To be used as an iterator this macro misses the enclosing parentheses */
244 #define for_each_lpi_its(dev, ite, its) \
245 	list_for_each_entry(dev, &(its)->device_list, dev_list) \
246 		list_for_each_entry(ite, &(dev)->itt_head, ite_list)
247 
248 #define GIC_LPI_OFFSET 8192
249 
250 #define VITS_TYPER_IDBITS 16
251 #define VITS_TYPER_DEVBITS 16
252 #define VITS_DTE_MAX_DEVID_OFFSET	(BIT(14) - 1)
253 #define VITS_ITE_MAX_EVENTID_OFFSET	(BIT(16) - 1)
254 
255 /*
256  * Finds and returns a collection in the ITS collection table.
257  * Must be called with the its_lock mutex held.
258  */
find_collection(struct vgic_its * its,int coll_id)259 static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
260 {
261 	struct its_collection *collection;
262 
263 	list_for_each_entry(collection, &its->collection_list, coll_list) {
264 		if (coll_id == collection->collection_id)
265 			return collection;
266 	}
267 
268 	return NULL;
269 }
270 
271 #define LPI_PROP_ENABLE_BIT(p)	((p) & LPI_PROP_ENABLED)
272 #define LPI_PROP_PRIORITY(p)	((p) & 0xfc)
273 
274 /*
275  * Reads the configuration data for a given LPI from guest memory and
276  * updates the fields in struct vgic_irq.
277  * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
278  * VCPU. Unconditionally applies if filter_vcpu is NULL.
279  */
update_lpi_config(struct kvm * kvm,struct vgic_irq * irq,struct kvm_vcpu * filter_vcpu,bool needs_inv)280 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
281 			     struct kvm_vcpu *filter_vcpu, bool needs_inv)
282 {
283 	u64 propbase = GICR_PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
284 	u8 prop;
285 	int ret;
286 	unsigned long flags;
287 
288 	ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
289 				  &prop, 1);
290 
291 	if (ret)
292 		return ret;
293 
294 	raw_spin_lock_irqsave(&irq->irq_lock, flags);
295 
296 	if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
297 		irq->priority = LPI_PROP_PRIORITY(prop);
298 		irq->enabled = LPI_PROP_ENABLE_BIT(prop);
299 
300 		if (!irq->hw) {
301 			vgic_queue_irq_unlock(kvm, irq, flags);
302 			return 0;
303 		}
304 	}
305 
306 	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
307 
308 	if (irq->hw)
309 		return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
310 
311 	return 0;
312 }
313 
314 /*
315  * Create a snapshot of the current LPIs targeting @vcpu, so that we can
316  * enumerate those LPIs without holding any lock.
317  * Returns their number and puts the kmalloc'ed array into intid_ptr.
318  */
vgic_copy_lpi_list(struct kvm * kvm,struct kvm_vcpu * vcpu,u32 ** intid_ptr)319 int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr)
320 {
321 	struct vgic_dist *dist = &kvm->arch.vgic;
322 	struct vgic_irq *irq;
323 	unsigned long flags;
324 	u32 *intids;
325 	int irq_count, i = 0;
326 
327 	/*
328 	 * There is an obvious race between allocating the array and LPIs
329 	 * being mapped/unmapped. If we ended up here as a result of a
330 	 * command, we're safe (locks are held, preventing another
331 	 * command). If coming from another path (such as enabling LPIs),
332 	 * we must be careful not to overrun the array.
333 	 */
334 	irq_count = READ_ONCE(dist->lpi_list_count);
335 	intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL_ACCOUNT);
336 	if (!intids)
337 		return -ENOMEM;
338 
339 	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
340 	list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
341 		if (i == irq_count)
342 			break;
343 		/* We don't need to "get" the IRQ, as we hold the list lock. */
344 		if (vcpu && irq->target_vcpu != vcpu)
345 			continue;
346 		intids[i++] = irq->intid;
347 	}
348 	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
349 
350 	*intid_ptr = intids;
351 	return i;
352 }
353 
update_affinity(struct vgic_irq * irq,struct kvm_vcpu * vcpu)354 static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu)
355 {
356 	int ret = 0;
357 	unsigned long flags;
358 
359 	raw_spin_lock_irqsave(&irq->irq_lock, flags);
360 	irq->target_vcpu = vcpu;
361 	raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
362 
363 	if (irq->hw) {
364 		struct its_vlpi_map map;
365 
366 		ret = its_get_vlpi(irq->host_irq, &map);
367 		if (ret)
368 			return ret;
369 
370 		if (map.vpe)
371 			atomic_dec(&map.vpe->vlpi_count);
372 		map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
373 		atomic_inc(&map.vpe->vlpi_count);
374 
375 		ret = its_map_vlpi(irq->host_irq, &map);
376 	}
377 
378 	return ret;
379 }
380 
381 /*
382  * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
383  * is targeting) to the VGIC's view, which deals with target VCPUs.
384  * Needs to be called whenever either the collection for a LPIs has
385  * changed or the collection itself got retargeted.
386  */
update_affinity_ite(struct kvm * kvm,struct its_ite * ite)387 static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
388 {
389 	struct kvm_vcpu *vcpu;
390 
391 	if (!its_is_collection_mapped(ite->collection))
392 		return;
393 
394 	vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
395 	update_affinity(ite->irq, vcpu);
396 }
397 
398 /*
399  * Updates the target VCPU for every LPI targeting this collection.
400  * Must be called with the its_lock mutex held.
401  */
update_affinity_collection(struct kvm * kvm,struct vgic_its * its,struct its_collection * coll)402 static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
403 				       struct its_collection *coll)
404 {
405 	struct its_device *device;
406 	struct its_ite *ite;
407 
408 	for_each_lpi_its(device, ite, its) {
409 		if (ite->collection != coll)
410 			continue;
411 
412 		update_affinity_ite(kvm, ite);
413 	}
414 }
415 
max_lpis_propbaser(u64 propbaser)416 static u32 max_lpis_propbaser(u64 propbaser)
417 {
418 	int nr_idbits = (propbaser & 0x1f) + 1;
419 
420 	return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
421 }
422 
423 /*
424  * Sync the pending table pending bit of LPIs targeting @vcpu
425  * with our own data structures. This relies on the LPI being
426  * mapped before.
427  */
its_sync_lpi_pending_table(struct kvm_vcpu * vcpu)428 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
429 {
430 	gpa_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
431 	struct vgic_irq *irq;
432 	int last_byte_offset = -1;
433 	int ret = 0;
434 	u32 *intids;
435 	int nr_irqs, i;
436 	unsigned long flags;
437 	u8 pendmask;
438 
439 	nr_irqs = vgic_copy_lpi_list(vcpu->kvm, vcpu, &intids);
440 	if (nr_irqs < 0)
441 		return nr_irqs;
442 
443 	for (i = 0; i < nr_irqs; i++) {
444 		int byte_offset, bit_nr;
445 
446 		byte_offset = intids[i] / BITS_PER_BYTE;
447 		bit_nr = intids[i] % BITS_PER_BYTE;
448 
449 		/*
450 		 * For contiguously allocated LPIs chances are we just read
451 		 * this very same byte in the last iteration. Reuse that.
452 		 */
453 		if (byte_offset != last_byte_offset) {
454 			ret = kvm_read_guest_lock(vcpu->kvm,
455 						  pendbase + byte_offset,
456 						  &pendmask, 1);
457 			if (ret) {
458 				kfree(intids);
459 				return ret;
460 			}
461 			last_byte_offset = byte_offset;
462 		}
463 
464 		irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
465 		if (!irq)
466 			continue;
467 
468 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
469 		irq->pending_latch = pendmask & (1U << bit_nr);
470 		vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
471 		vgic_put_irq(vcpu->kvm, irq);
472 	}
473 
474 	kfree(intids);
475 
476 	return ret;
477 }
478 
vgic_mmio_read_its_typer(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)479 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
480 					      struct vgic_its *its,
481 					      gpa_t addr, unsigned int len)
482 {
483 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
484 	u64 reg = GITS_TYPER_PLPIS;
485 
486 	/*
487 	 * We use linear CPU numbers for redistributor addressing,
488 	 * so GITS_TYPER.PTA is 0.
489 	 * Also we force all PROPBASER registers to be the same, so
490 	 * CommonLPIAff is 0 as well.
491 	 * To avoid memory waste in the guest, we keep the number of IDBits and
492 	 * DevBits low - as least for the time being.
493 	 */
494 	reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
495 	reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
496 	reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
497 
498 	return extract_bytes(reg, addr & 7, len);
499 }
500 
vgic_mmio_read_its_iidr(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)501 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
502 					     struct vgic_its *its,
503 					     gpa_t addr, unsigned int len)
504 {
505 	u32 val;
506 
507 	val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
508 	val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
509 	return val;
510 }
511 
vgic_mmio_uaccess_write_its_iidr(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)512 static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
513 					    struct vgic_its *its,
514 					    gpa_t addr, unsigned int len,
515 					    unsigned long val)
516 {
517 	u32 rev = GITS_IIDR_REV(val);
518 
519 	if (rev >= NR_ITS_ABIS)
520 		return -EINVAL;
521 	return vgic_its_set_abi(its, rev);
522 }
523 
vgic_mmio_read_its_idregs(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)524 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
525 					       struct vgic_its *its,
526 					       gpa_t addr, unsigned int len)
527 {
528 	switch (addr & 0xffff) {
529 	case GITS_PIDR0:
530 		return 0x92;	/* part number, bits[7:0] */
531 	case GITS_PIDR1:
532 		return 0xb4;	/* part number, bits[11:8] */
533 	case GITS_PIDR2:
534 		return GIC_PIDR2_ARCH_GICv3 | 0x0b;
535 	case GITS_PIDR4:
536 		return 0x40;	/* This is a 64K software visible page */
537 	/* The following are the ID registers for (any) GIC. */
538 	case GITS_CIDR0:
539 		return 0x0d;
540 	case GITS_CIDR1:
541 		return 0xf0;
542 	case GITS_CIDR2:
543 		return 0x05;
544 	case GITS_CIDR3:
545 		return 0xb1;
546 	}
547 
548 	return 0;
549 }
550 
__vgic_its_check_cache(struct vgic_dist * dist,phys_addr_t db,u32 devid,u32 eventid)551 static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist,
552 					       phys_addr_t db,
553 					       u32 devid, u32 eventid)
554 {
555 	struct vgic_translation_cache_entry *cte;
556 
557 	list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
558 		/*
559 		 * If we hit a NULL entry, there is nothing after this
560 		 * point.
561 		 */
562 		if (!cte->irq)
563 			break;
564 
565 		if (cte->db != db || cte->devid != devid ||
566 		    cte->eventid != eventid)
567 			continue;
568 
569 		/*
570 		 * Move this entry to the head, as it is the most
571 		 * recently used.
572 		 */
573 		if (!list_is_first(&cte->entry, &dist->lpi_translation_cache))
574 			list_move(&cte->entry, &dist->lpi_translation_cache);
575 
576 		return cte->irq;
577 	}
578 
579 	return NULL;
580 }
581 
vgic_its_check_cache(struct kvm * kvm,phys_addr_t db,u32 devid,u32 eventid)582 static struct vgic_irq *vgic_its_check_cache(struct kvm *kvm, phys_addr_t db,
583 					     u32 devid, u32 eventid)
584 {
585 	struct vgic_dist *dist = &kvm->arch.vgic;
586 	struct vgic_irq *irq;
587 	unsigned long flags;
588 
589 	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
590 
591 	irq = __vgic_its_check_cache(dist, db, devid, eventid);
592 	if (irq)
593 		vgic_get_irq_kref(irq);
594 
595 	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
596 
597 	return irq;
598 }
599 
vgic_its_cache_translation(struct kvm * kvm,struct vgic_its * its,u32 devid,u32 eventid,struct vgic_irq * irq)600 static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its,
601 				       u32 devid, u32 eventid,
602 				       struct vgic_irq *irq)
603 {
604 	struct vgic_dist *dist = &kvm->arch.vgic;
605 	struct vgic_translation_cache_entry *cte;
606 	unsigned long flags;
607 	phys_addr_t db;
608 
609 	/* Do not cache a directly injected interrupt */
610 	if (irq->hw)
611 		return;
612 
613 	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
614 
615 	if (unlikely(list_empty(&dist->lpi_translation_cache)))
616 		goto out;
617 
618 	/*
619 	 * We could have raced with another CPU caching the same
620 	 * translation behind our back, so let's check it is not in
621 	 * already
622 	 */
623 	db = its->vgic_its_base + GITS_TRANSLATER;
624 	if (__vgic_its_check_cache(dist, db, devid, eventid))
625 		goto out;
626 
627 	/* Always reuse the last entry (LRU policy) */
628 	cte = list_last_entry(&dist->lpi_translation_cache,
629 			      typeof(*cte), entry);
630 
631 	/*
632 	 * Caching the translation implies having an extra reference
633 	 * to the interrupt, so drop the potential reference on what
634 	 * was in the cache, and increment it on the new interrupt.
635 	 */
636 	if (cte->irq)
637 		__vgic_put_lpi_locked(kvm, cte->irq);
638 
639 	vgic_get_irq_kref(irq);
640 
641 	cte->db		= db;
642 	cte->devid	= devid;
643 	cte->eventid	= eventid;
644 	cte->irq	= irq;
645 
646 	/* Move the new translation to the head of the list */
647 	list_move(&cte->entry, &dist->lpi_translation_cache);
648 
649 out:
650 	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
651 }
652 
vgic_its_invalidate_cache(struct kvm * kvm)653 void vgic_its_invalidate_cache(struct kvm *kvm)
654 {
655 	struct vgic_dist *dist = &kvm->arch.vgic;
656 	struct vgic_translation_cache_entry *cte;
657 	unsigned long flags;
658 
659 	raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
660 
661 	list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
662 		/*
663 		 * If we hit a NULL entry, there is nothing after this
664 		 * point.
665 		 */
666 		if (!cte->irq)
667 			break;
668 
669 		__vgic_put_lpi_locked(kvm, cte->irq);
670 		cte->irq = NULL;
671 	}
672 
673 	raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
674 }
675 
vgic_its_resolve_lpi(struct kvm * kvm,struct vgic_its * its,u32 devid,u32 eventid,struct vgic_irq ** irq)676 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
677 			 u32 devid, u32 eventid, struct vgic_irq **irq)
678 {
679 	struct kvm_vcpu *vcpu;
680 	struct its_ite *ite;
681 
682 	if (!its->enabled)
683 		return -EBUSY;
684 
685 	ite = find_ite(its, devid, eventid);
686 	if (!ite || !its_is_collection_mapped(ite->collection))
687 		return E_ITS_INT_UNMAPPED_INTERRUPT;
688 
689 	vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
690 	if (!vcpu)
691 		return E_ITS_INT_UNMAPPED_INTERRUPT;
692 
693 	if (!vgic_lpis_enabled(vcpu))
694 		return -EBUSY;
695 
696 	vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq);
697 
698 	*irq = ite->irq;
699 	return 0;
700 }
701 
vgic_msi_to_its(struct kvm * kvm,struct kvm_msi * msi)702 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi)
703 {
704 	u64 address;
705 	struct kvm_io_device *kvm_io_dev;
706 	struct vgic_io_device *iodev;
707 
708 	if (!vgic_has_its(kvm))
709 		return ERR_PTR(-ENODEV);
710 
711 	if (!(msi->flags & KVM_MSI_VALID_DEVID))
712 		return ERR_PTR(-EINVAL);
713 
714 	address = (u64)msi->address_hi << 32 | msi->address_lo;
715 
716 	kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
717 	if (!kvm_io_dev)
718 		return ERR_PTR(-EINVAL);
719 
720 	if (kvm_io_dev->ops != &kvm_io_gic_ops)
721 		return ERR_PTR(-EINVAL);
722 
723 	iodev = container_of(kvm_io_dev, struct vgic_io_device, dev);
724 	if (iodev->iodev_type != IODEV_ITS)
725 		return ERR_PTR(-EINVAL);
726 
727 	return iodev->its;
728 }
729 
730 /*
731  * Find the target VCPU and the LPI number for a given devid/eventid pair
732  * and make this IRQ pending, possibly injecting it.
733  * Must be called with the its_lock mutex held.
734  * Returns 0 on success, a positive error value for any ITS mapping
735  * related errors and negative error values for generic errors.
736  */
vgic_its_trigger_msi(struct kvm * kvm,struct vgic_its * its,u32 devid,u32 eventid)737 static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
738 				u32 devid, u32 eventid)
739 {
740 	struct vgic_irq *irq = NULL;
741 	unsigned long flags;
742 	int err;
743 
744 	err = vgic_its_resolve_lpi(kvm, its, devid, eventid, &irq);
745 	if (err)
746 		return err;
747 
748 	if (irq->hw)
749 		return irq_set_irqchip_state(irq->host_irq,
750 					     IRQCHIP_STATE_PENDING, true);
751 
752 	raw_spin_lock_irqsave(&irq->irq_lock, flags);
753 	irq->pending_latch = true;
754 	vgic_queue_irq_unlock(kvm, irq, flags);
755 
756 	return 0;
757 }
758 
vgic_its_inject_cached_translation(struct kvm * kvm,struct kvm_msi * msi)759 int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi)
760 {
761 	struct vgic_irq *irq;
762 	unsigned long flags;
763 	phys_addr_t db;
764 
765 	db = (u64)msi->address_hi << 32 | msi->address_lo;
766 	irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data);
767 	if (!irq)
768 		return -EWOULDBLOCK;
769 
770 	raw_spin_lock_irqsave(&irq->irq_lock, flags);
771 	irq->pending_latch = true;
772 	vgic_queue_irq_unlock(kvm, irq, flags);
773 	vgic_put_irq(kvm, irq);
774 
775 	return 0;
776 }
777 
778 /*
779  * Queries the KVM IO bus framework to get the ITS pointer from the given
780  * doorbell address.
781  * We then call vgic_its_trigger_msi() with the decoded data.
782  * According to the KVM_SIGNAL_MSI API description returns 1 on success.
783  */
vgic_its_inject_msi(struct kvm * kvm,struct kvm_msi * msi)784 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
785 {
786 	struct vgic_its *its;
787 	int ret;
788 
789 	if (!vgic_its_inject_cached_translation(kvm, msi))
790 		return 1;
791 
792 	its = vgic_msi_to_its(kvm, msi);
793 	if (IS_ERR(its))
794 		return PTR_ERR(its);
795 
796 	mutex_lock(&its->its_lock);
797 	ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data);
798 	mutex_unlock(&its->its_lock);
799 
800 	if (ret < 0)
801 		return ret;
802 
803 	/*
804 	 * KVM_SIGNAL_MSI demands a return value > 0 for success and 0
805 	 * if the guest has blocked the MSI. So we map any LPI mapping
806 	 * related error to that.
807 	 */
808 	if (ret)
809 		return 0;
810 	else
811 		return 1;
812 }
813 
814 /* Requires the its_lock to be held. */
its_free_ite(struct kvm * kvm,struct its_ite * ite)815 static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
816 {
817 	list_del(&ite->ite_list);
818 
819 	/* This put matches the get in vgic_add_lpi. */
820 	if (ite->irq) {
821 		if (ite->irq->hw)
822 			WARN_ON(its_unmap_vlpi(ite->irq->host_irq));
823 
824 		vgic_put_irq(kvm, ite->irq);
825 	}
826 
827 	kfree(ite);
828 }
829 
its_cmd_mask_field(u64 * its_cmd,int word,int shift,int size)830 static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
831 {
832 	return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
833 }
834 
835 #define its_cmd_get_command(cmd)	its_cmd_mask_field(cmd, 0,  0,  8)
836 #define its_cmd_get_deviceid(cmd)	its_cmd_mask_field(cmd, 0, 32, 32)
837 #define its_cmd_get_size(cmd)		(its_cmd_mask_field(cmd, 1,  0,  5) + 1)
838 #define its_cmd_get_id(cmd)		its_cmd_mask_field(cmd, 1,  0, 32)
839 #define its_cmd_get_physical_id(cmd)	its_cmd_mask_field(cmd, 1, 32, 32)
840 #define its_cmd_get_collection(cmd)	its_cmd_mask_field(cmd, 2,  0, 16)
841 #define its_cmd_get_ittaddr(cmd)	(its_cmd_mask_field(cmd, 2,  8, 44) << 8)
842 #define its_cmd_get_target_addr(cmd)	its_cmd_mask_field(cmd, 2, 16, 32)
843 #define its_cmd_get_validbit(cmd)	its_cmd_mask_field(cmd, 2, 63,  1)
844 
845 /*
846  * The DISCARD command frees an Interrupt Translation Table Entry (ITTE).
847  * Must be called with the its_lock mutex held.
848  */
vgic_its_cmd_handle_discard(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)849 static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
850 				       u64 *its_cmd)
851 {
852 	u32 device_id = its_cmd_get_deviceid(its_cmd);
853 	u32 event_id = its_cmd_get_id(its_cmd);
854 	struct its_ite *ite;
855 
856 	ite = find_ite(its, device_id, event_id);
857 	if (ite && its_is_collection_mapped(ite->collection)) {
858 		/*
859 		 * Though the spec talks about removing the pending state, we
860 		 * don't bother here since we clear the ITTE anyway and the
861 		 * pending state is a property of the ITTE struct.
862 		 */
863 		vgic_its_invalidate_cache(kvm);
864 
865 		its_free_ite(kvm, ite);
866 		return 0;
867 	}
868 
869 	return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
870 }
871 
872 /*
873  * The MOVI command moves an ITTE to a different collection.
874  * Must be called with the its_lock mutex held.
875  */
vgic_its_cmd_handle_movi(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)876 static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
877 				    u64 *its_cmd)
878 {
879 	u32 device_id = its_cmd_get_deviceid(its_cmd);
880 	u32 event_id = its_cmd_get_id(its_cmd);
881 	u32 coll_id = its_cmd_get_collection(its_cmd);
882 	struct kvm_vcpu *vcpu;
883 	struct its_ite *ite;
884 	struct its_collection *collection;
885 
886 	ite = find_ite(its, device_id, event_id);
887 	if (!ite)
888 		return E_ITS_MOVI_UNMAPPED_INTERRUPT;
889 
890 	if (!its_is_collection_mapped(ite->collection))
891 		return E_ITS_MOVI_UNMAPPED_COLLECTION;
892 
893 	collection = find_collection(its, coll_id);
894 	if (!its_is_collection_mapped(collection))
895 		return E_ITS_MOVI_UNMAPPED_COLLECTION;
896 
897 	ite->collection = collection;
898 	vcpu = kvm_get_vcpu(kvm, collection->target_addr);
899 
900 	vgic_its_invalidate_cache(kvm);
901 
902 	return update_affinity(ite->irq, vcpu);
903 }
904 
__is_visible_gfn_locked(struct vgic_its * its,gpa_t gpa)905 static bool __is_visible_gfn_locked(struct vgic_its *its, gpa_t gpa)
906 {
907 	gfn_t gfn = gpa >> PAGE_SHIFT;
908 	int idx;
909 	bool ret;
910 
911 	idx = srcu_read_lock(&its->dev->kvm->srcu);
912 	ret = kvm_is_visible_gfn(its->dev->kvm, gfn);
913 	srcu_read_unlock(&its->dev->kvm->srcu, idx);
914 	return ret;
915 }
916 
917 /*
918  * Check whether an ID can be stored into the corresponding guest table.
919  * For a direct table this is pretty easy, but gets a bit nasty for
920  * indirect tables. We check whether the resulting guest physical address
921  * is actually valid (covered by a memslot and guest accessible).
922  * For this we have to read the respective first level entry.
923  */
vgic_its_check_id(struct vgic_its * its,u64 baser,u32 id,gpa_t * eaddr)924 static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
925 			      gpa_t *eaddr)
926 {
927 	int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
928 	u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
929 	phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser);
930 	int esz = GITS_BASER_ENTRY_SIZE(baser);
931 	int index;
932 
933 	switch (type) {
934 	case GITS_BASER_TYPE_DEVICE:
935 		if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
936 			return false;
937 		break;
938 	case GITS_BASER_TYPE_COLLECTION:
939 		/* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
940 		if (id >= BIT_ULL(16))
941 			return false;
942 		break;
943 	default:
944 		return false;
945 	}
946 
947 	if (!(baser & GITS_BASER_INDIRECT)) {
948 		phys_addr_t addr;
949 
950 		if (id >= (l1_tbl_size / esz))
951 			return false;
952 
953 		addr = base + id * esz;
954 
955 		if (eaddr)
956 			*eaddr = addr;
957 
958 		return __is_visible_gfn_locked(its, addr);
959 	}
960 
961 	/* calculate and check the index into the 1st level */
962 	index = id / (SZ_64K / esz);
963 	if (index >= (l1_tbl_size / sizeof(u64)))
964 		return false;
965 
966 	/* Each 1st level entry is represented by a 64-bit value. */
967 	if (kvm_read_guest_lock(its->dev->kvm,
968 			   base + index * sizeof(indirect_ptr),
969 			   &indirect_ptr, sizeof(indirect_ptr)))
970 		return false;
971 
972 	indirect_ptr = le64_to_cpu(indirect_ptr);
973 
974 	/* check the valid bit of the first level entry */
975 	if (!(indirect_ptr & BIT_ULL(63)))
976 		return false;
977 
978 	/* Mask the guest physical address and calculate the frame number. */
979 	indirect_ptr &= GENMASK_ULL(51, 16);
980 
981 	/* Find the address of the actual entry */
982 	index = id % (SZ_64K / esz);
983 	indirect_ptr += index * esz;
984 
985 	if (eaddr)
986 		*eaddr = indirect_ptr;
987 
988 	return __is_visible_gfn_locked(its, indirect_ptr);
989 }
990 
991 /*
992  * Check whether an event ID can be stored in the corresponding Interrupt
993  * Translation Table, which starts at device->itt_addr.
994  */
vgic_its_check_event_id(struct vgic_its * its,struct its_device * device,u32 event_id)995 static bool vgic_its_check_event_id(struct vgic_its *its, struct its_device *device,
996 		u32 event_id)
997 {
998 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
999 	int ite_esz = abi->ite_esz;
1000 	gpa_t gpa;
1001 
1002 	/* max table size is: BIT_ULL(device->num_eventid_bits) * ite_esz */
1003 	if (event_id >= BIT_ULL(device->num_eventid_bits))
1004 		return false;
1005 
1006 	gpa = device->itt_addr + event_id * ite_esz;
1007 	return __is_visible_gfn_locked(its, gpa);
1008 }
1009 
1010 /*
1011  * Add a new collection into the ITS collection table.
1012  * Returns 0 on success, and a negative error value for generic errors.
1013  */
vgic_its_alloc_collection(struct vgic_its * its,struct its_collection ** colp,u32 coll_id)1014 static int vgic_its_alloc_collection(struct vgic_its *its,
1015 				     struct its_collection **colp,
1016 				     u32 coll_id)
1017 {
1018 	struct its_collection *collection;
1019 
1020 	collection = kzalloc(sizeof(*collection), GFP_KERNEL_ACCOUNT);
1021 	if (!collection)
1022 		return -ENOMEM;
1023 
1024 	collection->collection_id = coll_id;
1025 	collection->target_addr = COLLECTION_NOT_MAPPED;
1026 
1027 	list_add_tail(&collection->coll_list, &its->collection_list);
1028 	*colp = collection;
1029 
1030 	return 0;
1031 }
1032 
vgic_its_free_collection(struct vgic_its * its,u32 coll_id)1033 static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
1034 {
1035 	struct its_collection *collection;
1036 	struct its_device *device;
1037 	struct its_ite *ite;
1038 
1039 	/*
1040 	 * Clearing the mapping for that collection ID removes the
1041 	 * entry from the list. If there wasn't any before, we can
1042 	 * go home early.
1043 	 */
1044 	collection = find_collection(its, coll_id);
1045 	if (!collection)
1046 		return;
1047 
1048 	for_each_lpi_its(device, ite, its)
1049 		if (ite->collection &&
1050 		    ite->collection->collection_id == coll_id)
1051 			ite->collection = NULL;
1052 
1053 	list_del(&collection->coll_list);
1054 	kfree(collection);
1055 }
1056 
1057 /* Must be called with its_lock mutex held */
vgic_its_alloc_ite(struct its_device * device,struct its_collection * collection,u32 event_id)1058 static struct its_ite *vgic_its_alloc_ite(struct its_device *device,
1059 					  struct its_collection *collection,
1060 					  u32 event_id)
1061 {
1062 	struct its_ite *ite;
1063 
1064 	ite = kzalloc(sizeof(*ite), GFP_KERNEL_ACCOUNT);
1065 	if (!ite)
1066 		return ERR_PTR(-ENOMEM);
1067 
1068 	ite->event_id	= event_id;
1069 	ite->collection = collection;
1070 
1071 	list_add_tail(&ite->ite_list, &device->itt_head);
1072 	return ite;
1073 }
1074 
1075 /*
1076  * The MAPTI and MAPI commands map LPIs to ITTEs.
1077  * Must be called with its_lock mutex held.
1078  */
vgic_its_cmd_handle_mapi(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1079 static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
1080 				    u64 *its_cmd)
1081 {
1082 	u32 device_id = its_cmd_get_deviceid(its_cmd);
1083 	u32 event_id = its_cmd_get_id(its_cmd);
1084 	u32 coll_id = its_cmd_get_collection(its_cmd);
1085 	struct its_ite *ite;
1086 	struct kvm_vcpu *vcpu = NULL;
1087 	struct its_device *device;
1088 	struct its_collection *collection, *new_coll = NULL;
1089 	struct vgic_irq *irq;
1090 	int lpi_nr;
1091 
1092 	device = find_its_device(its, device_id);
1093 	if (!device)
1094 		return E_ITS_MAPTI_UNMAPPED_DEVICE;
1095 
1096 	if (!vgic_its_check_event_id(its, device, event_id))
1097 		return E_ITS_MAPTI_ID_OOR;
1098 
1099 	if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
1100 		lpi_nr = its_cmd_get_physical_id(its_cmd);
1101 	else
1102 		lpi_nr = event_id;
1103 	if (lpi_nr < GIC_LPI_OFFSET ||
1104 	    lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser))
1105 		return E_ITS_MAPTI_PHYSICALID_OOR;
1106 
1107 	/* If there is an existing mapping, behavior is UNPREDICTABLE. */
1108 	if (find_ite(its, device_id, event_id))
1109 		return 0;
1110 
1111 	collection = find_collection(its, coll_id);
1112 	if (!collection) {
1113 		int ret;
1114 
1115 		if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
1116 			return E_ITS_MAPC_COLLECTION_OOR;
1117 
1118 		ret = vgic_its_alloc_collection(its, &collection, coll_id);
1119 		if (ret)
1120 			return ret;
1121 		new_coll = collection;
1122 	}
1123 
1124 	ite = vgic_its_alloc_ite(device, collection, event_id);
1125 	if (IS_ERR(ite)) {
1126 		if (new_coll)
1127 			vgic_its_free_collection(its, coll_id);
1128 		return PTR_ERR(ite);
1129 	}
1130 
1131 	if (its_is_collection_mapped(collection))
1132 		vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1133 
1134 	irq = vgic_add_lpi(kvm, lpi_nr, vcpu);
1135 	if (IS_ERR(irq)) {
1136 		if (new_coll)
1137 			vgic_its_free_collection(its, coll_id);
1138 		its_free_ite(kvm, ite);
1139 		return PTR_ERR(irq);
1140 	}
1141 	ite->irq = irq;
1142 
1143 	return 0;
1144 }
1145 
1146 /* Requires the its_lock to be held. */
vgic_its_free_device(struct kvm * kvm,struct its_device * device)1147 static void vgic_its_free_device(struct kvm *kvm, struct its_device *device)
1148 {
1149 	struct its_ite *ite, *temp;
1150 
1151 	/*
1152 	 * The spec says that unmapping a device with still valid
1153 	 * ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
1154 	 * since we cannot leave the memory unreferenced.
1155 	 */
1156 	list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
1157 		its_free_ite(kvm, ite);
1158 
1159 	vgic_its_invalidate_cache(kvm);
1160 
1161 	list_del(&device->dev_list);
1162 	kfree(device);
1163 }
1164 
1165 /* its lock must be held */
vgic_its_free_device_list(struct kvm * kvm,struct vgic_its * its)1166 static void vgic_its_free_device_list(struct kvm *kvm, struct vgic_its *its)
1167 {
1168 	struct its_device *cur, *temp;
1169 
1170 	list_for_each_entry_safe(cur, temp, &its->device_list, dev_list)
1171 		vgic_its_free_device(kvm, cur);
1172 }
1173 
1174 /* its lock must be held */
vgic_its_free_collection_list(struct kvm * kvm,struct vgic_its * its)1175 static void vgic_its_free_collection_list(struct kvm *kvm, struct vgic_its *its)
1176 {
1177 	struct its_collection *cur, *temp;
1178 
1179 	list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
1180 		vgic_its_free_collection(its, cur->collection_id);
1181 }
1182 
1183 /* Must be called with its_lock mutex held */
vgic_its_alloc_device(struct vgic_its * its,u32 device_id,gpa_t itt_addr,u8 num_eventid_bits)1184 static struct its_device *vgic_its_alloc_device(struct vgic_its *its,
1185 						u32 device_id, gpa_t itt_addr,
1186 						u8 num_eventid_bits)
1187 {
1188 	struct its_device *device;
1189 
1190 	device = kzalloc(sizeof(*device), GFP_KERNEL_ACCOUNT);
1191 	if (!device)
1192 		return ERR_PTR(-ENOMEM);
1193 
1194 	device->device_id = device_id;
1195 	device->itt_addr = itt_addr;
1196 	device->num_eventid_bits = num_eventid_bits;
1197 	INIT_LIST_HEAD(&device->itt_head);
1198 
1199 	list_add_tail(&device->dev_list, &its->device_list);
1200 	return device;
1201 }
1202 
1203 /*
1204  * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
1205  * Must be called with the its_lock mutex held.
1206  */
vgic_its_cmd_handle_mapd(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1207 static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
1208 				    u64 *its_cmd)
1209 {
1210 	u32 device_id = its_cmd_get_deviceid(its_cmd);
1211 	bool valid = its_cmd_get_validbit(its_cmd);
1212 	u8 num_eventid_bits = its_cmd_get_size(its_cmd);
1213 	gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
1214 	struct its_device *device;
1215 
1216 	if (!vgic_its_check_id(its, its->baser_device_table, device_id, NULL))
1217 		return E_ITS_MAPD_DEVICE_OOR;
1218 
1219 	if (valid && num_eventid_bits > VITS_TYPER_IDBITS)
1220 		return E_ITS_MAPD_ITTSIZE_OOR;
1221 
1222 	device = find_its_device(its, device_id);
1223 
1224 	/*
1225 	 * The spec says that calling MAPD on an already mapped device
1226 	 * invalidates all cached data for this device. We implement this
1227 	 * by removing the mapping and re-establishing it.
1228 	 */
1229 	if (device)
1230 		vgic_its_free_device(kvm, device);
1231 
1232 	/*
1233 	 * The spec does not say whether unmapping a not-mapped device
1234 	 * is an error, so we are done in any case.
1235 	 */
1236 	if (!valid)
1237 		return 0;
1238 
1239 	device = vgic_its_alloc_device(its, device_id, itt_addr,
1240 				       num_eventid_bits);
1241 
1242 	return PTR_ERR_OR_ZERO(device);
1243 }
1244 
1245 /*
1246  * The MAPC command maps collection IDs to redistributors.
1247  * Must be called with the its_lock mutex held.
1248  */
vgic_its_cmd_handle_mapc(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1249 static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its,
1250 				    u64 *its_cmd)
1251 {
1252 	u16 coll_id;
1253 	u32 target_addr;
1254 	struct its_collection *collection;
1255 	bool valid;
1256 
1257 	valid = its_cmd_get_validbit(its_cmd);
1258 	coll_id = its_cmd_get_collection(its_cmd);
1259 	target_addr = its_cmd_get_target_addr(its_cmd);
1260 
1261 	if (target_addr >= atomic_read(&kvm->online_vcpus))
1262 		return E_ITS_MAPC_PROCNUM_OOR;
1263 
1264 	if (!valid) {
1265 		vgic_its_free_collection(its, coll_id);
1266 		vgic_its_invalidate_cache(kvm);
1267 	} else {
1268 		collection = find_collection(its, coll_id);
1269 
1270 		if (!collection) {
1271 			int ret;
1272 
1273 			if (!vgic_its_check_id(its, its->baser_coll_table,
1274 						coll_id, NULL))
1275 				return E_ITS_MAPC_COLLECTION_OOR;
1276 
1277 			ret = vgic_its_alloc_collection(its, &collection,
1278 							coll_id);
1279 			if (ret)
1280 				return ret;
1281 			collection->target_addr = target_addr;
1282 		} else {
1283 			collection->target_addr = target_addr;
1284 			update_affinity_collection(kvm, its, collection);
1285 		}
1286 	}
1287 
1288 	return 0;
1289 }
1290 
1291 /*
1292  * The CLEAR command removes the pending state for a particular LPI.
1293  * Must be called with the its_lock mutex held.
1294  */
vgic_its_cmd_handle_clear(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1295 static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
1296 				     u64 *its_cmd)
1297 {
1298 	u32 device_id = its_cmd_get_deviceid(its_cmd);
1299 	u32 event_id = its_cmd_get_id(its_cmd);
1300 	struct its_ite *ite;
1301 
1302 
1303 	ite = find_ite(its, device_id, event_id);
1304 	if (!ite)
1305 		return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
1306 
1307 	ite->irq->pending_latch = false;
1308 
1309 	if (ite->irq->hw)
1310 		return irq_set_irqchip_state(ite->irq->host_irq,
1311 					     IRQCHIP_STATE_PENDING, false);
1312 
1313 	return 0;
1314 }
1315 
vgic_its_inv_lpi(struct kvm * kvm,struct vgic_irq * irq)1316 int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq)
1317 {
1318 	return update_lpi_config(kvm, irq, NULL, true);
1319 }
1320 
1321 /*
1322  * The INV command syncs the configuration bits from the memory table.
1323  * Must be called with the its_lock mutex held.
1324  */
vgic_its_cmd_handle_inv(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1325 static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
1326 				   u64 *its_cmd)
1327 {
1328 	u32 device_id = its_cmd_get_deviceid(its_cmd);
1329 	u32 event_id = its_cmd_get_id(its_cmd);
1330 	struct its_ite *ite;
1331 
1332 
1333 	ite = find_ite(its, device_id, event_id);
1334 	if (!ite)
1335 		return E_ITS_INV_UNMAPPED_INTERRUPT;
1336 
1337 	return vgic_its_inv_lpi(kvm, ite->irq);
1338 }
1339 
1340 /**
1341  * vgic_its_invall - invalidate all LPIs targetting a given vcpu
1342  * @vcpu: the vcpu for which the RD is targetted by an invalidation
1343  *
1344  * Contrary to the INVALL command, this targets a RD instead of a
1345  * collection, and we don't need to hold the its_lock, since no ITS is
1346  * involved here.
1347  */
vgic_its_invall(struct kvm_vcpu * vcpu)1348 int vgic_its_invall(struct kvm_vcpu *vcpu)
1349 {
1350 	struct kvm *kvm = vcpu->kvm;
1351 	int irq_count, i = 0;
1352 	u32 *intids;
1353 
1354 	irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids);
1355 	if (irq_count < 0)
1356 		return irq_count;
1357 
1358 	for (i = 0; i < irq_count; i++) {
1359 		struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intids[i]);
1360 		if (!irq)
1361 			continue;
1362 		update_lpi_config(kvm, irq, vcpu, false);
1363 		vgic_put_irq(kvm, irq);
1364 	}
1365 
1366 	kfree(intids);
1367 
1368 	if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm)
1369 		its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe);
1370 
1371 	return 0;
1372 }
1373 
1374 /*
1375  * The INVALL command requests flushing of all IRQ data in this collection.
1376  * Find the VCPU mapped to that collection, then iterate over the VM's list
1377  * of mapped LPIs and update the configuration for each IRQ which targets
1378  * the specified vcpu. The configuration will be read from the in-memory
1379  * configuration table.
1380  * Must be called with the its_lock mutex held.
1381  */
vgic_its_cmd_handle_invall(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1382 static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its,
1383 				      u64 *its_cmd)
1384 {
1385 	u32 coll_id = its_cmd_get_collection(its_cmd);
1386 	struct its_collection *collection;
1387 	struct kvm_vcpu *vcpu;
1388 
1389 	collection = find_collection(its, coll_id);
1390 	if (!its_is_collection_mapped(collection))
1391 		return E_ITS_INVALL_UNMAPPED_COLLECTION;
1392 
1393 	vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1394 	vgic_its_invall(vcpu);
1395 
1396 	return 0;
1397 }
1398 
1399 /*
1400  * The MOVALL command moves the pending state of all IRQs targeting one
1401  * redistributor to another. We don't hold the pending state in the VCPUs,
1402  * but in the IRQs instead, so there is really not much to do for us here.
1403  * However the spec says that no IRQ must target the old redistributor
1404  * afterwards, so we make sure that no LPI is using the associated target_vcpu.
1405  * This command affects all LPIs in the system that target that redistributor.
1406  */
vgic_its_cmd_handle_movall(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1407 static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its,
1408 				      u64 *its_cmd)
1409 {
1410 	u32 target1_addr = its_cmd_get_target_addr(its_cmd);
1411 	u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
1412 	struct kvm_vcpu *vcpu1, *vcpu2;
1413 	struct vgic_irq *irq;
1414 	u32 *intids;
1415 	int irq_count, i;
1416 
1417 	if (target1_addr >= atomic_read(&kvm->online_vcpus) ||
1418 	    target2_addr >= atomic_read(&kvm->online_vcpus))
1419 		return E_ITS_MOVALL_PROCNUM_OOR;
1420 
1421 	if (target1_addr == target2_addr)
1422 		return 0;
1423 
1424 	vcpu1 = kvm_get_vcpu(kvm, target1_addr);
1425 	vcpu2 = kvm_get_vcpu(kvm, target2_addr);
1426 
1427 	irq_count = vgic_copy_lpi_list(kvm, vcpu1, &intids);
1428 	if (irq_count < 0)
1429 		return irq_count;
1430 
1431 	for (i = 0; i < irq_count; i++) {
1432 		irq = vgic_get_irq(kvm, NULL, intids[i]);
1433 		if (!irq)
1434 			continue;
1435 
1436 		update_affinity(irq, vcpu2);
1437 
1438 		vgic_put_irq(kvm, irq);
1439 	}
1440 
1441 	vgic_its_invalidate_cache(kvm);
1442 
1443 	kfree(intids);
1444 	return 0;
1445 }
1446 
1447 /*
1448  * The INT command injects the LPI associated with that DevID/EvID pair.
1449  * Must be called with the its_lock mutex held.
1450  */
vgic_its_cmd_handle_int(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1451 static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its,
1452 				   u64 *its_cmd)
1453 {
1454 	u32 msi_data = its_cmd_get_id(its_cmd);
1455 	u64 msi_devid = its_cmd_get_deviceid(its_cmd);
1456 
1457 	return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data);
1458 }
1459 
1460 /*
1461  * This function is called with the its_cmd lock held, but the ITS data
1462  * structure lock dropped.
1463  */
vgic_its_handle_command(struct kvm * kvm,struct vgic_its * its,u64 * its_cmd)1464 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
1465 				   u64 *its_cmd)
1466 {
1467 	int ret = -ENODEV;
1468 
1469 	mutex_lock(&its->its_lock);
1470 	switch (its_cmd_get_command(its_cmd)) {
1471 	case GITS_CMD_MAPD:
1472 		ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd);
1473 		break;
1474 	case GITS_CMD_MAPC:
1475 		ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd);
1476 		break;
1477 	case GITS_CMD_MAPI:
1478 		ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1479 		break;
1480 	case GITS_CMD_MAPTI:
1481 		ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1482 		break;
1483 	case GITS_CMD_MOVI:
1484 		ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd);
1485 		break;
1486 	case GITS_CMD_DISCARD:
1487 		ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd);
1488 		break;
1489 	case GITS_CMD_CLEAR:
1490 		ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd);
1491 		break;
1492 	case GITS_CMD_MOVALL:
1493 		ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd);
1494 		break;
1495 	case GITS_CMD_INT:
1496 		ret = vgic_its_cmd_handle_int(kvm, its, its_cmd);
1497 		break;
1498 	case GITS_CMD_INV:
1499 		ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd);
1500 		break;
1501 	case GITS_CMD_INVALL:
1502 		ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd);
1503 		break;
1504 	case GITS_CMD_SYNC:
1505 		/* we ignore this command: we are in sync all of the time */
1506 		ret = 0;
1507 		break;
1508 	}
1509 	mutex_unlock(&its->its_lock);
1510 
1511 	return ret;
1512 }
1513 
vgic_sanitise_its_baser(u64 reg)1514 static u64 vgic_sanitise_its_baser(u64 reg)
1515 {
1516 	reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
1517 				  GITS_BASER_SHAREABILITY_SHIFT,
1518 				  vgic_sanitise_shareability);
1519 	reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
1520 				  GITS_BASER_INNER_CACHEABILITY_SHIFT,
1521 				  vgic_sanitise_inner_cacheability);
1522 	reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
1523 				  GITS_BASER_OUTER_CACHEABILITY_SHIFT,
1524 				  vgic_sanitise_outer_cacheability);
1525 
1526 	/* We support only one (ITS) page size: 64K */
1527 	reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
1528 
1529 	return reg;
1530 }
1531 
vgic_sanitise_its_cbaser(u64 reg)1532 static u64 vgic_sanitise_its_cbaser(u64 reg)
1533 {
1534 	reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
1535 				  GITS_CBASER_SHAREABILITY_SHIFT,
1536 				  vgic_sanitise_shareability);
1537 	reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
1538 				  GITS_CBASER_INNER_CACHEABILITY_SHIFT,
1539 				  vgic_sanitise_inner_cacheability);
1540 	reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
1541 				  GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
1542 				  vgic_sanitise_outer_cacheability);
1543 
1544 	/* Sanitise the physical address to be 64k aligned. */
1545 	reg &= ~GENMASK_ULL(15, 12);
1546 
1547 	return reg;
1548 }
1549 
vgic_mmio_read_its_cbaser(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)1550 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
1551 					       struct vgic_its *its,
1552 					       gpa_t addr, unsigned int len)
1553 {
1554 	return extract_bytes(its->cbaser, addr & 7, len);
1555 }
1556 
vgic_mmio_write_its_cbaser(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1557 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
1558 				       gpa_t addr, unsigned int len,
1559 				       unsigned long val)
1560 {
1561 	/* When GITS_CTLR.Enable is 1, this register is RO. */
1562 	if (its->enabled)
1563 		return;
1564 
1565 	mutex_lock(&its->cmd_lock);
1566 	its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
1567 	its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
1568 	its->creadr = 0;
1569 	/*
1570 	 * CWRITER is architecturally UNKNOWN on reset, but we need to reset
1571 	 * it to CREADR to make sure we start with an empty command buffer.
1572 	 */
1573 	its->cwriter = its->creadr;
1574 	mutex_unlock(&its->cmd_lock);
1575 }
1576 
1577 #define ITS_CMD_BUFFER_SIZE(baser)	((((baser) & 0xff) + 1) << 12)
1578 #define ITS_CMD_SIZE			32
1579 #define ITS_CMD_OFFSET(reg)		((reg) & GENMASK(19, 5))
1580 
1581 /* Must be called with the cmd_lock held. */
vgic_its_process_commands(struct kvm * kvm,struct vgic_its * its)1582 static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
1583 {
1584 	gpa_t cbaser;
1585 	u64 cmd_buf[4];
1586 
1587 	/* Commands are only processed when the ITS is enabled. */
1588 	if (!its->enabled)
1589 		return;
1590 
1591 	cbaser = GITS_CBASER_ADDRESS(its->cbaser);
1592 
1593 	while (its->cwriter != its->creadr) {
1594 		int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr,
1595 					      cmd_buf, ITS_CMD_SIZE);
1596 		/*
1597 		 * If kvm_read_guest() fails, this could be due to the guest
1598 		 * programming a bogus value in CBASER or something else going
1599 		 * wrong from which we cannot easily recover.
1600 		 * According to section 6.3.2 in the GICv3 spec we can just
1601 		 * ignore that command then.
1602 		 */
1603 		if (!ret)
1604 			vgic_its_handle_command(kvm, its, cmd_buf);
1605 
1606 		its->creadr += ITS_CMD_SIZE;
1607 		if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
1608 			its->creadr = 0;
1609 	}
1610 }
1611 
1612 /*
1613  * By writing to CWRITER the guest announces new commands to be processed.
1614  * To avoid any races in the first place, we take the its_cmd lock, which
1615  * protects our ring buffer variables, so that there is only one user
1616  * per ITS handling commands at a given time.
1617  */
vgic_mmio_write_its_cwriter(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1618 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
1619 					gpa_t addr, unsigned int len,
1620 					unsigned long val)
1621 {
1622 	u64 reg;
1623 
1624 	if (!its)
1625 		return;
1626 
1627 	mutex_lock(&its->cmd_lock);
1628 
1629 	reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
1630 	reg = ITS_CMD_OFFSET(reg);
1631 	if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1632 		mutex_unlock(&its->cmd_lock);
1633 		return;
1634 	}
1635 	its->cwriter = reg;
1636 
1637 	vgic_its_process_commands(kvm, its);
1638 
1639 	mutex_unlock(&its->cmd_lock);
1640 }
1641 
vgic_mmio_read_its_cwriter(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)1642 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
1643 						struct vgic_its *its,
1644 						gpa_t addr, unsigned int len)
1645 {
1646 	return extract_bytes(its->cwriter, addr & 0x7, len);
1647 }
1648 
vgic_mmio_read_its_creadr(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)1649 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
1650 					       struct vgic_its *its,
1651 					       gpa_t addr, unsigned int len)
1652 {
1653 	return extract_bytes(its->creadr, addr & 0x7, len);
1654 }
1655 
vgic_mmio_uaccess_write_its_creadr(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1656 static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
1657 					      struct vgic_its *its,
1658 					      gpa_t addr, unsigned int len,
1659 					      unsigned long val)
1660 {
1661 	u32 cmd_offset;
1662 	int ret = 0;
1663 
1664 	mutex_lock(&its->cmd_lock);
1665 
1666 	if (its->enabled) {
1667 		ret = -EBUSY;
1668 		goto out;
1669 	}
1670 
1671 	cmd_offset = ITS_CMD_OFFSET(val);
1672 	if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1673 		ret = -EINVAL;
1674 		goto out;
1675 	}
1676 
1677 	its->creadr = cmd_offset;
1678 out:
1679 	mutex_unlock(&its->cmd_lock);
1680 	return ret;
1681 }
1682 
1683 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
vgic_mmio_read_its_baser(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len)1684 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
1685 					      struct vgic_its *its,
1686 					      gpa_t addr, unsigned int len)
1687 {
1688 	u64 reg;
1689 
1690 	switch (BASER_INDEX(addr)) {
1691 	case 0:
1692 		reg = its->baser_device_table;
1693 		break;
1694 	case 1:
1695 		reg = its->baser_coll_table;
1696 		break;
1697 	default:
1698 		reg = 0;
1699 		break;
1700 	}
1701 
1702 	return extract_bytes(reg, addr & 7, len);
1703 }
1704 
1705 #define GITS_BASER_RO_MASK	(GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
vgic_mmio_write_its_baser(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1706 static void vgic_mmio_write_its_baser(struct kvm *kvm,
1707 				      struct vgic_its *its,
1708 				      gpa_t addr, unsigned int len,
1709 				      unsigned long val)
1710 {
1711 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
1712 	u64 entry_size, table_type;
1713 	u64 reg, *regptr, clearbits = 0;
1714 
1715 	/* When GITS_CTLR.Enable is 1, we ignore write accesses. */
1716 	if (its->enabled)
1717 		return;
1718 
1719 	switch (BASER_INDEX(addr)) {
1720 	case 0:
1721 		regptr = &its->baser_device_table;
1722 		entry_size = abi->dte_esz;
1723 		table_type = GITS_BASER_TYPE_DEVICE;
1724 		break;
1725 	case 1:
1726 		regptr = &its->baser_coll_table;
1727 		entry_size = abi->cte_esz;
1728 		table_type = GITS_BASER_TYPE_COLLECTION;
1729 		clearbits = GITS_BASER_INDIRECT;
1730 		break;
1731 	default:
1732 		return;
1733 	}
1734 
1735 	reg = update_64bit_reg(*regptr, addr & 7, len, val);
1736 	reg &= ~GITS_BASER_RO_MASK;
1737 	reg &= ~clearbits;
1738 
1739 	reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
1740 	reg |= table_type << GITS_BASER_TYPE_SHIFT;
1741 	reg = vgic_sanitise_its_baser(reg);
1742 
1743 	*regptr = reg;
1744 
1745 	if (!(reg & GITS_BASER_VALID)) {
1746 		/* Take the its_lock to prevent a race with a save/restore */
1747 		mutex_lock(&its->its_lock);
1748 		switch (table_type) {
1749 		case GITS_BASER_TYPE_DEVICE:
1750 			vgic_its_free_device_list(kvm, its);
1751 			break;
1752 		case GITS_BASER_TYPE_COLLECTION:
1753 			vgic_its_free_collection_list(kvm, its);
1754 			break;
1755 		}
1756 		mutex_unlock(&its->its_lock);
1757 	}
1758 }
1759 
vgic_mmio_read_its_ctlr(struct kvm * vcpu,struct vgic_its * its,gpa_t addr,unsigned int len)1760 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
1761 					     struct vgic_its *its,
1762 					     gpa_t addr, unsigned int len)
1763 {
1764 	u32 reg = 0;
1765 
1766 	mutex_lock(&its->cmd_lock);
1767 	if (its->creadr == its->cwriter)
1768 		reg |= GITS_CTLR_QUIESCENT;
1769 	if (its->enabled)
1770 		reg |= GITS_CTLR_ENABLE;
1771 	mutex_unlock(&its->cmd_lock);
1772 
1773 	return reg;
1774 }
1775 
vgic_mmio_write_its_ctlr(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1776 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
1777 				     gpa_t addr, unsigned int len,
1778 				     unsigned long val)
1779 {
1780 	mutex_lock(&its->cmd_lock);
1781 
1782 	/*
1783 	 * It is UNPREDICTABLE to enable the ITS if any of the CBASER or
1784 	 * device/collection BASER are invalid
1785 	 */
1786 	if (!its->enabled && (val & GITS_CTLR_ENABLE) &&
1787 		(!(its->baser_device_table & GITS_BASER_VALID) ||
1788 		 !(its->baser_coll_table & GITS_BASER_VALID) ||
1789 		 !(its->cbaser & GITS_CBASER_VALID)))
1790 		goto out;
1791 
1792 	its->enabled = !!(val & GITS_CTLR_ENABLE);
1793 	if (!its->enabled)
1794 		vgic_its_invalidate_cache(kvm);
1795 
1796 	/*
1797 	 * Try to process any pending commands. This function bails out early
1798 	 * if the ITS is disabled or no commands have been queued.
1799 	 */
1800 	vgic_its_process_commands(kvm, its);
1801 
1802 out:
1803 	mutex_unlock(&its->cmd_lock);
1804 }
1805 
1806 #define REGISTER_ITS_DESC(off, rd, wr, length, acc)		\
1807 {								\
1808 	.reg_offset = off,					\
1809 	.len = length,						\
1810 	.access_flags = acc,					\
1811 	.its_read = rd,						\
1812 	.its_write = wr,					\
1813 }
1814 
1815 #define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
1816 {								\
1817 	.reg_offset = off,					\
1818 	.len = length,						\
1819 	.access_flags = acc,					\
1820 	.its_read = rd,						\
1821 	.its_write = wr,					\
1822 	.uaccess_its_write = uwr,				\
1823 }
1824 
its_mmio_write_wi(struct kvm * kvm,struct vgic_its * its,gpa_t addr,unsigned int len,unsigned long val)1825 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
1826 			      gpa_t addr, unsigned int len, unsigned long val)
1827 {
1828 	/* Ignore */
1829 }
1830 
1831 static struct vgic_register_region its_registers[] = {
1832 	REGISTER_ITS_DESC(GITS_CTLR,
1833 		vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
1834 		VGIC_ACCESS_32bit),
1835 	REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
1836 		vgic_mmio_read_its_iidr, its_mmio_write_wi,
1837 		vgic_mmio_uaccess_write_its_iidr, 4,
1838 		VGIC_ACCESS_32bit),
1839 	REGISTER_ITS_DESC(GITS_TYPER,
1840 		vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
1841 		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1842 	REGISTER_ITS_DESC(GITS_CBASER,
1843 		vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
1844 		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1845 	REGISTER_ITS_DESC(GITS_CWRITER,
1846 		vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
1847 		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1848 	REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
1849 		vgic_mmio_read_its_creadr, its_mmio_write_wi,
1850 		vgic_mmio_uaccess_write_its_creadr, 8,
1851 		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1852 	REGISTER_ITS_DESC(GITS_BASER,
1853 		vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
1854 		VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1855 	REGISTER_ITS_DESC(GITS_IDREGS_BASE,
1856 		vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
1857 		VGIC_ACCESS_32bit),
1858 };
1859 
1860 /* This is called on setting the LPI enable bit in the redistributor. */
vgic_enable_lpis(struct kvm_vcpu * vcpu)1861 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
1862 {
1863 	if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
1864 		its_sync_lpi_pending_table(vcpu);
1865 }
1866 
vgic_register_its_iodev(struct kvm * kvm,struct vgic_its * its,u64 addr)1867 static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its,
1868 				   u64 addr)
1869 {
1870 	struct vgic_io_device *iodev = &its->iodev;
1871 	int ret;
1872 
1873 	mutex_lock(&kvm->slots_lock);
1874 	if (!IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1875 		ret = -EBUSY;
1876 		goto out;
1877 	}
1878 
1879 	its->vgic_its_base = addr;
1880 	iodev->regions = its_registers;
1881 	iodev->nr_regions = ARRAY_SIZE(its_registers);
1882 	kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
1883 
1884 	iodev->base_addr = its->vgic_its_base;
1885 	iodev->iodev_type = IODEV_ITS;
1886 	iodev->its = its;
1887 	ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
1888 				      KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
1889 out:
1890 	mutex_unlock(&kvm->slots_lock);
1891 
1892 	return ret;
1893 }
1894 
1895 /* Default is 16 cached LPIs per vcpu */
1896 #define LPI_DEFAULT_PCPU_CACHE_SIZE	16
1897 
vgic_lpi_translation_cache_init(struct kvm * kvm)1898 void vgic_lpi_translation_cache_init(struct kvm *kvm)
1899 {
1900 	struct vgic_dist *dist = &kvm->arch.vgic;
1901 	unsigned int sz;
1902 	int i;
1903 
1904 	if (!list_empty(&dist->lpi_translation_cache))
1905 		return;
1906 
1907 	sz = atomic_read(&kvm->online_vcpus) * LPI_DEFAULT_PCPU_CACHE_SIZE;
1908 
1909 	for (i = 0; i < sz; i++) {
1910 		struct vgic_translation_cache_entry *cte;
1911 
1912 		/* An allocation failure is not fatal */
1913 		cte = kzalloc(sizeof(*cte), GFP_KERNEL_ACCOUNT);
1914 		if (WARN_ON(!cte))
1915 			break;
1916 
1917 		INIT_LIST_HEAD(&cte->entry);
1918 		list_add(&cte->entry, &dist->lpi_translation_cache);
1919 	}
1920 }
1921 
vgic_lpi_translation_cache_destroy(struct kvm * kvm)1922 void vgic_lpi_translation_cache_destroy(struct kvm *kvm)
1923 {
1924 	struct vgic_dist *dist = &kvm->arch.vgic;
1925 	struct vgic_translation_cache_entry *cte, *tmp;
1926 
1927 	vgic_its_invalidate_cache(kvm);
1928 
1929 	list_for_each_entry_safe(cte, tmp,
1930 				 &dist->lpi_translation_cache, entry) {
1931 		list_del(&cte->entry);
1932 		kfree(cte);
1933 	}
1934 }
1935 
1936 #define INITIAL_BASER_VALUE						  \
1937 	(GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)		| \
1938 	 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner)		| \
1939 	 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)		| \
1940 	 GITS_BASER_PAGE_SIZE_64K)
1941 
1942 #define INITIAL_PROPBASER_VALUE						  \
1943 	(GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)		| \
1944 	 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner)	| \
1945 	 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
1946 
vgic_its_create(struct kvm_device * dev,u32 type)1947 static int vgic_its_create(struct kvm_device *dev, u32 type)
1948 {
1949 	int ret;
1950 	struct vgic_its *its;
1951 
1952 	if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
1953 		return -ENODEV;
1954 
1955 	its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL_ACCOUNT);
1956 	if (!its)
1957 		return -ENOMEM;
1958 
1959 	mutex_lock(&dev->kvm->arch.config_lock);
1960 
1961 	if (vgic_initialized(dev->kvm)) {
1962 		ret = vgic_v4_init(dev->kvm);
1963 		if (ret < 0) {
1964 			mutex_unlock(&dev->kvm->arch.config_lock);
1965 			kfree(its);
1966 			return ret;
1967 		}
1968 
1969 		vgic_lpi_translation_cache_init(dev->kvm);
1970 	}
1971 
1972 	mutex_init(&its->its_lock);
1973 	mutex_init(&its->cmd_lock);
1974 
1975 	/* Yep, even more trickery for lock ordering... */
1976 #ifdef CONFIG_LOCKDEP
1977 	mutex_lock(&its->cmd_lock);
1978 	mutex_lock(&its->its_lock);
1979 	mutex_unlock(&its->its_lock);
1980 	mutex_unlock(&its->cmd_lock);
1981 #endif
1982 
1983 	its->vgic_its_base = VGIC_ADDR_UNDEF;
1984 
1985 	INIT_LIST_HEAD(&its->device_list);
1986 	INIT_LIST_HEAD(&its->collection_list);
1987 
1988 	dev->kvm->arch.vgic.msis_require_devid = true;
1989 	dev->kvm->arch.vgic.has_its = true;
1990 	its->enabled = false;
1991 	its->dev = dev;
1992 
1993 	its->baser_device_table = INITIAL_BASER_VALUE			|
1994 		((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
1995 	its->baser_coll_table = INITIAL_BASER_VALUE |
1996 		((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
1997 	dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
1998 
1999 	dev->private = its;
2000 
2001 	ret = vgic_its_set_abi(its, NR_ITS_ABIS - 1);
2002 
2003 	mutex_unlock(&dev->kvm->arch.config_lock);
2004 
2005 	return ret;
2006 }
2007 
vgic_its_destroy(struct kvm_device * kvm_dev)2008 static void vgic_its_destroy(struct kvm_device *kvm_dev)
2009 {
2010 	struct kvm *kvm = kvm_dev->kvm;
2011 	struct vgic_its *its = kvm_dev->private;
2012 
2013 	mutex_lock(&its->its_lock);
2014 
2015 	vgic_its_free_device_list(kvm, its);
2016 	vgic_its_free_collection_list(kvm, its);
2017 
2018 	mutex_unlock(&its->its_lock);
2019 	kfree(its);
2020 	kfree(kvm_dev);/* alloc by kvm_ioctl_create_device, free by .destroy */
2021 }
2022 
vgic_its_has_attr_regs(struct kvm_device * dev,struct kvm_device_attr * attr)2023 static int vgic_its_has_attr_regs(struct kvm_device *dev,
2024 				  struct kvm_device_attr *attr)
2025 {
2026 	const struct vgic_register_region *region;
2027 	gpa_t offset = attr->attr;
2028 	int align;
2029 
2030 	align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7;
2031 
2032 	if (offset & align)
2033 		return -EINVAL;
2034 
2035 	region = vgic_find_mmio_region(its_registers,
2036 				       ARRAY_SIZE(its_registers),
2037 				       offset);
2038 	if (!region)
2039 		return -ENXIO;
2040 
2041 	return 0;
2042 }
2043 
vgic_its_attr_regs_access(struct kvm_device * dev,struct kvm_device_attr * attr,u64 * reg,bool is_write)2044 static int vgic_its_attr_regs_access(struct kvm_device *dev,
2045 				     struct kvm_device_attr *attr,
2046 				     u64 *reg, bool is_write)
2047 {
2048 	const struct vgic_register_region *region;
2049 	struct vgic_its *its;
2050 	gpa_t addr, offset;
2051 	unsigned int len;
2052 	int align, ret = 0;
2053 
2054 	its = dev->private;
2055 	offset = attr->attr;
2056 
2057 	/*
2058 	 * Although the spec supports upper/lower 32-bit accesses to
2059 	 * 64-bit ITS registers, the userspace ABI requires 64-bit
2060 	 * accesses to all 64-bit wide registers. We therefore only
2061 	 * support 32-bit accesses to GITS_CTLR, GITS_IIDR and GITS ID
2062 	 * registers
2063 	 */
2064 	if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4))
2065 		align = 0x3;
2066 	else
2067 		align = 0x7;
2068 
2069 	if (offset & align)
2070 		return -EINVAL;
2071 
2072 	mutex_lock(&dev->kvm->lock);
2073 
2074 	if (!lock_all_vcpus(dev->kvm)) {
2075 		mutex_unlock(&dev->kvm->lock);
2076 		return -EBUSY;
2077 	}
2078 
2079 	mutex_lock(&dev->kvm->arch.config_lock);
2080 
2081 	if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
2082 		ret = -ENXIO;
2083 		goto out;
2084 	}
2085 
2086 	region = vgic_find_mmio_region(its_registers,
2087 				       ARRAY_SIZE(its_registers),
2088 				       offset);
2089 	if (!region) {
2090 		ret = -ENXIO;
2091 		goto out;
2092 	}
2093 
2094 	addr = its->vgic_its_base + offset;
2095 
2096 	len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
2097 
2098 	if (is_write) {
2099 		if (region->uaccess_its_write)
2100 			ret = region->uaccess_its_write(dev->kvm, its, addr,
2101 							len, *reg);
2102 		else
2103 			region->its_write(dev->kvm, its, addr, len, *reg);
2104 	} else {
2105 		*reg = region->its_read(dev->kvm, its, addr, len);
2106 	}
2107 out:
2108 	mutex_unlock(&dev->kvm->arch.config_lock);
2109 	unlock_all_vcpus(dev->kvm);
2110 	mutex_unlock(&dev->kvm->lock);
2111 	return ret;
2112 }
2113 
compute_next_devid_offset(struct list_head * h,struct its_device * dev)2114 static u32 compute_next_devid_offset(struct list_head *h,
2115 				     struct its_device *dev)
2116 {
2117 	struct its_device *next;
2118 	u32 next_offset;
2119 
2120 	if (list_is_last(&dev->dev_list, h))
2121 		return 0;
2122 	next = list_next_entry(dev, dev_list);
2123 	next_offset = next->device_id - dev->device_id;
2124 
2125 	return min_t(u32, next_offset, VITS_DTE_MAX_DEVID_OFFSET);
2126 }
2127 
compute_next_eventid_offset(struct list_head * h,struct its_ite * ite)2128 static u32 compute_next_eventid_offset(struct list_head *h, struct its_ite *ite)
2129 {
2130 	struct its_ite *next;
2131 	u32 next_offset;
2132 
2133 	if (list_is_last(&ite->ite_list, h))
2134 		return 0;
2135 	next = list_next_entry(ite, ite_list);
2136 	next_offset = next->event_id - ite->event_id;
2137 
2138 	return min_t(u32, next_offset, VITS_ITE_MAX_EVENTID_OFFSET);
2139 }
2140 
2141 /**
2142  * entry_fn_t - Callback called on a table entry restore path
2143  * @its: its handle
2144  * @id: id of the entry
2145  * @entry: pointer to the entry
2146  * @opaque: pointer to an opaque data
2147  *
2148  * Return: < 0 on error, 0 if last element was identified, id offset to next
2149  * element otherwise
2150  */
2151 typedef int (*entry_fn_t)(struct vgic_its *its, u32 id, void *entry,
2152 			  void *opaque);
2153 
2154 /**
2155  * scan_its_table - Scan a contiguous table in guest RAM and applies a function
2156  * to each entry
2157  *
2158  * @its: its handle
2159  * @base: base gpa of the table
2160  * @size: size of the table in bytes
2161  * @esz: entry size in bytes
2162  * @start_id: the ID of the first entry in the table
2163  * (non zero for 2d level tables)
2164  * @fn: function to apply on each entry
2165  *
2166  * Return: < 0 on error, 0 if last element was identified, 1 otherwise
2167  * (the last element may not be found on second level tables)
2168  */
scan_its_table(struct vgic_its * its,gpa_t base,int size,u32 esz,int start_id,entry_fn_t fn,void * opaque)2169 static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz,
2170 			  int start_id, entry_fn_t fn, void *opaque)
2171 {
2172 	struct kvm *kvm = its->dev->kvm;
2173 	unsigned long len = size;
2174 	int id = start_id;
2175 	gpa_t gpa = base;
2176 	char entry[ESZ_MAX];
2177 	int ret;
2178 
2179 	memset(entry, 0, esz);
2180 
2181 	while (true) {
2182 		int next_offset;
2183 		size_t byte_offset;
2184 
2185 		ret = kvm_read_guest_lock(kvm, gpa, entry, esz);
2186 		if (ret)
2187 			return ret;
2188 
2189 		next_offset = fn(its, id, entry, opaque);
2190 		if (next_offset <= 0)
2191 			return next_offset;
2192 
2193 		byte_offset = next_offset * esz;
2194 		if (byte_offset >= len)
2195 			break;
2196 
2197 		id += next_offset;
2198 		gpa += byte_offset;
2199 		len -= byte_offset;
2200 	}
2201 	return 1;
2202 }
2203 
2204 /**
2205  * vgic_its_save_ite - Save an interrupt translation entry at @gpa
2206  */
vgic_its_save_ite(struct vgic_its * its,struct its_device * dev,struct its_ite * ite,gpa_t gpa,int ite_esz)2207 static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
2208 			      struct its_ite *ite, gpa_t gpa, int ite_esz)
2209 {
2210 	struct kvm *kvm = its->dev->kvm;
2211 	u32 next_offset;
2212 	u64 val;
2213 
2214 	next_offset = compute_next_eventid_offset(&dev->itt_head, ite);
2215 	val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) |
2216 	       ((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) |
2217 		ite->collection->collection_id;
2218 	val = cpu_to_le64(val);
2219 	return vgic_write_guest_lock(kvm, gpa, &val, ite_esz);
2220 }
2221 
2222 /**
2223  * vgic_its_restore_ite - restore an interrupt translation entry
2224  * @event_id: id used for indexing
2225  * @ptr: pointer to the ITE entry
2226  * @opaque: pointer to the its_device
2227  */
vgic_its_restore_ite(struct vgic_its * its,u32 event_id,void * ptr,void * opaque)2228 static int vgic_its_restore_ite(struct vgic_its *its, u32 event_id,
2229 				void *ptr, void *opaque)
2230 {
2231 	struct its_device *dev = opaque;
2232 	struct its_collection *collection;
2233 	struct kvm *kvm = its->dev->kvm;
2234 	struct kvm_vcpu *vcpu = NULL;
2235 	u64 val;
2236 	u64 *p = (u64 *)ptr;
2237 	struct vgic_irq *irq;
2238 	u32 coll_id, lpi_id;
2239 	struct its_ite *ite;
2240 	u32 offset;
2241 
2242 	val = *p;
2243 
2244 	val = le64_to_cpu(val);
2245 
2246 	coll_id = val & KVM_ITS_ITE_ICID_MASK;
2247 	lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT;
2248 
2249 	if (!lpi_id)
2250 		return 1; /* invalid entry, no choice but to scan next entry */
2251 
2252 	if (lpi_id < VGIC_MIN_LPI)
2253 		return -EINVAL;
2254 
2255 	offset = val >> KVM_ITS_ITE_NEXT_SHIFT;
2256 	if (event_id + offset >= BIT_ULL(dev->num_eventid_bits))
2257 		return -EINVAL;
2258 
2259 	collection = find_collection(its, coll_id);
2260 	if (!collection)
2261 		return -EINVAL;
2262 
2263 	if (!vgic_its_check_event_id(its, dev, event_id))
2264 		return -EINVAL;
2265 
2266 	ite = vgic_its_alloc_ite(dev, collection, event_id);
2267 	if (IS_ERR(ite))
2268 		return PTR_ERR(ite);
2269 
2270 	if (its_is_collection_mapped(collection))
2271 		vcpu = kvm_get_vcpu(kvm, collection->target_addr);
2272 
2273 	irq = vgic_add_lpi(kvm, lpi_id, vcpu);
2274 	if (IS_ERR(irq)) {
2275 		its_free_ite(kvm, ite);
2276 		return PTR_ERR(irq);
2277 	}
2278 	ite->irq = irq;
2279 
2280 	return offset;
2281 }
2282 
vgic_its_ite_cmp(void * priv,const struct list_head * a,const struct list_head * b)2283 static int vgic_its_ite_cmp(void *priv, const struct list_head *a,
2284 			    const struct list_head *b)
2285 {
2286 	struct its_ite *itea = container_of(a, struct its_ite, ite_list);
2287 	struct its_ite *iteb = container_of(b, struct its_ite, ite_list);
2288 
2289 	if (itea->event_id < iteb->event_id)
2290 		return -1;
2291 	else
2292 		return 1;
2293 }
2294 
vgic_its_save_itt(struct vgic_its * its,struct its_device * device)2295 static int vgic_its_save_itt(struct vgic_its *its, struct its_device *device)
2296 {
2297 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2298 	gpa_t base = device->itt_addr;
2299 	struct its_ite *ite;
2300 	int ret;
2301 	int ite_esz = abi->ite_esz;
2302 
2303 	list_sort(NULL, &device->itt_head, vgic_its_ite_cmp);
2304 
2305 	list_for_each_entry(ite, &device->itt_head, ite_list) {
2306 		gpa_t gpa = base + ite->event_id * ite_esz;
2307 
2308 		/*
2309 		 * If an LPI carries the HW bit, this means that this
2310 		 * interrupt is controlled by GICv4, and we do not
2311 		 * have direct access to that state without GICv4.1.
2312 		 * Let's simply fail the save operation...
2313 		 */
2314 		if (ite->irq->hw && !kvm_vgic_global_state.has_gicv4_1)
2315 			return -EACCES;
2316 
2317 		ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz);
2318 		if (ret)
2319 			return ret;
2320 	}
2321 	return 0;
2322 }
2323 
2324 /**
2325  * vgic_its_restore_itt - restore the ITT of a device
2326  *
2327  * @its: its handle
2328  * @dev: device handle
2329  *
2330  * Return 0 on success, < 0 on error
2331  */
vgic_its_restore_itt(struct vgic_its * its,struct its_device * dev)2332 static int vgic_its_restore_itt(struct vgic_its *its, struct its_device *dev)
2333 {
2334 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2335 	gpa_t base = dev->itt_addr;
2336 	int ret;
2337 	int ite_esz = abi->ite_esz;
2338 	size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz;
2339 
2340 	ret = scan_its_table(its, base, max_size, ite_esz, 0,
2341 			     vgic_its_restore_ite, dev);
2342 
2343 	/* scan_its_table returns +1 if all ITEs are invalid */
2344 	if (ret > 0)
2345 		ret = 0;
2346 
2347 	return ret;
2348 }
2349 
2350 /**
2351  * vgic_its_save_dte - Save a device table entry at a given GPA
2352  *
2353  * @its: ITS handle
2354  * @dev: ITS device
2355  * @ptr: GPA
2356  */
vgic_its_save_dte(struct vgic_its * its,struct its_device * dev,gpa_t ptr,int dte_esz)2357 static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
2358 			     gpa_t ptr, int dte_esz)
2359 {
2360 	struct kvm *kvm = its->dev->kvm;
2361 	u64 val, itt_addr_field;
2362 	u32 next_offset;
2363 
2364 	itt_addr_field = dev->itt_addr >> 8;
2365 	next_offset = compute_next_devid_offset(&its->device_list, dev);
2366 	val = (1ULL << KVM_ITS_DTE_VALID_SHIFT |
2367 	       ((u64)next_offset << KVM_ITS_DTE_NEXT_SHIFT) |
2368 	       (itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) |
2369 		(dev->num_eventid_bits - 1));
2370 	val = cpu_to_le64(val);
2371 	return vgic_write_guest_lock(kvm, ptr, &val, dte_esz);
2372 }
2373 
2374 /**
2375  * vgic_its_restore_dte - restore a device table entry
2376  *
2377  * @its: its handle
2378  * @id: device id the DTE corresponds to
2379  * @ptr: kernel VA where the 8 byte DTE is located
2380  * @opaque: unused
2381  *
2382  * Return: < 0 on error, 0 if the dte is the last one, id offset to the
2383  * next dte otherwise
2384  */
vgic_its_restore_dte(struct vgic_its * its,u32 id,void * ptr,void * opaque)2385 static int vgic_its_restore_dte(struct vgic_its *its, u32 id,
2386 				void *ptr, void *opaque)
2387 {
2388 	struct its_device *dev;
2389 	u64 baser = its->baser_device_table;
2390 	gpa_t itt_addr;
2391 	u8 num_eventid_bits;
2392 	u64 entry = *(u64 *)ptr;
2393 	bool valid;
2394 	u32 offset;
2395 	int ret;
2396 
2397 	entry = le64_to_cpu(entry);
2398 
2399 	valid = entry >> KVM_ITS_DTE_VALID_SHIFT;
2400 	num_eventid_bits = (entry & KVM_ITS_DTE_SIZE_MASK) + 1;
2401 	itt_addr = ((entry & KVM_ITS_DTE_ITTADDR_MASK)
2402 			>> KVM_ITS_DTE_ITTADDR_SHIFT) << 8;
2403 
2404 	if (!valid)
2405 		return 1;
2406 
2407 	/* dte entry is valid */
2408 	offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT;
2409 
2410 	if (!vgic_its_check_id(its, baser, id, NULL))
2411 		return -EINVAL;
2412 
2413 	dev = vgic_its_alloc_device(its, id, itt_addr, num_eventid_bits);
2414 	if (IS_ERR(dev))
2415 		return PTR_ERR(dev);
2416 
2417 	ret = vgic_its_restore_itt(its, dev);
2418 	if (ret) {
2419 		vgic_its_free_device(its->dev->kvm, dev);
2420 		return ret;
2421 	}
2422 
2423 	return offset;
2424 }
2425 
vgic_its_device_cmp(void * priv,const struct list_head * a,const struct list_head * b)2426 static int vgic_its_device_cmp(void *priv, const struct list_head *a,
2427 			       const struct list_head *b)
2428 {
2429 	struct its_device *deva = container_of(a, struct its_device, dev_list);
2430 	struct its_device *devb = container_of(b, struct its_device, dev_list);
2431 
2432 	if (deva->device_id < devb->device_id)
2433 		return -1;
2434 	else
2435 		return 1;
2436 }
2437 
2438 /**
2439  * vgic_its_save_device_tables - Save the device table and all ITT
2440  * into guest RAM
2441  *
2442  * L1/L2 handling is hidden by vgic_its_check_id() helper which directly
2443  * returns the GPA of the device entry
2444  */
vgic_its_save_device_tables(struct vgic_its * its)2445 static int vgic_its_save_device_tables(struct vgic_its *its)
2446 {
2447 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2448 	u64 baser = its->baser_device_table;
2449 	struct its_device *dev;
2450 	int dte_esz = abi->dte_esz;
2451 
2452 	if (!(baser & GITS_BASER_VALID))
2453 		return 0;
2454 
2455 	list_sort(NULL, &its->device_list, vgic_its_device_cmp);
2456 
2457 	list_for_each_entry(dev, &its->device_list, dev_list) {
2458 		int ret;
2459 		gpa_t eaddr;
2460 
2461 		if (!vgic_its_check_id(its, baser,
2462 				       dev->device_id, &eaddr))
2463 			return -EINVAL;
2464 
2465 		ret = vgic_its_save_itt(its, dev);
2466 		if (ret)
2467 			return ret;
2468 
2469 		ret = vgic_its_save_dte(its, dev, eaddr, dte_esz);
2470 		if (ret)
2471 			return ret;
2472 	}
2473 	return 0;
2474 }
2475 
2476 /**
2477  * handle_l1_dte - callback used for L1 device table entries (2 stage case)
2478  *
2479  * @its: its handle
2480  * @id: index of the entry in the L1 table
2481  * @addr: kernel VA
2482  * @opaque: unused
2483  *
2484  * L1 table entries are scanned by steps of 1 entry
2485  * Return < 0 if error, 0 if last dte was found when scanning the L2
2486  * table, +1 otherwise (meaning next L1 entry must be scanned)
2487  */
handle_l1_dte(struct vgic_its * its,u32 id,void * addr,void * opaque)2488 static int handle_l1_dte(struct vgic_its *its, u32 id, void *addr,
2489 			 void *opaque)
2490 {
2491 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2492 	int l2_start_id = id * (SZ_64K / abi->dte_esz);
2493 	u64 entry = *(u64 *)addr;
2494 	int dte_esz = abi->dte_esz;
2495 	gpa_t gpa;
2496 	int ret;
2497 
2498 	entry = le64_to_cpu(entry);
2499 
2500 	if (!(entry & KVM_ITS_L1E_VALID_MASK))
2501 		return 1;
2502 
2503 	gpa = entry & KVM_ITS_L1E_ADDR_MASK;
2504 
2505 	ret = scan_its_table(its, gpa, SZ_64K, dte_esz,
2506 			     l2_start_id, vgic_its_restore_dte, NULL);
2507 
2508 	return ret;
2509 }
2510 
2511 /**
2512  * vgic_its_restore_device_tables - Restore the device table and all ITT
2513  * from guest RAM to internal data structs
2514  */
vgic_its_restore_device_tables(struct vgic_its * its)2515 static int vgic_its_restore_device_tables(struct vgic_its *its)
2516 {
2517 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2518 	u64 baser = its->baser_device_table;
2519 	int l1_esz, ret;
2520 	int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2521 	gpa_t l1_gpa;
2522 
2523 	if (!(baser & GITS_BASER_VALID))
2524 		return 0;
2525 
2526 	l1_gpa = GITS_BASER_ADDR_48_to_52(baser);
2527 
2528 	if (baser & GITS_BASER_INDIRECT) {
2529 		l1_esz = GITS_LVL1_ENTRY_SIZE;
2530 		ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2531 				     handle_l1_dte, NULL);
2532 	} else {
2533 		l1_esz = abi->dte_esz;
2534 		ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2535 				     vgic_its_restore_dte, NULL);
2536 	}
2537 
2538 	/* scan_its_table returns +1 if all entries are invalid */
2539 	if (ret > 0)
2540 		ret = 0;
2541 
2542 	if (ret < 0)
2543 		vgic_its_free_device_list(its->dev->kvm, its);
2544 
2545 	return ret;
2546 }
2547 
vgic_its_save_cte(struct vgic_its * its,struct its_collection * collection,gpa_t gpa,int esz)2548 static int vgic_its_save_cte(struct vgic_its *its,
2549 			     struct its_collection *collection,
2550 			     gpa_t gpa, int esz)
2551 {
2552 	u64 val;
2553 
2554 	val = (1ULL << KVM_ITS_CTE_VALID_SHIFT |
2555 	       ((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) |
2556 	       collection->collection_id);
2557 	val = cpu_to_le64(val);
2558 	return vgic_write_guest_lock(its->dev->kvm, gpa, &val, esz);
2559 }
2560 
2561 /*
2562  * Restore a collection entry into the ITS collection table.
2563  * Return +1 on success, 0 if the entry was invalid (which should be
2564  * interpreted as end-of-table), and a negative error value for generic errors.
2565  */
vgic_its_restore_cte(struct vgic_its * its,gpa_t gpa,int esz)2566 static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
2567 {
2568 	struct its_collection *collection;
2569 	struct kvm *kvm = its->dev->kvm;
2570 	u32 target_addr, coll_id;
2571 	u64 val;
2572 	int ret;
2573 
2574 	BUG_ON(esz > sizeof(val));
2575 	ret = kvm_read_guest_lock(kvm, gpa, &val, esz);
2576 	if (ret)
2577 		return ret;
2578 	val = le64_to_cpu(val);
2579 	if (!(val & KVM_ITS_CTE_VALID_MASK))
2580 		return 0;
2581 
2582 	target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT);
2583 	coll_id = val & KVM_ITS_CTE_ICID_MASK;
2584 
2585 	if (target_addr != COLLECTION_NOT_MAPPED &&
2586 	    target_addr >= atomic_read(&kvm->online_vcpus))
2587 		return -EINVAL;
2588 
2589 	collection = find_collection(its, coll_id);
2590 	if (collection)
2591 		return -EEXIST;
2592 
2593 	if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
2594 		return -EINVAL;
2595 
2596 	ret = vgic_its_alloc_collection(its, &collection, coll_id);
2597 	if (ret)
2598 		return ret;
2599 	collection->target_addr = target_addr;
2600 	return 1;
2601 }
2602 
2603 /**
2604  * vgic_its_save_collection_table - Save the collection table into
2605  * guest RAM
2606  */
vgic_its_save_collection_table(struct vgic_its * its)2607 static int vgic_its_save_collection_table(struct vgic_its *its)
2608 {
2609 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2610 	u64 baser = its->baser_coll_table;
2611 	gpa_t gpa = GITS_BASER_ADDR_48_to_52(baser);
2612 	struct its_collection *collection;
2613 	u64 val;
2614 	size_t max_size, filled = 0;
2615 	int ret, cte_esz = abi->cte_esz;
2616 
2617 	if (!(baser & GITS_BASER_VALID))
2618 		return 0;
2619 
2620 	max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2621 
2622 	list_for_each_entry(collection, &its->collection_list, coll_list) {
2623 		ret = vgic_its_save_cte(its, collection, gpa, cte_esz);
2624 		if (ret)
2625 			return ret;
2626 		gpa += cte_esz;
2627 		filled += cte_esz;
2628 	}
2629 
2630 	if (filled == max_size)
2631 		return 0;
2632 
2633 	/*
2634 	 * table is not fully filled, add a last dummy element
2635 	 * with valid bit unset
2636 	 */
2637 	val = 0;
2638 	BUG_ON(cte_esz > sizeof(val));
2639 	ret = vgic_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz);
2640 	return ret;
2641 }
2642 
2643 /**
2644  * vgic_its_restore_collection_table - reads the collection table
2645  * in guest memory and restores the ITS internal state. Requires the
2646  * BASER registers to be restored before.
2647  */
vgic_its_restore_collection_table(struct vgic_its * its)2648 static int vgic_its_restore_collection_table(struct vgic_its *its)
2649 {
2650 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2651 	u64 baser = its->baser_coll_table;
2652 	int cte_esz = abi->cte_esz;
2653 	size_t max_size, read = 0;
2654 	gpa_t gpa;
2655 	int ret;
2656 
2657 	if (!(baser & GITS_BASER_VALID))
2658 		return 0;
2659 
2660 	gpa = GITS_BASER_ADDR_48_to_52(baser);
2661 
2662 	max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2663 
2664 	while (read < max_size) {
2665 		ret = vgic_its_restore_cte(its, gpa, cte_esz);
2666 		if (ret <= 0)
2667 			break;
2668 		gpa += cte_esz;
2669 		read += cte_esz;
2670 	}
2671 
2672 	if (ret > 0)
2673 		return 0;
2674 
2675 	if (ret < 0)
2676 		vgic_its_free_collection_list(its->dev->kvm, its);
2677 
2678 	return ret;
2679 }
2680 
2681 /**
2682  * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
2683  * according to v0 ABI
2684  */
vgic_its_save_tables_v0(struct vgic_its * its)2685 static int vgic_its_save_tables_v0(struct vgic_its *its)
2686 {
2687 	int ret;
2688 
2689 	ret = vgic_its_save_device_tables(its);
2690 	if (ret)
2691 		return ret;
2692 
2693 	return vgic_its_save_collection_table(its);
2694 }
2695 
2696 /**
2697  * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM
2698  * to internal data structs according to V0 ABI
2699  *
2700  */
vgic_its_restore_tables_v0(struct vgic_its * its)2701 static int vgic_its_restore_tables_v0(struct vgic_its *its)
2702 {
2703 	int ret;
2704 
2705 	ret = vgic_its_restore_collection_table(its);
2706 	if (ret)
2707 		return ret;
2708 
2709 	ret = vgic_its_restore_device_tables(its);
2710 	if (ret)
2711 		vgic_its_free_collection_list(its->dev->kvm, its);
2712 	return ret;
2713 }
2714 
vgic_its_commit_v0(struct vgic_its * its)2715 static int vgic_its_commit_v0(struct vgic_its *its)
2716 {
2717 	const struct vgic_its_abi *abi;
2718 
2719 	abi = vgic_its_get_abi(its);
2720 	its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2721 	its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2722 
2723 	its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
2724 					<< GITS_BASER_ENTRY_SIZE_SHIFT);
2725 
2726 	its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
2727 					<< GITS_BASER_ENTRY_SIZE_SHIFT);
2728 	return 0;
2729 }
2730 
vgic_its_reset(struct kvm * kvm,struct vgic_its * its)2731 static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
2732 {
2733 	/* We need to keep the ABI specific field values */
2734 	its->baser_coll_table &= ~GITS_BASER_VALID;
2735 	its->baser_device_table &= ~GITS_BASER_VALID;
2736 	its->cbaser = 0;
2737 	its->creadr = 0;
2738 	its->cwriter = 0;
2739 	its->enabled = 0;
2740 	vgic_its_free_device_list(kvm, its);
2741 	vgic_its_free_collection_list(kvm, its);
2742 }
2743 
vgic_its_has_attr(struct kvm_device * dev,struct kvm_device_attr * attr)2744 static int vgic_its_has_attr(struct kvm_device *dev,
2745 			     struct kvm_device_attr *attr)
2746 {
2747 	switch (attr->group) {
2748 	case KVM_DEV_ARM_VGIC_GRP_ADDR:
2749 		switch (attr->attr) {
2750 		case KVM_VGIC_ITS_ADDR_TYPE:
2751 			return 0;
2752 		}
2753 		break;
2754 	case KVM_DEV_ARM_VGIC_GRP_CTRL:
2755 		switch (attr->attr) {
2756 		case KVM_DEV_ARM_VGIC_CTRL_INIT:
2757 			return 0;
2758 		case KVM_DEV_ARM_ITS_CTRL_RESET:
2759 			return 0;
2760 		case KVM_DEV_ARM_ITS_SAVE_TABLES:
2761 			return 0;
2762 		case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2763 			return 0;
2764 		}
2765 		break;
2766 	case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
2767 		return vgic_its_has_attr_regs(dev, attr);
2768 	}
2769 	return -ENXIO;
2770 }
2771 
vgic_its_ctrl(struct kvm * kvm,struct vgic_its * its,u64 attr)2772 static int vgic_its_ctrl(struct kvm *kvm, struct vgic_its *its, u64 attr)
2773 {
2774 	const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2775 	int ret = 0;
2776 
2777 	if (attr == KVM_DEV_ARM_VGIC_CTRL_INIT) /* Nothing to do */
2778 		return 0;
2779 
2780 	mutex_lock(&kvm->lock);
2781 
2782 	if (!lock_all_vcpus(kvm)) {
2783 		mutex_unlock(&kvm->lock);
2784 		return -EBUSY;
2785 	}
2786 
2787 	mutex_lock(&kvm->arch.config_lock);
2788 	mutex_lock(&its->its_lock);
2789 
2790 	switch (attr) {
2791 	case KVM_DEV_ARM_ITS_CTRL_RESET:
2792 		vgic_its_reset(kvm, its);
2793 		break;
2794 	case KVM_DEV_ARM_ITS_SAVE_TABLES:
2795 		ret = abi->save_tables(its);
2796 		break;
2797 	case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2798 		ret = abi->restore_tables(its);
2799 		break;
2800 	}
2801 
2802 	mutex_unlock(&its->its_lock);
2803 	mutex_unlock(&kvm->arch.config_lock);
2804 	unlock_all_vcpus(kvm);
2805 	mutex_unlock(&kvm->lock);
2806 	return ret;
2807 }
2808 
2809 /*
2810  * kvm_arch_allow_write_without_running_vcpu - allow writing guest memory
2811  * without the running VCPU when dirty ring is enabled.
2812  *
2813  * The running VCPU is required to track dirty guest pages when dirty ring
2814  * is enabled. Otherwise, the backup bitmap should be used to track the
2815  * dirty guest pages. When vgic/its tables are being saved, the backup
2816  * bitmap is used to track the dirty guest pages due to the missed running
2817  * VCPU in the period.
2818  */
kvm_arch_allow_write_without_running_vcpu(struct kvm * kvm)2819 bool kvm_arch_allow_write_without_running_vcpu(struct kvm *kvm)
2820 {
2821 	struct vgic_dist *dist = &kvm->arch.vgic;
2822 
2823 	return dist->table_write_in_progress;
2824 }
2825 
vgic_its_set_attr(struct kvm_device * dev,struct kvm_device_attr * attr)2826 static int vgic_its_set_attr(struct kvm_device *dev,
2827 			     struct kvm_device_attr *attr)
2828 {
2829 	struct vgic_its *its = dev->private;
2830 	int ret;
2831 
2832 	switch (attr->group) {
2833 	case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2834 		u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2835 		unsigned long type = (unsigned long)attr->attr;
2836 		u64 addr;
2837 
2838 		if (type != KVM_VGIC_ITS_ADDR_TYPE)
2839 			return -ENODEV;
2840 
2841 		if (copy_from_user(&addr, uaddr, sizeof(addr)))
2842 			return -EFAULT;
2843 
2844 		ret = vgic_check_iorange(dev->kvm, its->vgic_its_base,
2845 					 addr, SZ_64K, KVM_VGIC_V3_ITS_SIZE);
2846 		if (ret)
2847 			return ret;
2848 
2849 		return vgic_register_its_iodev(dev->kvm, its, addr);
2850 	}
2851 	case KVM_DEV_ARM_VGIC_GRP_CTRL:
2852 		return vgic_its_ctrl(dev->kvm, its, attr->attr);
2853 	case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2854 		u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2855 		u64 reg;
2856 
2857 		if (get_user(reg, uaddr))
2858 			return -EFAULT;
2859 
2860 		return vgic_its_attr_regs_access(dev, attr, &reg, true);
2861 	}
2862 	}
2863 	return -ENXIO;
2864 }
2865 
vgic_its_get_attr(struct kvm_device * dev,struct kvm_device_attr * attr)2866 static int vgic_its_get_attr(struct kvm_device *dev,
2867 			     struct kvm_device_attr *attr)
2868 {
2869 	switch (attr->group) {
2870 	case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2871 		struct vgic_its *its = dev->private;
2872 		u64 addr = its->vgic_its_base;
2873 		u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2874 		unsigned long type = (unsigned long)attr->attr;
2875 
2876 		if (type != KVM_VGIC_ITS_ADDR_TYPE)
2877 			return -ENODEV;
2878 
2879 		if (copy_to_user(uaddr, &addr, sizeof(addr)))
2880 			return -EFAULT;
2881 		break;
2882 	}
2883 	case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2884 		u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2885 		u64 reg;
2886 		int ret;
2887 
2888 		ret = vgic_its_attr_regs_access(dev, attr, &reg, false);
2889 		if (ret)
2890 			return ret;
2891 		return put_user(reg, uaddr);
2892 	}
2893 	default:
2894 		return -ENXIO;
2895 	}
2896 
2897 	return 0;
2898 }
2899 
2900 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
2901 	.name = "kvm-arm-vgic-its",
2902 	.create = vgic_its_create,
2903 	.destroy = vgic_its_destroy,
2904 	.set_attr = vgic_its_set_attr,
2905 	.get_attr = vgic_its_get_attr,
2906 	.has_attr = vgic_its_has_attr,
2907 };
2908 
kvm_vgic_register_its_device(void)2909 int kvm_vgic_register_its_device(void)
2910 {
2911 	return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
2912 				       KVM_DEV_TYPE_ARM_VGIC_ITS);
2913 }
2914