xref: /openbmc/linux/arch/nios2/include/asm/registers.h (revision 4cce60f1)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
4  */
5 
6 #ifndef _ASM_NIOS2_REGISTERS_H
7 #define _ASM_NIOS2_REGISTERS_H
8 
9 #ifndef __ASSEMBLY__
10 #include <asm/cpuinfo.h>
11 #endif
12 
13 /* control register numbers */
14 #define CTL_FSTATUS	0
15 #define CTL_ESTATUS	1
16 #define CTL_BSTATUS	2
17 #define CTL_IENABLE	3
18 #define CTL_IPENDING	4
19 #define CTL_CPUID	5
20 #define CTL_RSV1	6
21 #define CTL_EXCEPTION	7
22 #define CTL_PTEADDR	8
23 #define CTL_TLBACC	9
24 #define CTL_TLBMISC	10
25 #define CTL_RSV2	11
26 #define CTL_BADADDR	12
27 #define CTL_CONFIG	13
28 #define CTL_MPUBASE	14
29 #define CTL_MPUACC	15
30 
31 /* access control registers using GCC builtins */
32 #define RDCTL(r)	__builtin_rdctl(r)
33 #define WRCTL(r, v)	__builtin_wrctl(r, v)
34 
35 /* status register bits */
36 #define STATUS_PIE	(1 << 0)	/* processor interrupt enable */
37 #define STATUS_U	(1 << 1)	/* user mode */
38 #define STATUS_EH	(1 << 2)	/* Exception mode */
39 
40 /* estatus register bits */
41 #define ESTATUS_EPIE	(1 << 0)	/* processor interrupt enable */
42 #define ESTATUS_EU	(1 << 1)	/* user mode */
43 #define ESTATUS_EH	(1 << 2)	/* Exception mode */
44 
45 /* tlbmisc register bits */
46 #define TLBMISC_PID_SHIFT	4
47 #ifndef __ASSEMBLY__
48 #define TLBMISC_PID_MASK	((1UL << cpuinfo.tlb_pid_num_bits) - 1)
49 #endif
50 #define TLBMISC_WAY_MASK	0xf
51 #define TLBMISC_WAY_SHIFT	20
52 
53 #define TLBMISC_PID	(TLBMISC_PID_MASK << TLBMISC_PID_SHIFT)	/* TLB PID */
54 #define TLBMISC_WE	(1 << 18)	/* TLB write enable */
55 #define TLBMISC_RD	(1 << 19)	/* TLB read */
56 #define TLBMISC_WAY	(TLBMISC_WAY_MASK << TLBMISC_WAY_SHIFT) /* TLB way */
57 
58 #endif /* _ASM_NIOS2_REGISTERS_H */
59