1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
4  */
5 
6 #include <asm/arch/clock.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <linux/errno.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/video.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/io.h>
18 #include <asm/arch/sys_proto.h>
19 #include <spl.h>
20 #include <netdev.h>
21 #include <miiphy.h>
22 #include <micrel.h>
23 
24 #include <common.h>
25 #include <malloc.h>
26 #include <fuse.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
31 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
32 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
33 
34 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
35 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
36 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
37 
38 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
39 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
40 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
41 
42 #define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
43 				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44 
45 static iomux_v3_cfg_t const uart1_pads[] = {
46 	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
47 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
48 };
49 
50 static iomux_v3_cfg_t const gpios_pads[] = {
51 	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
52 };
53 
54 static iomux_v3_cfg_t const usdhc2_pads[] = {
55 	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
56 	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
62 };
63 
64 static iomux_v3_cfg_t const enet_pads[] = {
65 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
78 						MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
80 						MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
82 						MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
84 };
85 
86 iomux_v3_cfg_t const enet_pads1[] = {
87 	/* pin 35 - 1 (PHY_AD2) on reset */
88 	IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30	| MUX_PAD_CTRL(NO_PAD_CTRL)),
89 	/* pin 32 - 1 - (MODE0) all */
90 	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
91 	/* pin 31 - 1 - (MODE1) all */
92 	IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27	| MUX_PAD_CTRL(NO_PAD_CTRL)),
93 	/* pin 28 - 1 - (MODE2) all */
94 	IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28	| MUX_PAD_CTRL(NO_PAD_CTRL)),
95 	/* pin 27 - 1 - (MODE3) all */
96 	IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29	| MUX_PAD_CTRL(NO_PAD_CTRL)),
97 	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
98 	IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL)),
99 	/* pin 42 PHY nRST */
100 	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 };
102 
mx6_rgmii_rework(struct phy_device * phydev)103 static int mx6_rgmii_rework(struct phy_device *phydev)
104 {
105 
106 	/* min rx data delay */
107 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
108 				   0x0);
109 	/* min tx data delay */
110 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
111 				   0x0);
112 	/* max rx/tx clock delay, min rx/tx control */
113 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
114 				   0xf0f0);
115 
116 	return 0;
117 }
118 
board_phy_config(struct phy_device * phydev)119 int board_phy_config(struct phy_device *phydev)
120 {
121 	mx6_rgmii_rework(phydev);
122 
123 	if (phydev->drv->config)
124 		return phydev->drv->config(phydev);
125 
126 	return 0;
127 }
128 
129 #define ENET_NRST IMX_GPIO_NR(1, 25)
130 
setup_iomux_enet(void)131 void setup_iomux_enet(void)
132 {
133 	SETUP_IOMUX_PADS(enet_pads);
134 
135 }
136 
board_eth_init(bd_t * bis)137 int board_eth_init(bd_t *bis)
138 {
139 	uint32_t base = IMX_FEC_BASE;
140 	struct mii_dev *bus = NULL;
141 	struct phy_device *phydev = NULL;
142 	int ret;
143 
144 	setup_iomux_enet();
145 
146 	bus = fec_get_miibus(base, -1);
147 	if (!bus)
148 		return -EINVAL;
149 	/* scan phy */
150 	phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
151 					PHY_INTERFACE_MODE_RGMII);
152 
153 	if (!phydev) {
154 		ret = -EINVAL;
155 		goto free_bus;
156 	}
157 	ret  = fec_probe(bis, -1, base, bus, phydev);
158 	if (ret)
159 		goto free_phydev;
160 
161 	return 0;
162 
163 free_phydev:
164 	free(phydev);
165 free_bus:
166 	free(bus);
167 	return ret;
168 }
169 
board_early_init_f(void)170 int board_early_init_f(void)
171 {
172 	SETUP_IOMUX_PADS(uart1_pads);
173 
174 	return 0;
175 }
176 
board_init(void)177 int board_init(void)
178 {
179 	/* Address of boot parameters */
180 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
181 
182 	/* Take in reset the ATMega processor */
183 	SETUP_IOMUX_PADS(gpios_pads);
184 	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
185 
186 	return 0;
187 }
188 
dram_init(void)189 int dram_init(void)
190 {
191 	gd->ram_size = imx_ddr_size();
192 
193 	return 0;
194 }
195 
196 struct fsl_esdhc_cfg usdhc_cfg[1] = {
197 	{USDHC2_BASE_ADDR, 0},
198 };
199 
200 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 0)
board_mmc_getcd(struct mmc * mmc)201 int board_mmc_getcd(struct mmc *mmc)
202 {
203 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
204 	int ret = 0;
205 
206 	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
207 		ret = 1;
208 
209 	return ret;
210 }
211 
board_mmc_init(bd_t * bis)212 int board_mmc_init(bd_t *bis)
213 {
214 	int ret;
215 
216 	SETUP_IOMUX_PADS(usdhc2_pads);
217 	gpio_direction_input(USDHC2_CD_GPIO);
218 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
219 	usdhc_cfg[0].max_bus_width = 4;
220 
221 	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
222 	if (ret) {
223 		printf("Warning: failed to initialize mmc dev \n");
224 		return ret;
225 	}
226 
227 	return 0;
228 }
229 
230 #if defined(CONFIG_SPL_BUILD)
231 #include <asm/arch/mx6-ddr.h>
232 
233 /*
234  * Driving strength:
235  *   0x30 == 40 Ohm
236  *   0x28 == 48 Ohm
237  */
238 #define IMX6SDL_DRIVE_STRENGTH	0x230
239 
240 
241 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
242 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
243 	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
244 	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
245 	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
246 	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
247 	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
248 	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
249 	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
250 	.dram_sdba2 = 0x00000000,
251 	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
252 	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
253 	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
254 	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
255 	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
256 	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
257 	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
258 	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
259 	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
260 	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
261 	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
262 	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
263 	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
264 	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
265 	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
266 	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
267 	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
268 	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
269 };
270 
271 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
272 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
273 	.grp_ddr_type = 0x000c0000,
274 	.grp_ddrmode_ctl = 0x00020000,
275 	.grp_ddrpke = 0x00000000,
276 	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
277 	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
278 	.grp_ddrmode = 0x00020000,
279 	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
280 	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
281 	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
282 	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
283 	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
284 	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
285 	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
286 	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
287 };
288 
289 /* MT41K128M16JT-125 */
290 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
291 	/* quad = 1066, duallite = 800 */
292 	.mem_speed = 1066,
293 	.density = 2,
294 	.width = 16,
295 	.banks = 8,
296 	.rowaddr = 14,
297 	.coladdr = 10,
298 	.pagesz = 2,
299 	.trcd = 1375,
300 	.trcmin = 4875,
301 	.trasmin = 3500,
302 	.SRT = 0,
303 };
304 
305 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
306 	.p0_mpwldectrl0 = 0x0043004E,
307 	.p0_mpwldectrl1 = 0x003D003F,
308 	.p1_mpwldectrl0 = 0x00230021,
309 	.p1_mpwldectrl1 = 0x0028003E,
310 	.p0_mpdgctrl0 = 0x42580250,
311 	.p0_mpdgctrl1 = 0x0238023C,
312 	.p1_mpdgctrl0 = 0x422C0238,
313 	.p1_mpdgctrl1 = 0x02180228,
314 	.p0_mprddlctl = 0x44464A46,
315 	.p1_mprddlctl = 0x44464A42,
316 	.p0_mpwrdlctl = 0x36343236,
317 	.p1_mpwrdlctl = 0x36343230,
318 };
319 
320 /* DDR 64bit 1GB */
321 static struct mx6_ddr_sysinfo mem_qdl = {
322 	.dsize = 2,
323 	.cs1_mirror = 0,
324 	/* config for full 4GB range so that get_mem_size() works */
325 	.cs_density = 32,
326 	.ncs = 1,
327 	.bi_on = 1,
328 	.rtt_nom = 1,
329 	.rtt_wr = 1,
330 	.ralat = 5,
331 	.walat = 0,
332 	.mif3_mode = 3,
333 	.rst_to_cke = 0x23,
334 	.sde_to_rst = 0x10,
335 	.refsel = 1,	/* Refresh cycles at 32KHz */
336 	.refr = 7,	/* 8 refresh commands per refresh cycle */
337 };
338 
ccgr_init(void)339 static void ccgr_init(void)
340 {
341 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
342 
343 	/* set the default clock gate to save power */
344 	writel(0x00C03F3F, &ccm->CCGR0);
345 	writel(0x0030FC03, &ccm->CCGR1);
346 	writel(0x0FFFC000, &ccm->CCGR2);
347 	writel(0x3FF00000, &ccm->CCGR3);
348 	writel(0x00FFF300, &ccm->CCGR4);
349 	writel(0xFFFFFFFF, &ccm->CCGR5);
350 	writel(0x000003FF, &ccm->CCGR6);
351 }
352 
spl_dram_init(void)353 static void spl_dram_init(void)
354 {
355 	if (is_cpu_type(MXC_CPU_MX6DL)) {
356 		mt41k128m16jt_125.mem_speed = 800;
357 		mem_qdl.rtt_nom = 1;
358 		mem_qdl.rtt_wr = 1;
359 
360 		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
361 		mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
362 	} else {
363 		printf("Wrong CPU for this board\n");
364 		return;
365 	}
366 
367 	udelay(100);
368 
369 #ifdef CONFIG_MX6_DDRCAL
370 
371 	/* Perform DDR DRAM calibration */
372 	mmdc_do_write_level_calibration(&mem_qdl);
373 	mmdc_do_dqs_calibration(&mem_qdl);
374 #endif
375 }
376 
check_bootcfg(void)377 static void check_bootcfg(void)
378 {
379 	u32 val5, val6;
380 
381 	fuse_sense(0, 5, &val5);
382 	fuse_sense(0, 6, &val6);
383 	/* Check if boot from MMC */
384 	if (val6 & 0x10) {
385 		puts("BT_FUSE_SEL already fused, will do nothing\n");
386 		return;
387 	}
388 	fuse_prog(0, 5, 0x00000840);
389 	/* BT_FUSE_SEL */
390 	fuse_prog(0, 6, 0x00000010);
391 
392 	do_reset(NULL, 0, 0, NULL);
393 }
394 
board_init_f(ulong dummy)395 void board_init_f(ulong dummy)
396 {
397 	ccgr_init();
398 
399 	/* setup AIPS and disable watchdog */
400 	arch_cpu_init();
401 
402 	gpr_init();
403 
404 	/* iomux */
405 	board_early_init_f();
406 
407 	/* setup GP timer */
408 	timer_init();
409 
410 	/* UART clocks enabled and gd valid - init serial console */
411 	preloader_console_init();
412 
413 	/* DDR initialization */
414 	spl_dram_init();
415 
416 	/* Set fuses for new boards and reboot if not set */
417 	check_bootcfg();
418 
419 	/* Clear the BSS. */
420 	memset(__bss_start, 0, __bss_end - __bss_start);
421 
422 	/* load/boot image from boot device */
423 	board_init_r(NULL, 0);
424 }
425 #endif
426