1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6 #include "ena_com.h"
7
8 /*****************************************************************************/
9 /*****************************************************************************/
10
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
13
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
16
17
18 #define ENA_CTRL_MAJOR 0
19 #define ENA_CTRL_MINOR 0
20 #define ENA_CTRL_SUB_MINOR 1
21
22 #define MIN_ENA_CTRL_VER \
23 (((ENA_CTRL_MAJOR) << \
24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
25 ((ENA_CTRL_MINOR) << \
26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
27 (ENA_CTRL_SUB_MINOR))
28
29 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
30 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31
32 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33
34 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35
36 #define ENA_REGS_ADMIN_INTR_MASK 1
37
38 #define ENA_MAX_BACKOFF_DELAY_EXP 16U
39
40 #define ENA_MIN_ADMIN_POLL_US 100
41
42 #define ENA_MAX_ADMIN_POLL_US 5000
43
44 /*****************************************************************************/
45 /*****************************************************************************/
46 /*****************************************************************************/
47
48 enum ena_cmd_status {
49 ENA_CMD_SUBMITTED,
50 ENA_CMD_COMPLETED,
51 /* Abort - canceled by the driver */
52 ENA_CMD_ABORTED,
53 };
54
55 struct ena_comp_ctx {
56 struct completion wait_event;
57 struct ena_admin_acq_entry *user_cqe;
58 u32 comp_size;
59 enum ena_cmd_status status;
60 /* status from the device */
61 u8 comp_status;
62 u8 cmd_opcode;
63 bool occupied;
64 };
65
66 struct ena_com_stats_ctx {
67 struct ena_admin_aq_get_stats_cmd get_cmd;
68 struct ena_admin_acq_get_stats_resp get_resp;
69 };
70
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)71 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
72 struct ena_common_mem_addr *ena_addr,
73 dma_addr_t addr)
74 {
75 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
76 netdev_err(ena_dev->net_device,
77 "DMA address has more bits that the device supports\n");
78 return -EINVAL;
79 }
80
81 ena_addr->mem_addr_low = lower_32_bits(addr);
82 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
83
84 return 0;
85 }
86
ena_com_admin_init_sq(struct ena_com_admin_queue * admin_queue)87 static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)
88 {
89 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
90 struct ena_com_admin_sq *sq = &admin_queue->sq;
91 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
92
93 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &sq->dma_addr, GFP_KERNEL);
94
95 if (!sq->entries) {
96 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
97 return -ENOMEM;
98 }
99
100 sq->head = 0;
101 sq->tail = 0;
102 sq->phase = 1;
103
104 sq->db_addr = NULL;
105
106 return 0;
107 }
108
ena_com_admin_init_cq(struct ena_com_admin_queue * admin_queue)109 static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)
110 {
111 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
112 struct ena_com_admin_cq *cq = &admin_queue->cq;
113 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
114
115 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &cq->dma_addr, GFP_KERNEL);
116
117 if (!cq->entries) {
118 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
119 return -ENOMEM;
120 }
121
122 cq->head = 0;
123 cq->phase = 1;
124
125 return 0;
126 }
127
ena_com_admin_init_aenq(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)128 static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,
129 struct ena_aenq_handlers *aenq_handlers)
130 {
131 struct ena_com_aenq *aenq = &ena_dev->aenq;
132 u32 addr_low, addr_high, aenq_caps;
133 u16 size;
134
135 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
136 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
137 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL);
138
139 if (!aenq->entries) {
140 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
141 return -ENOMEM;
142 }
143
144 aenq->head = aenq->q_depth;
145 aenq->phase = 1;
146
147 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
148 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
149
150 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
151 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
152
153 aenq_caps = 0;
154 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
155 aenq_caps |=
156 (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
157 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
158 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
159
160 if (unlikely(!aenq_handlers)) {
161 netdev_err(ena_dev->net_device, "AENQ handlers pointer is NULL\n");
162 return -EINVAL;
163 }
164
165 aenq->aenq_handlers = aenq_handlers;
166
167 return 0;
168 }
169
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)170 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
171 struct ena_comp_ctx *comp_ctx)
172 {
173 comp_ctx->occupied = false;
174 atomic_dec(&queue->outstanding_cmds);
175 }
176
get_comp_ctxt(struct ena_com_admin_queue * admin_queue,u16 command_id,bool capture)177 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue,
178 u16 command_id, bool capture)
179 {
180 if (unlikely(command_id >= admin_queue->q_depth)) {
181 netdev_err(admin_queue->ena_dev->net_device,
182 "Command id is larger than the queue size. cmd_id: %u queue size %d\n",
183 command_id, admin_queue->q_depth);
184 return NULL;
185 }
186
187 if (unlikely(!admin_queue->comp_ctx)) {
188 netdev_err(admin_queue->ena_dev->net_device, "Completion context is NULL\n");
189 return NULL;
190 }
191
192 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) {
193 netdev_err(admin_queue->ena_dev->net_device, "Completion context is occupied\n");
194 return NULL;
195 }
196
197 if (capture) {
198 atomic_inc(&admin_queue->outstanding_cmds);
199 admin_queue->comp_ctx[command_id].occupied = true;
200 }
201
202 return &admin_queue->comp_ctx[command_id];
203 }
204
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)205 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
206 struct ena_admin_aq_entry *cmd,
207 size_t cmd_size_in_bytes,
208 struct ena_admin_acq_entry *comp,
209 size_t comp_size_in_bytes)
210 {
211 struct ena_comp_ctx *comp_ctx;
212 u16 tail_masked, cmd_id;
213 u16 queue_size_mask;
214 u16 cnt;
215
216 queue_size_mask = admin_queue->q_depth - 1;
217
218 tail_masked = admin_queue->sq.tail & queue_size_mask;
219
220 /* In case of queue FULL */
221 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
222 if (cnt >= admin_queue->q_depth) {
223 netdev_dbg(admin_queue->ena_dev->net_device, "Admin queue is full.\n");
224 admin_queue->stats.out_of_space++;
225 return ERR_PTR(-ENOSPC);
226 }
227
228 cmd_id = admin_queue->curr_cmd_id;
229
230 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
231 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
232
233 cmd->aq_common_descriptor.command_id |= cmd_id &
234 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
235
236 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
237 if (unlikely(!comp_ctx))
238 return ERR_PTR(-EINVAL);
239
240 comp_ctx->status = ENA_CMD_SUBMITTED;
241 comp_ctx->comp_size = (u32)comp_size_in_bytes;
242 comp_ctx->user_cqe = comp;
243 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
244
245 reinit_completion(&comp_ctx->wait_event);
246
247 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
248
249 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
250 queue_size_mask;
251
252 admin_queue->sq.tail++;
253 admin_queue->stats.submitted_cmd++;
254
255 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
256 admin_queue->sq.phase = !admin_queue->sq.phase;
257
258 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
259
260 return comp_ctx;
261 }
262
ena_com_init_comp_ctxt(struct ena_com_admin_queue * admin_queue)263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue)
264 {
265 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
266 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx);
267 struct ena_comp_ctx *comp_ctx;
268 u16 i;
269
270 admin_queue->comp_ctx = devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL);
271 if (unlikely(!admin_queue->comp_ctx)) {
272 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
273 return -ENOMEM;
274 }
275
276 for (i = 0; i < admin_queue->q_depth; i++) {
277 comp_ctx = get_comp_ctxt(admin_queue, i, false);
278 if (comp_ctx)
279 init_completion(&comp_ctx->wait_event);
280 }
281
282 return 0;
283 }
284
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)285 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
286 struct ena_admin_aq_entry *cmd,
287 size_t cmd_size_in_bytes,
288 struct ena_admin_acq_entry *comp,
289 size_t comp_size_in_bytes)
290 {
291 unsigned long flags = 0;
292 struct ena_comp_ctx *comp_ctx;
293
294 spin_lock_irqsave(&admin_queue->q_lock, flags);
295 if (unlikely(!admin_queue->running_state)) {
296 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
297 return ERR_PTR(-ENODEV);
298 }
299 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
300 cmd_size_in_bytes,
301 comp,
302 comp_size_in_bytes);
303 if (IS_ERR(comp_ctx))
304 admin_queue->running_state = false;
305 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
306
307 return comp_ctx;
308 }
309
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)310 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
311 struct ena_com_create_io_ctx *ctx,
312 struct ena_com_io_sq *io_sq)
313 {
314 size_t size;
315
316 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
317
318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
319 io_sq->desc_entry_size =
320 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
321 sizeof(struct ena_eth_io_tx_desc) :
322 sizeof(struct ena_eth_io_rx_desc);
323
324 size = io_sq->desc_entry_size * io_sq->q_depth;
325
326 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
327 io_sq->desc_addr.virt_addr =
328 dma_alloc_coherent(ena_dev->dmadev, size, &io_sq->desc_addr.phys_addr,
329 GFP_KERNEL);
330 if (!io_sq->desc_addr.virt_addr) {
331 io_sq->desc_addr.virt_addr =
332 dma_alloc_coherent(ena_dev->dmadev, size,
333 &io_sq->desc_addr.phys_addr, GFP_KERNEL);
334 }
335
336 if (!io_sq->desc_addr.virt_addr) {
337 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
338 return -ENOMEM;
339 }
340 }
341
342 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
343 /* Allocate bounce buffers */
344 io_sq->bounce_buf_ctrl.buffer_size =
345 ena_dev->llq_info.desc_list_entry_size;
346 io_sq->bounce_buf_ctrl.buffers_num =
347 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
348 io_sq->bounce_buf_ctrl.next_to_use = 0;
349
350 size = (size_t)io_sq->bounce_buf_ctrl.buffer_size *
351 io_sq->bounce_buf_ctrl.buffers_num;
352
353 io_sq->bounce_buf_ctrl.base_buffer = devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
354 if (!io_sq->bounce_buf_ctrl.base_buffer)
355 io_sq->bounce_buf_ctrl.base_buffer =
356 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
357
358 if (!io_sq->bounce_buf_ctrl.base_buffer) {
359 netdev_err(ena_dev->net_device, "Bounce buffer memory allocation failed\n");
360 return -ENOMEM;
361 }
362
363 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
364 sizeof(io_sq->llq_info));
365
366 /* Initiate the first bounce buffer */
367 io_sq->llq_buf_ctrl.curr_bounce_buf =
368 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
369 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
370 0x0, io_sq->llq_info.desc_list_entry_size);
371 io_sq->llq_buf_ctrl.descs_left_in_line =
372 io_sq->llq_info.descs_num_before_header;
373 io_sq->disable_meta_caching =
374 io_sq->llq_info.disable_meta_caching;
375
376 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
377 io_sq->entries_in_tx_burst_left =
378 io_sq->llq_info.max_entries_in_tx_burst;
379 }
380
381 io_sq->tail = 0;
382 io_sq->next_to_comp = 0;
383 io_sq->phase = 1;
384
385 return 0;
386 }
387
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)388 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
389 struct ena_com_create_io_ctx *ctx,
390 struct ena_com_io_cq *io_cq)
391 {
392 size_t size;
393
394 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
395
396 /* Use the basic completion descriptor for Rx */
397 io_cq->cdesc_entry_size_in_bytes =
398 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
399 sizeof(struct ena_eth_io_tx_cdesc) :
400 sizeof(struct ena_eth_io_rx_cdesc_base);
401
402 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
403
404 io_cq->cdesc_addr.virt_addr =
405 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
406 if (!io_cq->cdesc_addr.virt_addr) {
407 io_cq->cdesc_addr.virt_addr =
408 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr,
409 GFP_KERNEL);
410 }
411
412 if (!io_cq->cdesc_addr.virt_addr) {
413 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
414 return -ENOMEM;
415 }
416
417 io_cq->phase = 1;
418 io_cq->head = 0;
419
420 return 0;
421 }
422
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)423 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
424 struct ena_admin_acq_entry *cqe)
425 {
426 struct ena_comp_ctx *comp_ctx;
427 u16 cmd_id;
428
429 cmd_id = cqe->acq_common_descriptor.command &
430 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
431
432 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
433 if (unlikely(!comp_ctx)) {
434 netdev_err(admin_queue->ena_dev->net_device,
435 "comp_ctx is NULL. Changing the admin queue running state\n");
436 admin_queue->running_state = false;
437 return;
438 }
439
440 comp_ctx->status = ENA_CMD_COMPLETED;
441 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
442
443 if (comp_ctx->user_cqe)
444 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
445
446 if (!admin_queue->polling)
447 complete(&comp_ctx->wait_event);
448 }
449
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)450 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
451 {
452 struct ena_admin_acq_entry *cqe = NULL;
453 u16 comp_num = 0;
454 u16 head_masked;
455 u8 phase;
456
457 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
458 phase = admin_queue->cq.phase;
459
460 cqe = &admin_queue->cq.entries[head_masked];
461
462 /* Go over all the completions */
463 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
464 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
465 /* Do not read the rest of the completion entry before the
466 * phase bit was validated
467 */
468 dma_rmb();
469 ena_com_handle_single_admin_completion(admin_queue, cqe);
470
471 head_masked++;
472 comp_num++;
473 if (unlikely(head_masked == admin_queue->q_depth)) {
474 head_masked = 0;
475 phase = !phase;
476 }
477
478 cqe = &admin_queue->cq.entries[head_masked];
479 }
480
481 admin_queue->cq.head += comp_num;
482 admin_queue->cq.phase = phase;
483 admin_queue->sq.head += comp_num;
484 admin_queue->stats.completed_cmd += comp_num;
485 }
486
ena_com_comp_status_to_errno(struct ena_com_admin_queue * admin_queue,u8 comp_status)487 static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue,
488 u8 comp_status)
489 {
490 if (unlikely(comp_status != 0))
491 netdev_err(admin_queue->ena_dev->net_device, "Admin command failed[%u]\n",
492 comp_status);
493
494 switch (comp_status) {
495 case ENA_ADMIN_SUCCESS:
496 return 0;
497 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
498 return -ENOMEM;
499 case ENA_ADMIN_UNSUPPORTED_OPCODE:
500 return -EOPNOTSUPP;
501 case ENA_ADMIN_BAD_OPCODE:
502 case ENA_ADMIN_MALFORMED_REQUEST:
503 case ENA_ADMIN_ILLEGAL_PARAMETER:
504 case ENA_ADMIN_UNKNOWN_ERROR:
505 return -EINVAL;
506 case ENA_ADMIN_RESOURCE_BUSY:
507 return -EAGAIN;
508 }
509
510 return -EINVAL;
511 }
512
ena_delay_exponential_backoff_us(u32 exp,u32 delay_us)513 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
514 {
515 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP);
516 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
517 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
518 usleep_range(delay_us, 2 * delay_us);
519 }
520
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)521 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
522 struct ena_com_admin_queue *admin_queue)
523 {
524 unsigned long flags = 0;
525 unsigned long timeout;
526 int ret;
527 u32 exp = 0;
528
529 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
530
531 while (1) {
532 spin_lock_irqsave(&admin_queue->q_lock, flags);
533 ena_com_handle_admin_completion(admin_queue);
534 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
535
536 if (comp_ctx->status != ENA_CMD_SUBMITTED)
537 break;
538
539 if (time_is_before_jiffies(timeout)) {
540 netdev_err(admin_queue->ena_dev->net_device,
541 "Wait for completion (polling) timeout\n");
542 /* ENA didn't have any completion */
543 spin_lock_irqsave(&admin_queue->q_lock, flags);
544 admin_queue->stats.no_completion++;
545 admin_queue->running_state = false;
546 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
547
548 ret = -ETIME;
549 goto err;
550 }
551
552 ena_delay_exponential_backoff_us(exp++,
553 admin_queue->ena_dev->ena_min_poll_delay_us);
554 }
555
556 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
557 netdev_err(admin_queue->ena_dev->net_device, "Command was aborted\n");
558 spin_lock_irqsave(&admin_queue->q_lock, flags);
559 admin_queue->stats.aborted_cmd++;
560 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
561 ret = -ENODEV;
562 goto err;
563 }
564
565 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", comp_ctx->status);
566
567 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
568 err:
569 comp_ctxt_release(admin_queue, comp_ctx);
570 return ret;
571 }
572
573 /*
574 * Set the LLQ configurations of the firmware
575 *
576 * The driver provides only the enabled feature values to the device,
577 * which in turn, checks if they are supported.
578 */
ena_com_set_llq(struct ena_com_dev * ena_dev)579 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
580 {
581 struct ena_com_admin_queue *admin_queue;
582 struct ena_admin_set_feat_cmd cmd;
583 struct ena_admin_set_feat_resp resp;
584 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
585 int ret;
586
587 memset(&cmd, 0x0, sizeof(cmd));
588 admin_queue = &ena_dev->admin_queue;
589
590 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
591 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
592
593 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
594 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
595 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
596 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
597
598 cmd.u.llq.accel_mode.u.set.enabled_flags =
599 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
600 BIT(ENA_ADMIN_LIMIT_TX_BURST);
601
602 ret = ena_com_execute_admin_command(admin_queue,
603 (struct ena_admin_aq_entry *)&cmd,
604 sizeof(cmd),
605 (struct ena_admin_acq_entry *)&resp,
606 sizeof(resp));
607
608 if (unlikely(ret))
609 netdev_err(ena_dev->net_device, "Failed to set LLQ configurations: %d\n", ret);
610
611 return ret;
612 }
613
ena_com_config_llq_info(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)614 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
615 struct ena_admin_feature_llq_desc *llq_features,
616 struct ena_llq_configurations *llq_default_cfg)
617 {
618 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
619 struct ena_admin_accel_mode_get llq_accel_mode_get;
620 u16 supported_feat;
621 int rc;
622
623 memset(llq_info, 0, sizeof(*llq_info));
624
625 supported_feat = llq_features->header_location_ctrl_supported;
626
627 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
628 llq_info->header_location_ctrl =
629 llq_default_cfg->llq_header_location;
630 } else {
631 netdev_err(ena_dev->net_device,
632 "Invalid header location control, supported: 0x%x\n", supported_feat);
633 return -EINVAL;
634 }
635
636 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
637 supported_feat = llq_features->descriptors_stride_ctrl_supported;
638 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
639 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
640 } else {
641 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
642 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
643 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
644 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
645 } else {
646 netdev_err(ena_dev->net_device,
647 "Invalid desc_stride_ctrl, supported: 0x%x\n",
648 supported_feat);
649 return -EINVAL;
650 }
651
652 netdev_err(ena_dev->net_device,
653 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
654 llq_default_cfg->llq_stride_ctrl, supported_feat,
655 llq_info->desc_stride_ctrl);
656 }
657 } else {
658 llq_info->desc_stride_ctrl = 0;
659 }
660
661 supported_feat = llq_features->entry_size_ctrl_supported;
662 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
663 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
664 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
665 } else {
666 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
667 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
668 llq_info->desc_list_entry_size = 128;
669 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
670 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
671 llq_info->desc_list_entry_size = 192;
672 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
673 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
674 llq_info->desc_list_entry_size = 256;
675 } else {
676 netdev_err(ena_dev->net_device,
677 "Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
678 return -EINVAL;
679 }
680
681 netdev_err(ena_dev->net_device,
682 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
683 llq_default_cfg->llq_ring_entry_size, supported_feat,
684 llq_info->desc_list_entry_size);
685 }
686 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
687 /* The desc list entry size should be whole multiply of 8
688 * This requirement comes from __iowrite64_copy()
689 */
690 netdev_err(ena_dev->net_device, "Illegal entry size %d\n",
691 llq_info->desc_list_entry_size);
692 return -EINVAL;
693 }
694
695 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
696 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
697 sizeof(struct ena_eth_io_tx_desc);
698 else
699 llq_info->descs_per_entry = 1;
700
701 supported_feat = llq_features->desc_num_before_header_supported;
702 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
703 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
704 } else {
705 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
706 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
707 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
708 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
709 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
710 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
711 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
712 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
713 } else {
714 netdev_err(ena_dev->net_device,
715 "Invalid descs_num_before_header, supported: 0x%x\n",
716 supported_feat);
717 return -EINVAL;
718 }
719
720 netdev_err(ena_dev->net_device,
721 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
722 llq_default_cfg->llq_num_decs_before_header, supported_feat,
723 llq_info->descs_num_before_header);
724 }
725 /* Check for accelerated queue supported */
726 llq_accel_mode_get = llq_features->accel_mode.u.get;
727
728 llq_info->disable_meta_caching =
729 !!(llq_accel_mode_get.supported_flags &
730 BIT(ENA_ADMIN_DISABLE_META_CACHING));
731
732 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
733 llq_info->max_entries_in_tx_burst =
734 llq_accel_mode_get.max_tx_burst_size /
735 llq_default_cfg->llq_ring_entry_size_value;
736
737 rc = ena_com_set_llq(ena_dev);
738 if (rc)
739 netdev_err(ena_dev->net_device, "Cannot set LLQ configuration: %d\n", rc);
740
741 return rc;
742 }
743
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)744 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
745 struct ena_com_admin_queue *admin_queue)
746 {
747 unsigned long flags = 0;
748 int ret;
749
750 wait_for_completion_timeout(&comp_ctx->wait_event,
751 usecs_to_jiffies(admin_queue->completion_timeout));
752
753 /* In case the command wasn't completed find out the root cause.
754 * There might be 2 kinds of errors
755 * 1) No completion (timeout reached)
756 * 2) There is completion but the device didn't get any msi-x interrupt.
757 */
758 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
759 spin_lock_irqsave(&admin_queue->q_lock, flags);
760 ena_com_handle_admin_completion(admin_queue);
761 admin_queue->stats.no_completion++;
762 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
763
764 if (comp_ctx->status == ENA_CMD_COMPLETED) {
765 netdev_err(admin_queue->ena_dev->net_device,
766 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
767 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
768 /* Check if fallback to polling is enabled */
769 if (admin_queue->auto_polling)
770 admin_queue->polling = true;
771 } else {
772 netdev_err(admin_queue->ena_dev->net_device,
773 "The ena device didn't send a completion for the admin cmd %d status %d\n",
774 comp_ctx->cmd_opcode, comp_ctx->status);
775 }
776 /* Check if shifted to polling mode.
777 * This will happen if there is a completion without an interrupt
778 * and autopolling mode is enabled. Continuing normal execution in such case
779 */
780 if (!admin_queue->polling) {
781 admin_queue->running_state = false;
782 ret = -ETIME;
783 goto err;
784 }
785 }
786
787 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
788 err:
789 comp_ctxt_release(admin_queue, comp_ctx);
790 return ret;
791 }
792
793 /* This method read the hardware device register through posting writes
794 * and waiting for response
795 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
796 */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)797 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
798 {
799 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
800 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
801 mmio_read->read_resp;
802 u32 mmio_read_reg, ret, i;
803 unsigned long flags = 0;
804 u32 timeout = mmio_read->reg_read_to;
805
806 might_sleep();
807
808 if (timeout == 0)
809 timeout = ENA_REG_READ_TIMEOUT;
810
811 /* If readless is disabled, perform regular read */
812 if (!mmio_read->readless_supported)
813 return readl(ena_dev->reg_bar + offset);
814
815 spin_lock_irqsave(&mmio_read->lock, flags);
816 mmio_read->seq_num++;
817
818 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
819 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
820 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
821 mmio_read_reg |= mmio_read->seq_num &
822 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
823
824 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
825
826 for (i = 0; i < timeout; i++) {
827 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
828 break;
829
830 udelay(1);
831 }
832
833 if (unlikely(i == timeout)) {
834 netdev_err(ena_dev->net_device,
835 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n",
836 mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off);
837 ret = ENA_MMIO_READ_TIMEOUT;
838 goto err;
839 }
840
841 if (read_resp->reg_off != offset) {
842 netdev_err(ena_dev->net_device, "Read failure: wrong offset provided\n");
843 ret = ENA_MMIO_READ_TIMEOUT;
844 } else {
845 ret = read_resp->reg_val;
846 }
847 err:
848 spin_unlock_irqrestore(&mmio_read->lock, flags);
849
850 return ret;
851 }
852
853 /* There are two types to wait for completion.
854 * Polling mode - wait until the completion is available.
855 * Async mode - wait on wait queue until the completion is ready
856 * (or the timeout expired).
857 * It is expected that the IRQ called ena_com_handle_admin_completion
858 * to mark the completions.
859 */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)860 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
861 struct ena_com_admin_queue *admin_queue)
862 {
863 if (admin_queue->polling)
864 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
865 admin_queue);
866
867 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
868 admin_queue);
869 }
870
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)871 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
872 struct ena_com_io_sq *io_sq)
873 {
874 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
875 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
876 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
877 u8 direction;
878 int ret;
879
880 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
881
882 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
883 direction = ENA_ADMIN_SQ_DIRECTION_TX;
884 else
885 direction = ENA_ADMIN_SQ_DIRECTION_RX;
886
887 destroy_cmd.sq.sq_identity |= (direction <<
888 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
889 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
890
891 destroy_cmd.sq.sq_idx = io_sq->idx;
892 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
893
894 ret = ena_com_execute_admin_command(admin_queue,
895 (struct ena_admin_aq_entry *)&destroy_cmd,
896 sizeof(destroy_cmd),
897 (struct ena_admin_acq_entry *)&destroy_resp,
898 sizeof(destroy_resp));
899
900 if (unlikely(ret && (ret != -ENODEV)))
901 netdev_err(ena_dev->net_device, "Failed to destroy io sq error: %d\n", ret);
902
903 return ret;
904 }
905
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)906 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
907 struct ena_com_io_sq *io_sq,
908 struct ena_com_io_cq *io_cq)
909 {
910 size_t size;
911
912 if (io_cq->cdesc_addr.virt_addr) {
913 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
914
915 dma_free_coherent(ena_dev->dmadev, size, io_cq->cdesc_addr.virt_addr,
916 io_cq->cdesc_addr.phys_addr);
917
918 io_cq->cdesc_addr.virt_addr = NULL;
919 }
920
921 if (io_sq->desc_addr.virt_addr) {
922 size = io_sq->desc_entry_size * io_sq->q_depth;
923
924 dma_free_coherent(ena_dev->dmadev, size, io_sq->desc_addr.virt_addr,
925 io_sq->desc_addr.phys_addr);
926
927 io_sq->desc_addr.virt_addr = NULL;
928 }
929
930 if (io_sq->bounce_buf_ctrl.base_buffer) {
931 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
932 io_sq->bounce_buf_ctrl.base_buffer = NULL;
933 }
934 }
935
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)936 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
937 u16 exp_state)
938 {
939 u32 val, exp = 0;
940 unsigned long timeout_stamp;
941
942 /* Convert timeout from resolution of 100ms to us resolution. */
943 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
944
945 while (1) {
946 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
947
948 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
949 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
950 return -ETIME;
951 }
952
953 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
954 exp_state)
955 return 0;
956
957 if (time_is_before_jiffies(timeout_stamp))
958 return -ETIME;
959
960 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
961 }
962 }
963
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)964 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
965 enum ena_admin_aq_feature_id feature_id)
966 {
967 u32 feature_mask = 1 << feature_id;
968
969 /* Device attributes is always supported */
970 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
971 !(ena_dev->supported_features & feature_mask))
972 return false;
973
974 return true;
975 }
976
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size,u8 feature_ver)977 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
978 struct ena_admin_get_feat_resp *get_resp,
979 enum ena_admin_aq_feature_id feature_id,
980 dma_addr_t control_buf_dma_addr,
981 u32 control_buff_size,
982 u8 feature_ver)
983 {
984 struct ena_com_admin_queue *admin_queue;
985 struct ena_admin_get_feat_cmd get_cmd;
986 int ret;
987
988 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
989 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", feature_id);
990 return -EOPNOTSUPP;
991 }
992
993 memset(&get_cmd, 0x0, sizeof(get_cmd));
994 admin_queue = &ena_dev->admin_queue;
995
996 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
997
998 if (control_buff_size)
999 get_cmd.aq_common_descriptor.flags =
1000 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1001 else
1002 get_cmd.aq_common_descriptor.flags = 0;
1003
1004 ret = ena_com_mem_addr_set(ena_dev,
1005 &get_cmd.control_buffer.address,
1006 control_buf_dma_addr);
1007 if (unlikely(ret)) {
1008 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1009 return ret;
1010 }
1011
1012 get_cmd.control_buffer.length = control_buff_size;
1013 get_cmd.feat_common.feature_version = feature_ver;
1014 get_cmd.feat_common.feature_id = feature_id;
1015
1016 ret = ena_com_execute_admin_command(admin_queue,
1017 (struct ena_admin_aq_entry *)
1018 &get_cmd,
1019 sizeof(get_cmd),
1020 (struct ena_admin_acq_entry *)
1021 get_resp,
1022 sizeof(*get_resp));
1023
1024 if (unlikely(ret))
1025 netdev_err(ena_dev->net_device,
1026 "Failed to submit get_feature command %d error: %d\n", feature_id, ret);
1027
1028 return ret;
1029 }
1030
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,u8 feature_ver)1031 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1032 struct ena_admin_get_feat_resp *get_resp,
1033 enum ena_admin_aq_feature_id feature_id,
1034 u8 feature_ver)
1035 {
1036 return ena_com_get_feature_ex(ena_dev,
1037 get_resp,
1038 feature_id,
1039 0,
1040 0,
1041 feature_ver);
1042 }
1043
ena_com_get_current_hash_function(struct ena_com_dev * ena_dev)1044 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1045 {
1046 return ena_dev->rss.hash_func;
1047 }
1048
ena_com_hash_key_fill_default_key(struct ena_com_dev * ena_dev)1049 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1050 {
1051 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1052 (ena_dev->rss).hash_key;
1053
1054 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
1055 /* The key buffer is stored in the device in an array of
1056 * uint32 elements.
1057 */
1058 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS;
1059 }
1060
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)1061 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1062 {
1063 struct ena_rss *rss = &ena_dev->rss;
1064
1065 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION))
1066 return -EOPNOTSUPP;
1067
1068 rss->hash_key = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1069 &rss->hash_key_dma_addr, GFP_KERNEL);
1070
1071 if (unlikely(!rss->hash_key))
1072 return -ENOMEM;
1073
1074 return 0;
1075 }
1076
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)1077 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1078 {
1079 struct ena_rss *rss = &ena_dev->rss;
1080
1081 if (rss->hash_key)
1082 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), rss->hash_key,
1083 rss->hash_key_dma_addr);
1084 rss->hash_key = NULL;
1085 }
1086
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)1087 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1088 {
1089 struct ena_rss *rss = &ena_dev->rss;
1090
1091 rss->hash_ctrl = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1092 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
1093
1094 if (unlikely(!rss->hash_ctrl))
1095 return -ENOMEM;
1096
1097 return 0;
1098 }
1099
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)1100 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1101 {
1102 struct ena_rss *rss = &ena_dev->rss;
1103
1104 if (rss->hash_ctrl)
1105 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), rss->hash_ctrl,
1106 rss->hash_ctrl_dma_addr);
1107 rss->hash_ctrl = NULL;
1108 }
1109
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)1110 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1111 u16 log_size)
1112 {
1113 struct ena_rss *rss = &ena_dev->rss;
1114 struct ena_admin_get_feat_resp get_resp;
1115 size_t tbl_size;
1116 int ret;
1117
1118 ret = ena_com_get_feature(ena_dev, &get_resp,
1119 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0);
1120 if (unlikely(ret))
1121 return ret;
1122
1123 if ((get_resp.u.ind_table.min_size > log_size) ||
1124 (get_resp.u.ind_table.max_size < log_size)) {
1125 netdev_err(ena_dev->net_device,
1126 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1127 1 << log_size, 1 << get_resp.u.ind_table.min_size,
1128 1 << get_resp.u.ind_table.max_size);
1129 return -EINVAL;
1130 }
1131
1132 tbl_size = (1ULL << log_size) *
1133 sizeof(struct ena_admin_rss_ind_table_entry);
1134
1135 rss->rss_ind_tbl = dma_alloc_coherent(ena_dev->dmadev, tbl_size, &rss->rss_ind_tbl_dma_addr,
1136 GFP_KERNEL);
1137 if (unlikely(!rss->rss_ind_tbl))
1138 goto mem_err1;
1139
1140 tbl_size = (1ULL << log_size) * sizeof(u16);
1141 rss->host_rss_ind_tbl = devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
1142 if (unlikely(!rss->host_rss_ind_tbl))
1143 goto mem_err2;
1144
1145 rss->tbl_log_size = log_size;
1146
1147 return 0;
1148
1149 mem_err2:
1150 tbl_size = (1ULL << log_size) *
1151 sizeof(struct ena_admin_rss_ind_table_entry);
1152
1153 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, rss->rss_ind_tbl_dma_addr);
1154 rss->rss_ind_tbl = NULL;
1155 mem_err1:
1156 rss->tbl_log_size = 0;
1157 return -ENOMEM;
1158 }
1159
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)1160 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1161 {
1162 struct ena_rss *rss = &ena_dev->rss;
1163 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1164 sizeof(struct ena_admin_rss_ind_table_entry);
1165
1166 if (rss->rss_ind_tbl)
1167 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1168 rss->rss_ind_tbl_dma_addr);
1169 rss->rss_ind_tbl = NULL;
1170
1171 if (rss->host_rss_ind_tbl)
1172 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
1173 rss->host_rss_ind_tbl = NULL;
1174 }
1175
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)1176 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1177 struct ena_com_io_sq *io_sq, u16 cq_idx)
1178 {
1179 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1180 struct ena_admin_aq_create_sq_cmd create_cmd;
1181 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1182 u8 direction;
1183 int ret;
1184
1185 memset(&create_cmd, 0x0, sizeof(create_cmd));
1186
1187 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1188
1189 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1190 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1191 else
1192 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1193
1194 create_cmd.sq_identity |= (direction <<
1195 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1196 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1197
1198 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1199 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1200
1201 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1202 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1203 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1204
1205 create_cmd.sq_caps_3 |=
1206 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1207
1208 create_cmd.cq_idx = cq_idx;
1209 create_cmd.sq_depth = io_sq->q_depth;
1210
1211 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1212 ret = ena_com_mem_addr_set(ena_dev,
1213 &create_cmd.sq_ba,
1214 io_sq->desc_addr.phys_addr);
1215 if (unlikely(ret)) {
1216 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1217 return ret;
1218 }
1219 }
1220
1221 ret = ena_com_execute_admin_command(admin_queue,
1222 (struct ena_admin_aq_entry *)&create_cmd,
1223 sizeof(create_cmd),
1224 (struct ena_admin_acq_entry *)&cmd_completion,
1225 sizeof(cmd_completion));
1226 if (unlikely(ret)) {
1227 netdev_err(ena_dev->net_device, "Failed to create IO SQ. error: %d\n", ret);
1228 return ret;
1229 }
1230
1231 io_sq->idx = cmd_completion.sq_idx;
1232
1233 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1234 (uintptr_t)cmd_completion.sq_doorbell_offset);
1235
1236 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1237 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1238 + cmd_completion.llq_headers_offset);
1239
1240 io_sq->desc_addr.pbuf_dev_addr =
1241 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1242 cmd_completion.llq_descriptors_offset);
1243 }
1244
1245 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1246
1247 return ret;
1248 }
1249
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1250 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1251 {
1252 struct ena_rss *rss = &ena_dev->rss;
1253 struct ena_com_io_sq *io_sq;
1254 u16 qid;
1255 int i;
1256
1257 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1258 qid = rss->host_rss_ind_tbl[i];
1259 if (qid >= ENA_TOTAL_NUM_QUEUES)
1260 return -EINVAL;
1261
1262 io_sq = &ena_dev->io_sq_queues[qid];
1263
1264 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1265 return -EINVAL;
1266
1267 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1268 }
1269
1270 return 0;
1271 }
1272
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1273 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1274 u16 intr_delay_resolution)
1275 {
1276 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1277
1278 if (unlikely(!intr_delay_resolution)) {
1279 netdev_err(ena_dev->net_device,
1280 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1281 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1282 }
1283
1284 /* update Rx */
1285 ena_dev->intr_moder_rx_interval =
1286 ena_dev->intr_moder_rx_interval *
1287 prev_intr_delay_resolution /
1288 intr_delay_resolution;
1289
1290 /* update Tx */
1291 ena_dev->intr_moder_tx_interval =
1292 ena_dev->intr_moder_tx_interval *
1293 prev_intr_delay_resolution /
1294 intr_delay_resolution;
1295
1296 ena_dev->intr_delay_resolution = intr_delay_resolution;
1297 }
1298
1299 /*****************************************************************************/
1300 /******************************* API ******************************/
1301 /*****************************************************************************/
1302
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1303 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1304 struct ena_admin_aq_entry *cmd,
1305 size_t cmd_size,
1306 struct ena_admin_acq_entry *comp,
1307 size_t comp_size)
1308 {
1309 struct ena_comp_ctx *comp_ctx;
1310 int ret;
1311
1312 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1313 comp, comp_size);
1314 if (IS_ERR(comp_ctx)) {
1315 ret = PTR_ERR(comp_ctx);
1316 if (ret == -ENODEV)
1317 netdev_dbg(admin_queue->ena_dev->net_device,
1318 "Failed to submit command [%d]\n", ret);
1319 else
1320 netdev_err(admin_queue->ena_dev->net_device,
1321 "Failed to submit command [%d]\n", ret);
1322
1323 return ret;
1324 }
1325
1326 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1327 if (unlikely(ret)) {
1328 if (admin_queue->running_state)
1329 netdev_err(admin_queue->ena_dev->net_device,
1330 "Failed to process command. ret = %d\n", ret);
1331 else
1332 netdev_dbg(admin_queue->ena_dev->net_device,
1333 "Failed to process command. ret = %d\n", ret);
1334 }
1335 return ret;
1336 }
1337
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1338 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1339 struct ena_com_io_cq *io_cq)
1340 {
1341 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1342 struct ena_admin_aq_create_cq_cmd create_cmd;
1343 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1344 int ret;
1345
1346 memset(&create_cmd, 0x0, sizeof(create_cmd));
1347
1348 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1349
1350 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1351 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1352 create_cmd.cq_caps_1 |=
1353 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1354
1355 create_cmd.msix_vector = io_cq->msix_vector;
1356 create_cmd.cq_depth = io_cq->q_depth;
1357
1358 ret = ena_com_mem_addr_set(ena_dev,
1359 &create_cmd.cq_ba,
1360 io_cq->cdesc_addr.phys_addr);
1361 if (unlikely(ret)) {
1362 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1363 return ret;
1364 }
1365
1366 ret = ena_com_execute_admin_command(admin_queue,
1367 (struct ena_admin_aq_entry *)&create_cmd,
1368 sizeof(create_cmd),
1369 (struct ena_admin_acq_entry *)&cmd_completion,
1370 sizeof(cmd_completion));
1371 if (unlikely(ret)) {
1372 netdev_err(ena_dev->net_device, "Failed to create IO CQ. error: %d\n", ret);
1373 return ret;
1374 }
1375
1376 io_cq->idx = cmd_completion.cq_idx;
1377
1378 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1379 cmd_completion.cq_interrupt_unmask_register_offset);
1380
1381 if (cmd_completion.cq_head_db_register_offset)
1382 io_cq->cq_head_db_reg =
1383 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1384 cmd_completion.cq_head_db_register_offset);
1385
1386 if (cmd_completion.numa_node_register_offset)
1387 io_cq->numa_node_cfg_reg =
1388 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1389 cmd_completion.numa_node_register_offset);
1390
1391 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1392
1393 return ret;
1394 }
1395
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1396 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1397 struct ena_com_io_sq **io_sq,
1398 struct ena_com_io_cq **io_cq)
1399 {
1400 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1401 netdev_err(ena_dev->net_device, "Invalid queue number %d but the max is %d\n", qid,
1402 ENA_TOTAL_NUM_QUEUES);
1403 return -EINVAL;
1404 }
1405
1406 *io_sq = &ena_dev->io_sq_queues[qid];
1407 *io_cq = &ena_dev->io_cq_queues[qid];
1408
1409 return 0;
1410 }
1411
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1412 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1413 {
1414 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1415 struct ena_comp_ctx *comp_ctx;
1416 u16 i;
1417
1418 if (!admin_queue->comp_ctx)
1419 return;
1420
1421 for (i = 0; i < admin_queue->q_depth; i++) {
1422 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1423 if (unlikely(!comp_ctx))
1424 break;
1425
1426 comp_ctx->status = ENA_CMD_ABORTED;
1427
1428 complete(&comp_ctx->wait_event);
1429 }
1430 }
1431
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1432 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1433 {
1434 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1435 unsigned long flags = 0;
1436 u32 exp = 0;
1437
1438 spin_lock_irqsave(&admin_queue->q_lock, flags);
1439 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1440 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1441 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1442 spin_lock_irqsave(&admin_queue->q_lock, flags);
1443 }
1444 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1445 }
1446
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1447 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1448 struct ena_com_io_cq *io_cq)
1449 {
1450 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1451 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1452 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1453 int ret;
1454
1455 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1456
1457 destroy_cmd.cq_idx = io_cq->idx;
1458 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1459
1460 ret = ena_com_execute_admin_command(admin_queue,
1461 (struct ena_admin_aq_entry *)&destroy_cmd,
1462 sizeof(destroy_cmd),
1463 (struct ena_admin_acq_entry *)&destroy_resp,
1464 sizeof(destroy_resp));
1465
1466 if (unlikely(ret && (ret != -ENODEV)))
1467 netdev_err(ena_dev->net_device, "Failed to destroy IO CQ. error: %d\n", ret);
1468
1469 return ret;
1470 }
1471
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1472 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1473 {
1474 return ena_dev->admin_queue.running_state;
1475 }
1476
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1477 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1478 {
1479 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1480 unsigned long flags = 0;
1481
1482 spin_lock_irqsave(&admin_queue->q_lock, flags);
1483 ena_dev->admin_queue.running_state = state;
1484 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1485 }
1486
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1487 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1488 {
1489 u16 depth = ena_dev->aenq.q_depth;
1490
1491 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1492
1493 /* Init head_db to mark that all entries in the queue
1494 * are initially available
1495 */
1496 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1497 }
1498
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1499 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1500 {
1501 struct ena_com_admin_queue *admin_queue;
1502 struct ena_admin_set_feat_cmd cmd;
1503 struct ena_admin_set_feat_resp resp;
1504 struct ena_admin_get_feat_resp get_resp;
1505 int ret;
1506
1507 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1508 if (ret) {
1509 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n");
1510 return ret;
1511 }
1512
1513 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1514 netdev_warn(ena_dev->net_device,
1515 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1516 get_resp.u.aenq.supported_groups, groups_flag);
1517 return -EOPNOTSUPP;
1518 }
1519
1520 memset(&cmd, 0x0, sizeof(cmd));
1521 admin_queue = &ena_dev->admin_queue;
1522
1523 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1524 cmd.aq_common_descriptor.flags = 0;
1525 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1526 cmd.u.aenq.enabled_groups = groups_flag;
1527
1528 ret = ena_com_execute_admin_command(admin_queue,
1529 (struct ena_admin_aq_entry *)&cmd,
1530 sizeof(cmd),
1531 (struct ena_admin_acq_entry *)&resp,
1532 sizeof(resp));
1533
1534 if (unlikely(ret))
1535 netdev_err(ena_dev->net_device, "Failed to config AENQ ret: %d\n", ret);
1536
1537 return ret;
1538 }
1539
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1540 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1541 {
1542 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1543 u32 width;
1544
1545 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1546 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1547 return -ETIME;
1548 }
1549
1550 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1551 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1552
1553 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width);
1554
1555 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1556 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n", width);
1557 return -EINVAL;
1558 }
1559
1560 ena_dev->dma_addr_bits = width;
1561
1562 return width;
1563 }
1564
ena_com_validate_version(struct ena_com_dev * ena_dev)1565 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1566 {
1567 u32 ver;
1568 u32 ctrl_ver;
1569 u32 ctrl_ver_masked;
1570
1571 /* Make sure the ENA version and the controller version are at least
1572 * as the driver expects
1573 */
1574 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1575 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1576 ENA_REGS_CONTROLLER_VERSION_OFF);
1577
1578 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1579 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1580 return -ETIME;
1581 }
1582
1583 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n",
1584 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1585 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1586
1587 dev_info(ena_dev->dmadev, "ENA controller version: %d.%d.%d implementation version %d\n",
1588 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1589 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1590 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1591 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1592 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1593 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1594 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1595
1596 ctrl_ver_masked =
1597 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1598 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1599 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1600
1601 /* Validate the ctrl version without the implementation ID */
1602 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1603 netdev_err(ena_dev->net_device,
1604 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1605 return -1;
1606 }
1607
1608 return 0;
1609 }
1610
1611 static void
ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev * ena_dev,struct ena_com_admin_queue * admin_queue)1612 ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev,
1613 struct ena_com_admin_queue *admin_queue)
1614
1615 {
1616 if (!admin_queue->comp_ctx)
1617 return;
1618
1619 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1620
1621 admin_queue->comp_ctx = NULL;
1622 }
1623
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1624 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1625 {
1626 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1627 struct ena_com_admin_cq *cq = &admin_queue->cq;
1628 struct ena_com_admin_sq *sq = &admin_queue->sq;
1629 struct ena_com_aenq *aenq = &ena_dev->aenq;
1630 u16 size;
1631
1632 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue);
1633
1634 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1635 if (sq->entries)
1636 dma_free_coherent(ena_dev->dmadev, size, sq->entries, sq->dma_addr);
1637 sq->entries = NULL;
1638
1639 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1640 if (cq->entries)
1641 dma_free_coherent(ena_dev->dmadev, size, cq->entries, cq->dma_addr);
1642 cq->entries = NULL;
1643
1644 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1645 if (ena_dev->aenq.entries)
1646 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr);
1647 aenq->entries = NULL;
1648 }
1649
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1650 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1651 {
1652 u32 mask_value = 0;
1653
1654 if (polling)
1655 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1656
1657 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1658 ena_dev->admin_queue.polling = polling;
1659 }
1660
ena_com_set_admin_auto_polling_mode(struct ena_com_dev * ena_dev,bool polling)1661 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1662 bool polling)
1663 {
1664 ena_dev->admin_queue.auto_polling = polling;
1665 }
1666
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1667 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1668 {
1669 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1670
1671 spin_lock_init(&mmio_read->lock);
1672 mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1673 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1674 if (unlikely(!mmio_read->read_resp))
1675 goto err;
1676
1677 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1678
1679 mmio_read->read_resp->req_id = 0x0;
1680 mmio_read->seq_num = 0x0;
1681 mmio_read->readless_supported = true;
1682
1683 return 0;
1684
1685 err:
1686
1687 return -ENOMEM;
1688 }
1689
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1690 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1691 {
1692 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1693
1694 mmio_read->readless_supported = readless_supported;
1695 }
1696
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1697 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1698 {
1699 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1700
1701 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1702 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1703
1704 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp,
1705 mmio_read->read_resp_dma_addr);
1706
1707 mmio_read->read_resp = NULL;
1708 }
1709
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1710 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1711 {
1712 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1713 u32 addr_low, addr_high;
1714
1715 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1716 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1717
1718 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1719 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1720 }
1721
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)1722 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1723 struct ena_aenq_handlers *aenq_handlers)
1724 {
1725 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1726 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1727 int ret;
1728
1729 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1730
1731 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1732 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1733 return -ETIME;
1734 }
1735
1736 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1737 netdev_err(ena_dev->net_device, "Device isn't ready, abort com init\n");
1738 return -ENODEV;
1739 }
1740
1741 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1742
1743 admin_queue->q_dmadev = ena_dev->dmadev;
1744 admin_queue->polling = false;
1745 admin_queue->curr_cmd_id = 0;
1746
1747 atomic_set(&admin_queue->outstanding_cmds, 0);
1748
1749 spin_lock_init(&admin_queue->q_lock);
1750
1751 ret = ena_com_init_comp_ctxt(admin_queue);
1752 if (ret)
1753 goto error;
1754
1755 ret = ena_com_admin_init_sq(admin_queue);
1756 if (ret)
1757 goto error;
1758
1759 ret = ena_com_admin_init_cq(admin_queue);
1760 if (ret)
1761 goto error;
1762
1763 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1764 ENA_REGS_AQ_DB_OFF);
1765
1766 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1767 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1768
1769 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1770 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1771
1772 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1773 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1774
1775 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1776 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1777
1778 aq_caps = 0;
1779 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1780 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1781 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1782 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1783
1784 acq_caps = 0;
1785 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1786 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1787 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1788 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1789
1790 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1791 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1792 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1793 if (ret)
1794 goto error;
1795
1796 admin_queue->ena_dev = ena_dev;
1797 admin_queue->running_state = true;
1798
1799 return 0;
1800 error:
1801 ena_com_admin_destroy(ena_dev);
1802
1803 return ret;
1804 }
1805
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)1806 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1807 struct ena_com_create_io_ctx *ctx)
1808 {
1809 struct ena_com_io_sq *io_sq;
1810 struct ena_com_io_cq *io_cq;
1811 int ret;
1812
1813 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1814 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
1815 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1816 return -EINVAL;
1817 }
1818
1819 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1820 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1821
1822 memset(io_sq, 0x0, sizeof(*io_sq));
1823 memset(io_cq, 0x0, sizeof(*io_cq));
1824
1825 /* Init CQ */
1826 io_cq->q_depth = ctx->queue_size;
1827 io_cq->direction = ctx->direction;
1828 io_cq->qid = ctx->qid;
1829
1830 io_cq->msix_vector = ctx->msix_vector;
1831
1832 io_sq->q_depth = ctx->queue_size;
1833 io_sq->direction = ctx->direction;
1834 io_sq->qid = ctx->qid;
1835
1836 io_sq->mem_queue_type = ctx->mem_queue_type;
1837
1838 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1839 /* header length is limited to 8 bits */
1840 io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1841
1842 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1843 if (ret)
1844 goto error;
1845 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1846 if (ret)
1847 goto error;
1848
1849 ret = ena_com_create_io_cq(ena_dev, io_cq);
1850 if (ret)
1851 goto error;
1852
1853 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1854 if (ret)
1855 goto destroy_io_cq;
1856
1857 return 0;
1858
1859 destroy_io_cq:
1860 ena_com_destroy_io_cq(ena_dev, io_cq);
1861 error:
1862 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1863 return ret;
1864 }
1865
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)1866 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1867 {
1868 struct ena_com_io_sq *io_sq;
1869 struct ena_com_io_cq *io_cq;
1870
1871 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1872 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n",
1873 qid, ENA_TOTAL_NUM_QUEUES);
1874 return;
1875 }
1876
1877 io_sq = &ena_dev->io_sq_queues[qid];
1878 io_cq = &ena_dev->io_cq_queues[qid];
1879
1880 ena_com_destroy_io_sq(ena_dev, io_sq);
1881 ena_com_destroy_io_cq(ena_dev, io_cq);
1882
1883 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1884 }
1885
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)1886 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1887 struct ena_admin_get_feat_resp *resp)
1888 {
1889 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1890 }
1891
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1892 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1893 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1894 {
1895 struct ena_admin_get_feat_resp get_resp;
1896 int rc;
1897
1898 rc = ena_com_get_feature(ena_dev, &get_resp,
1899 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1900 if (rc)
1901 return rc;
1902
1903 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1904 sizeof(get_resp.u.dev_attr));
1905
1906 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1907 ena_dev->capabilities = get_resp.u.dev_attr.capabilities;
1908
1909 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1910 rc = ena_com_get_feature(ena_dev, &get_resp,
1911 ENA_ADMIN_MAX_QUEUES_EXT,
1912 ENA_FEATURE_MAX_QUEUE_EXT_VER);
1913 if (rc)
1914 return rc;
1915
1916 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1917 return -EINVAL;
1918
1919 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1920 sizeof(get_resp.u.max_queue_ext));
1921 ena_dev->tx_max_header_size =
1922 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1923 } else {
1924 rc = ena_com_get_feature(ena_dev, &get_resp,
1925 ENA_ADMIN_MAX_QUEUES_NUM, 0);
1926 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1927 sizeof(get_resp.u.max_queue));
1928 ena_dev->tx_max_header_size =
1929 get_resp.u.max_queue.max_header_size;
1930
1931 if (rc)
1932 return rc;
1933 }
1934
1935 rc = ena_com_get_feature(ena_dev, &get_resp,
1936 ENA_ADMIN_AENQ_CONFIG, 0);
1937 if (rc)
1938 return rc;
1939
1940 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1941 sizeof(get_resp.u.aenq));
1942
1943 rc = ena_com_get_feature(ena_dev, &get_resp,
1944 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1945 if (rc)
1946 return rc;
1947
1948 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1949 sizeof(get_resp.u.offload));
1950
1951 /* Driver hints isn't mandatory admin command. So in case the
1952 * command isn't supported set driver hints to 0
1953 */
1954 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1955
1956 if (!rc)
1957 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, sizeof(get_resp.u.hw_hints));
1958 else if (rc == -EOPNOTSUPP)
1959 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1960 else
1961 return rc;
1962
1963 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1964 if (!rc)
1965 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, sizeof(get_resp.u.llq));
1966 else if (rc == -EOPNOTSUPP)
1967 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1968 else
1969 return rc;
1970
1971 return 0;
1972 }
1973
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)1974 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1975 {
1976 ena_com_handle_admin_completion(&ena_dev->admin_queue);
1977 }
1978
1979 /* ena_handle_specific_aenq_event:
1980 * return the handler that is relevant to the specific event group
1981 */
ena_com_get_specific_aenq_cb(struct ena_com_dev * ena_dev,u16 group)1982 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev,
1983 u16 group)
1984 {
1985 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;
1986
1987 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1988 return aenq_handlers->handlers[group];
1989
1990 return aenq_handlers->unimplemented_handler;
1991 }
1992
1993 /* ena_aenq_intr_handler:
1994 * handles the aenq incoming events.
1995 * pop events from the queue and apply the specific handler
1996 */
ena_com_aenq_intr_handler(struct ena_com_dev * ena_dev,void * data)1997 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)
1998 {
1999 struct ena_admin_aenq_entry *aenq_e;
2000 struct ena_admin_aenq_common_desc *aenq_common;
2001 struct ena_com_aenq *aenq = &ena_dev->aenq;
2002 u64 timestamp;
2003 ena_aenq_handler handler_cb;
2004 u16 masked_head, processed = 0;
2005 u8 phase;
2006
2007 masked_head = aenq->head & (aenq->q_depth - 1);
2008 phase = aenq->phase;
2009 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2010 aenq_common = &aenq_e->aenq_common_desc;
2011
2012 /* Go over all the events */
2013 while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2014 /* Make sure the phase bit (ownership) is as expected before
2015 * reading the rest of the descriptor.
2016 */
2017 dma_rmb();
2018
2019 timestamp = (u64)aenq_common->timestamp_low |
2020 ((u64)aenq_common->timestamp_high << 32);
2021
2022 netdev_dbg(ena_dev->net_device, "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n",
2023 aenq_common->group, aenq_common->syndrome, timestamp);
2024
2025 /* Handle specific event*/
2026 handler_cb = ena_com_get_specific_aenq_cb(ena_dev,
2027 aenq_common->group);
2028 handler_cb(data, aenq_e); /* call the actual event handler*/
2029
2030 /* Get next event entry */
2031 masked_head++;
2032 processed++;
2033
2034 if (unlikely(masked_head == aenq->q_depth)) {
2035 masked_head = 0;
2036 phase = !phase;
2037 }
2038 aenq_e = &aenq->entries[masked_head];
2039 aenq_common = &aenq_e->aenq_common_desc;
2040 }
2041
2042 aenq->head += processed;
2043 aenq->phase = phase;
2044
2045 /* Don't update aenq doorbell if there weren't any processed events */
2046 if (!processed)
2047 return;
2048
2049 /* write the aenq doorbell after all AENQ descriptors were read */
2050 mb();
2051 writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2052 }
2053
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)2054 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2055 enum ena_regs_reset_reason_types reset_reason)
2056 {
2057 u32 stat, timeout, cap, reset_val;
2058 int rc;
2059
2060 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2061 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2062
2063 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) {
2064 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n");
2065 return -ETIME;
2066 }
2067
2068 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2069 netdev_err(ena_dev->net_device, "Device isn't ready, can't reset device\n");
2070 return -EINVAL;
2071 }
2072
2073 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2074 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2075 if (timeout == 0) {
2076 netdev_err(ena_dev->net_device, "Invalid timeout value\n");
2077 return -EINVAL;
2078 }
2079
2080 /* start reset */
2081 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2082 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2083 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2084 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2085
2086 /* Write again the MMIO read request address */
2087 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2088
2089 rc = wait_for_reset_state(ena_dev, timeout,
2090 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2091 if (rc != 0) {
2092 netdev_err(ena_dev->net_device, "Reset indication didn't turn on\n");
2093 return rc;
2094 }
2095
2096 /* reset done */
2097 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2098 rc = wait_for_reset_state(ena_dev, timeout, 0);
2099 if (rc != 0) {
2100 netdev_err(ena_dev->net_device, "Reset indication didn't turn off\n");
2101 return rc;
2102 }
2103
2104 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2105 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2106 if (timeout)
2107 /* the resolution of timeout reg is 100ms */
2108 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2109 else
2110 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2111
2112 return 0;
2113 }
2114
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)2115 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2116 struct ena_com_stats_ctx *ctx,
2117 enum ena_admin_get_stats_type type)
2118 {
2119 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2120 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2121 struct ena_com_admin_queue *admin_queue;
2122 int ret;
2123
2124 admin_queue = &ena_dev->admin_queue;
2125
2126 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2127 get_cmd->aq_common_descriptor.flags = 0;
2128 get_cmd->type = type;
2129
2130 ret = ena_com_execute_admin_command(admin_queue,
2131 (struct ena_admin_aq_entry *)get_cmd,
2132 sizeof(*get_cmd),
2133 (struct ena_admin_acq_entry *)get_resp,
2134 sizeof(*get_resp));
2135
2136 if (unlikely(ret))
2137 netdev_err(ena_dev->net_device, "Failed to get stats. error: %d\n", ret);
2138
2139 return ret;
2140 }
2141
ena_com_get_eni_stats(struct ena_com_dev * ena_dev,struct ena_admin_eni_stats * stats)2142 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2143 struct ena_admin_eni_stats *stats)
2144 {
2145 struct ena_com_stats_ctx ctx;
2146 int ret;
2147
2148 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) {
2149 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n",
2150 ENA_ADMIN_ENI_STATS);
2151 return -EOPNOTSUPP;
2152 }
2153
2154 memset(&ctx, 0x0, sizeof(ctx));
2155 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2156 if (likely(ret == 0))
2157 memcpy(stats, &ctx.get_resp.u.eni_stats,
2158 sizeof(ctx.get_resp.u.eni_stats));
2159
2160 return ret;
2161 }
2162
ena_com_get_dev_basic_stats(struct ena_com_dev * ena_dev,struct ena_admin_basic_stats * stats)2163 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2164 struct ena_admin_basic_stats *stats)
2165 {
2166 struct ena_com_stats_ctx ctx;
2167 int ret;
2168
2169 memset(&ctx, 0x0, sizeof(ctx));
2170 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2171 if (likely(ret == 0))
2172 memcpy(stats, &ctx.get_resp.u.basic_stats,
2173 sizeof(ctx.get_resp.u.basic_stats));
2174
2175 return ret;
2176 }
2177
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,u32 mtu)2178 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu)
2179 {
2180 struct ena_com_admin_queue *admin_queue;
2181 struct ena_admin_set_feat_cmd cmd;
2182 struct ena_admin_set_feat_resp resp;
2183 int ret;
2184
2185 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2186 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", ENA_ADMIN_MTU);
2187 return -EOPNOTSUPP;
2188 }
2189
2190 memset(&cmd, 0x0, sizeof(cmd));
2191 admin_queue = &ena_dev->admin_queue;
2192
2193 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2194 cmd.aq_common_descriptor.flags = 0;
2195 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2196 cmd.u.mtu.mtu = mtu;
2197
2198 ret = ena_com_execute_admin_command(admin_queue,
2199 (struct ena_admin_aq_entry *)&cmd,
2200 sizeof(cmd),
2201 (struct ena_admin_acq_entry *)&resp,
2202 sizeof(resp));
2203
2204 if (unlikely(ret))
2205 netdev_err(ena_dev->net_device, "Failed to set mtu %d. error: %d\n", mtu, ret);
2206
2207 return ret;
2208 }
2209
ena_com_get_offload_settings(struct ena_com_dev * ena_dev,struct ena_admin_feature_offload_desc * offload)2210 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2211 struct ena_admin_feature_offload_desc *offload)
2212 {
2213 int ret;
2214 struct ena_admin_get_feat_resp resp;
2215
2216 ret = ena_com_get_feature(ena_dev, &resp,
2217 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2218 if (unlikely(ret)) {
2219 netdev_err(ena_dev->net_device, "Failed to get offload capabilities %d\n", ret);
2220 return ret;
2221 }
2222
2223 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2224
2225 return 0;
2226 }
2227
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2228 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2229 {
2230 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2231 struct ena_rss *rss = &ena_dev->rss;
2232 struct ena_admin_set_feat_cmd cmd;
2233 struct ena_admin_set_feat_resp resp;
2234 struct ena_admin_get_feat_resp get_resp;
2235 int ret;
2236
2237 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) {
2238 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2239 ENA_ADMIN_RSS_HASH_FUNCTION);
2240 return -EOPNOTSUPP;
2241 }
2242
2243 /* Validate hash function is supported */
2244 ret = ena_com_get_feature(ena_dev, &get_resp,
2245 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2246 if (unlikely(ret))
2247 return ret;
2248
2249 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2250 netdev_err(ena_dev->net_device, "Func hash %d isn't supported by device, abort\n",
2251 rss->hash_func);
2252 return -EOPNOTSUPP;
2253 }
2254
2255 memset(&cmd, 0x0, sizeof(cmd));
2256
2257 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2258 cmd.aq_common_descriptor.flags =
2259 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2260 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2261 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2262 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2263
2264 ret = ena_com_mem_addr_set(ena_dev,
2265 &cmd.control_buffer.address,
2266 rss->hash_key_dma_addr);
2267 if (unlikely(ret)) {
2268 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2269 return ret;
2270 }
2271
2272 cmd.control_buffer.length = sizeof(*rss->hash_key);
2273
2274 ret = ena_com_execute_admin_command(admin_queue,
2275 (struct ena_admin_aq_entry *)&cmd,
2276 sizeof(cmd),
2277 (struct ena_admin_acq_entry *)&resp,
2278 sizeof(resp));
2279 if (unlikely(ret)) {
2280 netdev_err(ena_dev->net_device, "Failed to set hash function %d. error: %d\n",
2281 rss->hash_func, ret);
2282 return -EINVAL;
2283 }
2284
2285 return 0;
2286 }
2287
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2288 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2289 enum ena_admin_hash_functions func,
2290 const u8 *key, u16 key_len, u32 init_val)
2291 {
2292 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2293 struct ena_admin_get_feat_resp get_resp;
2294 enum ena_admin_hash_functions old_func;
2295 struct ena_rss *rss = &ena_dev->rss;
2296 int rc;
2297
2298 hash_key = rss->hash_key;
2299
2300 /* Make sure size is a mult of DWs */
2301 if (unlikely(key_len & 0x3))
2302 return -EINVAL;
2303
2304 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2305 ENA_ADMIN_RSS_HASH_FUNCTION,
2306 rss->hash_key_dma_addr,
2307 sizeof(*rss->hash_key), 0);
2308 if (unlikely(rc))
2309 return rc;
2310
2311 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2312 netdev_err(ena_dev->net_device, "Flow hash function %d isn't supported\n", func);
2313 return -EOPNOTSUPP;
2314 }
2315
2316 if ((func == ENA_ADMIN_TOEPLITZ) && key) {
2317 if (key_len != sizeof(hash_key->key)) {
2318 netdev_err(ena_dev->net_device,
2319 "key len (%u) doesn't equal the supported size (%zu)\n", key_len,
2320 sizeof(hash_key->key));
2321 return -EINVAL;
2322 }
2323 memcpy(hash_key->key, key, key_len);
2324 hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
2325 }
2326
2327 rss->hash_init_val = init_val;
2328 old_func = rss->hash_func;
2329 rss->hash_func = func;
2330 rc = ena_com_set_hash_function(ena_dev);
2331
2332 /* Restore the old function */
2333 if (unlikely(rc))
2334 rss->hash_func = old_func;
2335
2336 return rc;
2337 }
2338
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func)2339 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2340 enum ena_admin_hash_functions *func)
2341 {
2342 struct ena_rss *rss = &ena_dev->rss;
2343 struct ena_admin_get_feat_resp get_resp;
2344 int rc;
2345
2346 if (unlikely(!func))
2347 return -EINVAL;
2348
2349 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2350 ENA_ADMIN_RSS_HASH_FUNCTION,
2351 rss->hash_key_dma_addr,
2352 sizeof(*rss->hash_key), 0);
2353 if (unlikely(rc))
2354 return rc;
2355
2356 /* ffs() returns 1 in case the lsb is set */
2357 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2358 if (rss->hash_func)
2359 rss->hash_func--;
2360
2361 *func = rss->hash_func;
2362
2363 return 0;
2364 }
2365
ena_com_get_hash_key(struct ena_com_dev * ena_dev,u8 * key)2366 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2367 {
2368 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2369 ena_dev->rss.hash_key;
2370
2371 if (key)
2372 memcpy(key, hash_key->key,
2373 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0]));
2374
2375 return 0;
2376 }
2377
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2378 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2379 enum ena_admin_flow_hash_proto proto,
2380 u16 *fields)
2381 {
2382 struct ena_rss *rss = &ena_dev->rss;
2383 struct ena_admin_get_feat_resp get_resp;
2384 int rc;
2385
2386 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2387 ENA_ADMIN_RSS_HASH_INPUT,
2388 rss->hash_ctrl_dma_addr,
2389 sizeof(*rss->hash_ctrl), 0);
2390 if (unlikely(rc))
2391 return rc;
2392
2393 if (fields)
2394 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2395
2396 return 0;
2397 }
2398
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2399 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2400 {
2401 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2402 struct ena_rss *rss = &ena_dev->rss;
2403 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2404 struct ena_admin_set_feat_cmd cmd;
2405 struct ena_admin_set_feat_resp resp;
2406 int ret;
2407
2408 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) {
2409 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2410 ENA_ADMIN_RSS_HASH_INPUT);
2411 return -EOPNOTSUPP;
2412 }
2413
2414 memset(&cmd, 0x0, sizeof(cmd));
2415
2416 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2417 cmd.aq_common_descriptor.flags =
2418 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2419 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2420 cmd.u.flow_hash_input.enabled_input_sort =
2421 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2422 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2423
2424 ret = ena_com_mem_addr_set(ena_dev,
2425 &cmd.control_buffer.address,
2426 rss->hash_ctrl_dma_addr);
2427 if (unlikely(ret)) {
2428 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2429 return ret;
2430 }
2431 cmd.control_buffer.length = sizeof(*hash_ctrl);
2432
2433 ret = ena_com_execute_admin_command(admin_queue,
2434 (struct ena_admin_aq_entry *)&cmd,
2435 sizeof(cmd),
2436 (struct ena_admin_acq_entry *)&resp,
2437 sizeof(resp));
2438 if (unlikely(ret))
2439 netdev_err(ena_dev->net_device, "Failed to set hash input. error: %d\n", ret);
2440
2441 return ret;
2442 }
2443
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2444 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2445 {
2446 struct ena_rss *rss = &ena_dev->rss;
2447 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2448 rss->hash_ctrl;
2449 u16 available_fields = 0;
2450 int rc, i;
2451
2452 /* Get the supported hash input */
2453 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2454 if (unlikely(rc))
2455 return rc;
2456
2457 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2458 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2459 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2460
2461 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2462 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2463 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2464
2465 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2466 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2467 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2468
2469 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2470 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2471 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2472
2473 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2474 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2475
2476 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2477 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2478
2479 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2480 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2481
2482 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2483 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2484
2485 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2486 available_fields = hash_ctrl->selected_fields[i].fields &
2487 hash_ctrl->supported_fields[i].fields;
2488 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2489 netdev_err(ena_dev->net_device,
2490 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2491 i, hash_ctrl->supported_fields[i].fields,
2492 hash_ctrl->selected_fields[i].fields);
2493 return -EOPNOTSUPP;
2494 }
2495 }
2496
2497 rc = ena_com_set_hash_ctrl(ena_dev);
2498
2499 /* In case of failure, restore the old hash ctrl */
2500 if (unlikely(rc))
2501 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2502
2503 return rc;
2504 }
2505
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2506 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2507 enum ena_admin_flow_hash_proto proto,
2508 u16 hash_fields)
2509 {
2510 struct ena_rss *rss = &ena_dev->rss;
2511 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2512 u16 supported_fields;
2513 int rc;
2514
2515 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2516 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n", proto);
2517 return -EINVAL;
2518 }
2519
2520 /* Get the ctrl table */
2521 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2522 if (unlikely(rc))
2523 return rc;
2524
2525 /* Make sure all the fields are supported */
2526 supported_fields = hash_ctrl->supported_fields[proto].fields;
2527 if ((hash_fields & supported_fields) != hash_fields) {
2528 netdev_err(ena_dev->net_device,
2529 "Proto %d doesn't support the required fields %x. supports only: %x\n",
2530 proto, hash_fields, supported_fields);
2531 }
2532
2533 hash_ctrl->selected_fields[proto].fields = hash_fields;
2534
2535 rc = ena_com_set_hash_ctrl(ena_dev);
2536
2537 /* In case of failure, restore the old hash ctrl */
2538 if (unlikely(rc))
2539 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2540
2541 return 0;
2542 }
2543
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2544 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2545 u16 entry_idx, u16 entry_value)
2546 {
2547 struct ena_rss *rss = &ena_dev->rss;
2548
2549 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2550 return -EINVAL;
2551
2552 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2553 return -EINVAL;
2554
2555 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2556
2557 return 0;
2558 }
2559
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2560 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2561 {
2562 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2563 struct ena_rss *rss = &ena_dev->rss;
2564 struct ena_admin_set_feat_cmd cmd;
2565 struct ena_admin_set_feat_resp resp;
2566 int ret;
2567
2568 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) {
2569 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2570 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG);
2571 return -EOPNOTSUPP;
2572 }
2573
2574 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2575 if (ret) {
2576 netdev_err(ena_dev->net_device,
2577 "Failed to convert host indirection table to device table\n");
2578 return ret;
2579 }
2580
2581 memset(&cmd, 0x0, sizeof(cmd));
2582
2583 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2584 cmd.aq_common_descriptor.flags =
2585 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2586 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG;
2587 cmd.u.ind_table.size = rss->tbl_log_size;
2588 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2589
2590 ret = ena_com_mem_addr_set(ena_dev,
2591 &cmd.control_buffer.address,
2592 rss->rss_ind_tbl_dma_addr);
2593 if (unlikely(ret)) {
2594 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2595 return ret;
2596 }
2597
2598 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2599 sizeof(struct ena_admin_rss_ind_table_entry);
2600
2601 ret = ena_com_execute_admin_command(admin_queue,
2602 (struct ena_admin_aq_entry *)&cmd,
2603 sizeof(cmd),
2604 (struct ena_admin_acq_entry *)&resp,
2605 sizeof(resp));
2606
2607 if (unlikely(ret))
2608 netdev_err(ena_dev->net_device, "Failed to set indirect table. error: %d\n", ret);
2609
2610 return ret;
2611 }
2612
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2613 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2614 {
2615 struct ena_rss *rss = &ena_dev->rss;
2616 struct ena_admin_get_feat_resp get_resp;
2617 u32 tbl_size;
2618 int i, rc;
2619
2620 tbl_size = (1ULL << rss->tbl_log_size) *
2621 sizeof(struct ena_admin_rss_ind_table_entry);
2622
2623 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2624 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG,
2625 rss->rss_ind_tbl_dma_addr,
2626 tbl_size, 0);
2627 if (unlikely(rc))
2628 return rc;
2629
2630 if (!ind_tbl)
2631 return 0;
2632
2633 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2634 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2635
2636 return 0;
2637 }
2638
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2639 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2640 {
2641 int rc;
2642
2643 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2644
2645 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2646 if (unlikely(rc))
2647 goto err_indr_tbl;
2648
2649 /* The following function might return unsupported in case the
2650 * device doesn't support setting the key / hash function. We can safely
2651 * ignore this error and have indirection table support only.
2652 */
2653 rc = ena_com_hash_key_allocate(ena_dev);
2654 if (likely(!rc))
2655 ena_com_hash_key_fill_default_key(ena_dev);
2656 else if (rc != -EOPNOTSUPP)
2657 goto err_hash_key;
2658
2659 rc = ena_com_hash_ctrl_init(ena_dev);
2660 if (unlikely(rc))
2661 goto err_hash_ctrl;
2662
2663 return 0;
2664
2665 err_hash_ctrl:
2666 ena_com_hash_key_destroy(ena_dev);
2667 err_hash_key:
2668 ena_com_indirect_table_destroy(ena_dev);
2669 err_indr_tbl:
2670
2671 return rc;
2672 }
2673
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2674 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2675 {
2676 ena_com_indirect_table_destroy(ena_dev);
2677 ena_com_hash_key_destroy(ena_dev);
2678 ena_com_hash_ctrl_destroy(ena_dev);
2679
2680 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2681 }
2682
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2683 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2684 {
2685 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2686
2687 host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K,
2688 &host_attr->host_info_dma_addr, GFP_KERNEL);
2689 if (unlikely(!host_attr->host_info))
2690 return -ENOMEM;
2691
2692 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2693 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2694 (ENA_COMMON_SPEC_VERSION_MINOR));
2695
2696 return 0;
2697 }
2698
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)2699 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2700 u32 debug_area_size)
2701 {
2702 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2703
2704 host_attr->debug_area_virt_addr =
2705 dma_alloc_coherent(ena_dev->dmadev, debug_area_size,
2706 &host_attr->debug_area_dma_addr, GFP_KERNEL);
2707 if (unlikely(!host_attr->debug_area_virt_addr)) {
2708 host_attr->debug_area_size = 0;
2709 return -ENOMEM;
2710 }
2711
2712 host_attr->debug_area_size = debug_area_size;
2713
2714 return 0;
2715 }
2716
ena_com_delete_host_info(struct ena_com_dev * ena_dev)2717 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2718 {
2719 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2720
2721 if (host_attr->host_info) {
2722 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2723 host_attr->host_info_dma_addr);
2724 host_attr->host_info = NULL;
2725 }
2726 }
2727
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)2728 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2729 {
2730 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2731
2732 if (host_attr->debug_area_virt_addr) {
2733 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2734 host_attr->debug_area_virt_addr, host_attr->debug_area_dma_addr);
2735 host_attr->debug_area_virt_addr = NULL;
2736 }
2737 }
2738
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)2739 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2740 {
2741 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2742 struct ena_com_admin_queue *admin_queue;
2743 struct ena_admin_set_feat_cmd cmd;
2744 struct ena_admin_set_feat_resp resp;
2745
2746 int ret;
2747
2748 /* Host attribute config is called before ena_com_get_dev_attr_feat
2749 * so ena_com can't check if the feature is supported.
2750 */
2751
2752 memset(&cmd, 0x0, sizeof(cmd));
2753 admin_queue = &ena_dev->admin_queue;
2754
2755 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2756 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2757
2758 ret = ena_com_mem_addr_set(ena_dev,
2759 &cmd.u.host_attr.debug_ba,
2760 host_attr->debug_area_dma_addr);
2761 if (unlikely(ret)) {
2762 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2763 return ret;
2764 }
2765
2766 ret = ena_com_mem_addr_set(ena_dev,
2767 &cmd.u.host_attr.os_info_ba,
2768 host_attr->host_info_dma_addr);
2769 if (unlikely(ret)) {
2770 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2771 return ret;
2772 }
2773
2774 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2775
2776 ret = ena_com_execute_admin_command(admin_queue,
2777 (struct ena_admin_aq_entry *)&cmd,
2778 sizeof(cmd),
2779 (struct ena_admin_acq_entry *)&resp,
2780 sizeof(resp));
2781
2782 if (unlikely(ret))
2783 netdev_err(ena_dev->net_device, "Failed to set host attributes: %d\n", ret);
2784
2785 return ret;
2786 }
2787
2788 /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)2789 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2790 {
2791 return ena_com_check_supported_feature_id(ena_dev,
2792 ENA_ADMIN_INTERRUPT_MODERATION);
2793 }
2794
ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev * ena_dev,u32 coalesce_usecs,u32 intr_delay_resolution,u32 * intr_moder_interval)2795 static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev,
2796 u32 coalesce_usecs,
2797 u32 intr_delay_resolution,
2798 u32 *intr_moder_interval)
2799 {
2800 if (!intr_delay_resolution) {
2801 netdev_err(ena_dev->net_device, "Illegal interrupt delay granularity value\n");
2802 return -EFAULT;
2803 }
2804
2805 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2806
2807 return 0;
2808 }
2809
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)2810 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2811 u32 tx_coalesce_usecs)
2812 {
2813 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2814 tx_coalesce_usecs,
2815 ena_dev->intr_delay_resolution,
2816 &ena_dev->intr_moder_tx_interval);
2817 }
2818
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)2819 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2820 u32 rx_coalesce_usecs)
2821 {
2822 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2823 rx_coalesce_usecs,
2824 ena_dev->intr_delay_resolution,
2825 &ena_dev->intr_moder_rx_interval);
2826 }
2827
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)2828 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2829 {
2830 struct ena_admin_get_feat_resp get_resp;
2831 u16 delay_resolution;
2832 int rc;
2833
2834 rc = ena_com_get_feature(ena_dev, &get_resp,
2835 ENA_ADMIN_INTERRUPT_MODERATION, 0);
2836
2837 if (rc) {
2838 if (rc == -EOPNOTSUPP) {
2839 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2840 ENA_ADMIN_INTERRUPT_MODERATION);
2841 rc = 0;
2842 } else {
2843 netdev_err(ena_dev->net_device,
2844 "Failed to get interrupt moderation admin cmd. rc: %d\n", rc);
2845 }
2846
2847 /* no moderation supported, disable adaptive support */
2848 ena_com_disable_adaptive_moderation(ena_dev);
2849 return rc;
2850 }
2851
2852 /* if moderation is supported by device we set adaptive moderation */
2853 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2854 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2855
2856 /* Disable adaptive moderation by default - can be enabled later */
2857 ena_com_disable_adaptive_moderation(ena_dev);
2858
2859 return 0;
2860 }
2861
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)2862 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2863 {
2864 return ena_dev->intr_moder_tx_interval;
2865 }
2866
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)2867 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2868 {
2869 return ena_dev->intr_moder_rx_interval;
2870 }
2871
ena_com_config_dev_mode(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)2872 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2873 struct ena_admin_feature_llq_desc *llq_features,
2874 struct ena_llq_configurations *llq_default_cfg)
2875 {
2876 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
2877 int rc;
2878
2879 if (!llq_features->max_llq_num) {
2880 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2881 return 0;
2882 }
2883
2884 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2885 if (rc)
2886 return rc;
2887
2888 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2889 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2890
2891 if (unlikely(ena_dev->tx_max_header_size == 0)) {
2892 netdev_err(ena_dev->net_device, "The size of the LLQ entry is smaller than needed\n");
2893 return -EINVAL;
2894 }
2895
2896 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2897
2898 return 0;
2899 }
2900