xref: /openbmc/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * (C) Copyright 2013
4   * Texas Instruments Incorporated
5   *
6   * Nishant Kamat <nskamat@ti.com>
7   * Lokesh Vutla <lokeshvutla@ti.com>
8   */
9  #ifndef _MUX_DRA7XX_H_
10  #define _MUX_DRA7XX_H_
11  
12  #include <asm/types.h>
13  
14  #define PULL_ENA		(0 << 16)
15  #define PULL_DIS		(1 << 16)
16  #define PULL_UP			(1 << 17)
17  #define INPUT_EN		(1 << 18)
18  #define SLEWCONTROL		(1 << 19)
19  
20  /* Active pin states */
21  #define PIN_OUTPUT		(0 | PULL_DIS)
22  #define PIN_OUTPUT_PULLUP	(PULL_UP)
23  #define PIN_OUTPUT_PULLDOWN	(0)
24  #define PIN_INPUT		(INPUT_EN | PULL_DIS)
25  #define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
26  #define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
27  #define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
28  
29  #define M0	0
30  #define M1	1
31  #define M2	2
32  #define M3	3
33  #define M4	4
34  #define M5	5
35  #define M6	6
36  #define M7	7
37  #define M8	8
38  #define M9	9
39  #define M10	10
40  #define M11	11
41  #define M12	12
42  #define M13	13
43  #define M14	14
44  #define M15	15
45  
46  #define MODE_SELECT		(1 << 8)
47  #define DELAYMODE_SHIFT		4
48  
49  #define MANUAL_MODE	MODE_SELECT
50  
51  #define VIRTUAL_MODE0	(MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
52  #define VIRTUAL_MODE1	(MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
53  #define VIRTUAL_MODE2	(MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
54  #define VIRTUAL_MODE3	(MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
55  #define VIRTUAL_MODE4	(MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
56  #define VIRTUAL_MODE5	(MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
57  #define VIRTUAL_MODE6	(MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
58  #define VIRTUAL_MODE7	(MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
59  #define VIRTUAL_MODE8	(MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
60  #define VIRTUAL_MODE9	(MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
61  #define VIRTUAL_MODE10	(MODE_SELECT | (0xa << DELAYMODE_SHIFT))
62  #define VIRTUAL_MODE11	(MODE_SELECT | (0xb << DELAYMODE_SHIFT))
63  #define VIRTUAL_MODE12	(MODE_SELECT | (0xc << DELAYMODE_SHIFT))
64  #define VIRTUAL_MODE13	(MODE_SELECT | (0xd << DELAYMODE_SHIFT))
65  #define VIRTUAL_MODE14	(MODE_SELECT | (0xe << DELAYMODE_SHIFT))
66  #define VIRTUAL_MODE15	(MODE_SELECT | (0xf << DELAYMODE_SHIFT))
67  
68  #define SAFE_MODE	M15
69  
70  #define GPMC_AD0	0x000
71  #define GPMC_AD1	0x004
72  #define GPMC_AD2	0x008
73  #define GPMC_AD3	0x00C
74  #define GPMC_AD4	0x010
75  #define GPMC_AD5	0x014
76  #define GPMC_AD6	0x018
77  #define GPMC_AD7	0x01C
78  #define GPMC_AD8	0x020
79  #define GPMC_AD9	0x024
80  #define GPMC_AD10	0x028
81  #define GPMC_AD11	0x02C
82  #define GPMC_AD12	0x030
83  #define GPMC_AD13	0x034
84  #define GPMC_AD14	0x038
85  #define GPMC_AD15	0x03C
86  #define GPMC_A0		0x040
87  #define GPMC_A1		0x044
88  #define GPMC_A2		0x048
89  #define GPMC_A3		0x04C
90  #define GPMC_A4		0x050
91  #define GPMC_A5		0x054
92  #define GPMC_A6		0x058
93  #define GPMC_A7		0x05C
94  #define GPMC_A8		0x060
95  #define GPMC_A9		0x064
96  #define GPMC_A10	0x068
97  #define GPMC_A11	0x06C
98  #define GPMC_A12	0x070
99  #define GPMC_A13	0x074
100  #define GPMC_A14	0x078
101  #define GPMC_A15	0x07C
102  #define GPMC_A16	0x080
103  #define GPMC_A17	0x084
104  #define GPMC_A18	0x088
105  #define GPMC_A19	0x08C
106  #define GPMC_A20	0x090
107  #define GPMC_A21	0x094
108  #define GPMC_A22	0x098
109  #define GPMC_A23	0x09C
110  #define GPMC_A24	0x0A0
111  #define GPMC_A25	0x0A4
112  #define GPMC_A26	0x0A8
113  #define GPMC_A27	0x0AC
114  #define GPMC_CS1	0x0B0
115  #define GPMC_CS0	0x0B4
116  #define GPMC_CS2	0x0B8
117  #define GPMC_CS3	0x0BC
118  #define GPMC_CLK	0x0C0
119  #define GPMC_ADVN_ALE	0x0C4
120  #define GPMC_OEN_REN	0x0C8
121  #define GPMC_WEN	0x0CC
122  #define GPMC_BEN0	0x0D0
123  #define GPMC_BEN1	0x0D4
124  #define GPMC_WAIT0	0x0D8
125  #define VIN1A_CLK0	0x0DC
126  #define VIN1B_CLK1	0x0E0
127  #define VIN1A_DE0	0x0E4
128  #define VIN1A_FLD0	0x0E8
129  #define VIN1A_HSYNC0	0x0EC
130  #define VIN1A_VSYNC0	0x0F0
131  #define VIN1A_D0	0x0F4
132  #define VIN1A_D1	0x0F8
133  #define VIN1A_D2	0x0FC
134  #define VIN1A_D3	0x100
135  #define VIN1A_D4	0x104
136  #define VIN1A_D5	0x108
137  #define VIN1A_D6	0x10C
138  #define VIN1A_D7	0x110
139  #define VIN1A_D8	0x114
140  #define VIN1A_D9	0x118
141  #define VIN1A_D10	0x11C
142  #define VIN1A_D11	0x120
143  #define VIN1A_D12	0x124
144  #define VIN1A_D13	0x128
145  #define VIN1A_D14	0x12C
146  #define VIN1A_D15	0x130
147  #define VIN1A_D16	0x134
148  #define VIN1A_D17	0x138
149  #define VIN1A_D18	0x13C
150  #define VIN1A_D19	0x140
151  #define VIN1A_D20	0x144
152  #define VIN1A_D21	0x148
153  #define VIN1A_D22	0x14C
154  #define VIN1A_D23	0x150
155  #define VIN2A_CLK0	0x154
156  #define VIN2A_DE0	0x158
157  #define VIN2A_FLD0	0x15C
158  #define VIN2A_HSYNC0	0x160
159  #define VIN2A_VSYNC0	0x164
160  #define VIN2A_D0	0x168
161  #define VIN2A_D1	0x16C
162  #define VIN2A_D2	0x170
163  #define VIN2A_D3	0x174
164  #define VIN2A_D4	0x178
165  #define VIN2A_D5	0x17C
166  #define VIN2A_D6	0x180
167  #define VIN2A_D7	0x184
168  #define VIN2A_D8	0x188
169  #define VIN2A_D9	0x18C
170  #define VIN2A_D10	0x190
171  #define VIN2A_D11	0x194
172  #define VIN2A_D12	0x198
173  #define VIN2A_D13	0x19C
174  #define VIN2A_D14	0x1A0
175  #define VIN2A_D15	0x1A4
176  #define VIN2A_D16	0x1A8
177  #define VIN2A_D17	0x1AC
178  #define VIN2A_D18	0x1B0
179  #define VIN2A_D19	0x1B4
180  #define VIN2A_D20	0x1B8
181  #define VIN2A_D21	0x1BC
182  #define VIN2A_D22	0x1C0
183  #define VIN2A_D23	0x1C4
184  #define VOUT1_CLK	0x1C8
185  #define VOUT1_DE	0x1CC
186  #define VOUT1_FLD	0x1D0
187  #define VOUT1_HSYNC	0x1D4
188  #define VOUT1_VSYNC	0x1D8
189  #define VOUT1_D0	0x1DC
190  #define VOUT1_D1	0x1E0
191  #define VOUT1_D2	0x1E4
192  #define VOUT1_D3	0x1E8
193  #define VOUT1_D4	0x1EC
194  #define VOUT1_D5	0x1F0
195  #define VOUT1_D6	0x1F4
196  #define VOUT1_D7	0x1F8
197  #define VOUT1_D8	0x1FC
198  #define VOUT1_D9	0x200
199  #define VOUT1_D10	0x204
200  #define VOUT1_D11	0x208
201  #define VOUT1_D12	0x20C
202  #define VOUT1_D13	0x210
203  #define VOUT1_D14	0x214
204  #define VOUT1_D15	0x218
205  #define VOUT1_D16	0x21C
206  #define VOUT1_D17	0x220
207  #define VOUT1_D18	0x224
208  #define VOUT1_D19	0x228
209  #define VOUT1_D20	0x22C
210  #define VOUT1_D21	0x230
211  #define VOUT1_D22	0x234
212  #define VOUT1_D23	0x238
213  #define MDIO_MCLK	0x23C
214  #define MDIO_D		0x240
215  #define RMII_MHZ_50_CLK	0x244
216  #define UART3_RXD	0x248
217  #define UART3_TXD	0x24C
218  #define RGMII0_TXC	0x250
219  #define RGMII0_TXCTL	0x254
220  #define RGMII0_TXD3	0x258
221  #define RGMII0_TXD2	0x25C
222  #define RGMII0_TXD1	0x260
223  #define RGMII0_TXD0	0x264
224  #define RGMII0_RXC	0x268
225  #define RGMII0_RXCTL	0x26C
226  #define RGMII0_RXD3	0x270
227  #define RGMII0_RXD2	0x274
228  #define RGMII0_RXD1	0x278
229  #define RGMII0_RXD0	0x27C
230  #define USB1_DRVVBUS	0x280
231  #define USB2_DRVVBUS	0x284
232  #define GPIO6_14	0x288
233  #define GPIO6_15	0x28C
234  #define GPIO6_16	0x290
235  #define XREF_CLK0	0x294
236  #define XREF_CLK1	0x298
237  #define XREF_CLK2	0x29C
238  #define XREF_CLK3	0x2A0
239  #define MCASP1_ACLKX	0x2A4
240  #define MCASP1_FSX	0x2A8
241  #define MCASP1_ACLKR	0x2AC
242  #define MCASP1_FSR	0x2B0
243  #define MCASP1_AXR0	0x2B4
244  #define MCASP1_AXR1	0x2B8
245  #define MCASP1_AXR2	0x2BC
246  #define MCASP1_AXR3	0x2C0
247  #define MCASP1_AXR4	0x2C4
248  #define MCASP1_AXR5	0x2C8
249  #define MCASP1_AXR6	0x2CC
250  #define MCASP1_AXR7	0x2D0
251  #define MCASP1_AXR8	0x2D4
252  #define MCASP1_AXR9	0x2D8
253  #define MCASP1_AXR10	0x2DC
254  #define MCASP1_AXR11	0x2E0
255  #define MCASP1_AXR12	0x2E4
256  #define MCASP1_AXR13	0x2E8
257  #define MCASP1_AXR14	0x2EC
258  #define MCASP1_AXR15	0x2F0
259  #define MCASP2_ACLKX	0x2F4
260  #define MCASP2_FSX	0x2F8
261  #define MCASP2_ACLKR	0x2FC
262  #define MCASP2_FSR	0x300
263  #define MCASP2_AXR0	0x304
264  #define MCASP2_AXR1	0x308
265  #define MCASP2_AXR2	0x30C
266  #define MCASP2_AXR3	0x310
267  #define MCASP2_AXR4	0x314
268  #define MCASP2_AXR5	0x318
269  #define MCASP2_AXR6	0x31C
270  #define MCASP2_AXR7	0x320
271  #define MCASP3_ACLKX	0x324
272  #define MCASP3_FSX	0x328
273  #define MCASP3_AXR0	0x32C
274  #define MCASP3_AXR1	0x330
275  #define MCASP4_ACLKX	0x334
276  #define MCASP4_FSX	0x338
277  #define MCASP4_AXR0	0x33C
278  #define MCASP4_AXR1	0x340
279  #define MCASP5_ACLKX	0x344
280  #define MCASP5_FSX	0x348
281  #define MCASP5_AXR0	0x34C
282  #define MCASP5_AXR1	0x350
283  #define MMC1_CLK	0x354
284  #define MMC1_CMD	0x358
285  #define MMC1_DAT0	0x35C
286  #define MMC1_DAT1	0x360
287  #define MMC1_DAT2	0x364
288  #define MMC1_DAT3	0x368
289  #define MMC1_SDCD	0x36C
290  #define MMC1_SDWP	0x370
291  #define GPIO6_10	0x374
292  #define GPIO6_11	0x378
293  #define MMC3_CLK	0x37C
294  #define MMC3_CMD	0x380
295  #define MMC3_DAT0	0x384
296  #define MMC3_DAT1	0x388
297  #define MMC3_DAT2	0x38C
298  #define MMC3_DAT3	0x390
299  #define MMC3_DAT4	0x394
300  #define MMC3_DAT5	0x398
301  #define MMC3_DAT6	0x39C
302  #define MMC3_DAT7	0x3A0
303  #define SPI1_SCLK	0x3A4
304  #define SPI1_D1		0x3A8
305  #define SPI1_D0		0x3AC
306  #define SPI1_CS0	0x3B0
307  #define SPI1_CS1	0x3B4
308  #define SPI1_CS2	0x3B8
309  #define SPI1_CS3	0x3BC
310  #define SPI2_SCLK	0x3C0
311  #define SPI2_D1		0x3C4
312  #define SPI2_D0		0x3C8
313  #define SPI2_CS0	0x3CC
314  #define DCAN1_TX	0x3D0
315  #define DCAN1_RX	0x3D4
316  #define DCAN2_TX	0x3D8
317  #define DCAN2_RX	0x3DC
318  #define UART1_RXD	0x3E0
319  #define UART1_TXD	0x3E4
320  #define UART1_CTSN	0x3E8
321  #define UART1_RTSN	0x3EC
322  #define UART2_RXD	0x3F0
323  #define UART2_TXD	0x3F4
324  #define UART2_CTSN	0x3F8
325  #define UART2_RTSN	0x3FC
326  #define I2C1_SDA	0x400
327  #define I2C1_SCL	0x404
328  #define I2C2_SDA	0x408
329  #define I2C2_SCL	0x40C
330  #define I2C3_SDA	0x410
331  #define I2C3_SCL	0x414
332  #define WAKEUP0		0x418
333  #define WAKEUP1		0x41C
334  #define WAKEUP2		0x420
335  #define WAKEUP3		0x424
336  #define ON_OFF		0x428
337  #define RTC_PORZ	0x42C
338  #define TMS		0x430
339  #define TDI		0x434
340  #define TDO		0x438
341  #define TCLK		0x43C
342  #define TRSTN		0x440
343  #define RTCK		0x444
344  #define EMU0		0x448
345  #define EMU1		0x44C
346  #define EMU2		0x450
347  #define EMU3		0x454
348  #define EMU4		0x458
349  #define RESETN		0x45C
350  #define NMIN_DSP	0x460
351  #define RSTOUTN		0x464
352  
353  #define MCAN_SEL_ALT_MASK	0x6000
354  #define MCAN_SEL		0x2000
355  
356  #endif /* _MUX_DRA7XX_H_ */
357