xref: /openbmc/linux/drivers/usb/host/ehci.h (revision dda4b60e)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2001-2002 by David Brownell
4  */
5 
6 #ifndef __LINUX_EHCI_HCD_H
7 #define __LINUX_EHCI_HCD_H
8 
9 /* definitions used for the EHCI driver */
10 
11 /*
12  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
13  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
14  * the host controller implementation.
15  *
16  * To facilitate the strongest possible byte-order checking from "sparse"
17  * and so on, we use __leXX unless that's not practical.
18  */
19 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20 typedef __u32 __bitwise __hc32;
21 typedef __u16 __bitwise __hc16;
22 #else
23 #define __hc32	__le32
24 #define __hc16	__le16
25 #endif
26 
27 /* statistics can be kept for tuning/monitoring */
28 #ifdef CONFIG_DYNAMIC_DEBUG
29 #define EHCI_STATS
30 #endif
31 
32 struct ehci_stats {
33 	/* irq usage */
34 	unsigned long		normal;
35 	unsigned long		error;
36 	unsigned long		iaa;
37 	unsigned long		lost_iaa;
38 
39 	/* termination of urbs from core */
40 	unsigned long		complete;
41 	unsigned long		unlink;
42 };
43 
44 /*
45  * Scheduling and budgeting information for periodic transfers, for both
46  * high-speed devices and full/low-speed devices lying behind a TT.
47  */
48 struct ehci_per_sched {
49 	struct usb_device	*udev;		/* access to the TT */
50 	struct usb_host_endpoint *ep;
51 	struct list_head	ps_list;	/* node on ehci_tt's ps_list */
52 	u16			tt_usecs;	/* time on the FS/LS bus */
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
54 	u16			period;		/* actual period in frames */
55 	u16			phase;		/* actual phase, frame part */
56 	u8			bw_phase;	/* same, for bandwidth
57 						   reservation */
58 	u8			phase_uf;	/* uframe part of the phase */
59 	u8			usecs, c_usecs;	/* times on the HS bus */
60 	u8			bw_uperiod;	/* period in microframes, for
61 						   bandwidth reservation */
62 	u8			bw_period;	/* same, in frames */
63 };
64 #define NO_FRAME	29999			/* frame not assigned yet */
65 
66 /* ehci_hcd->lock guards shared data against other CPUs:
67  *   ehci_hcd:	async, unlink, periodic (and shadow), ...
68  *   usb_host_endpoint: hcpriv
69  *   ehci_qh:	qh_next, qtd_list
70  *   ehci_qtd:	qtd_list
71  *
72  * Also, hold this lock when talking to HC registers or
73  * when updating hw_* fields in shared qh/qtd/... structures.
74  */
75 
76 #define	EHCI_MAX_ROOT_PORTS	15		/* see HCS_N_PORTS */
77 
78 /*
79  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
80  * controller may be doing DMA.  Lower values mean there's no DMA.
81  */
82 enum ehci_rh_state {
83 	EHCI_RH_HALTED,
84 	EHCI_RH_SUSPENDED,
85 	EHCI_RH_RUNNING,
86 	EHCI_RH_STOPPING
87 };
88 
89 /*
90  * Timer events, ordered by increasing delay length.
91  * Always update event_delays_ns[] and event_handlers[] (defined in
92  * ehci-timer.c) in parallel with this list.
93  */
94 enum ehci_hrtimer_event {
95 	EHCI_HRTIMER_POLL_ASS,		/* Poll for async schedule off */
96 	EHCI_HRTIMER_POLL_PSS,		/* Poll for periodic schedule off */
97 	EHCI_HRTIMER_POLL_DEAD,		/* Wait for dead controller to stop */
98 	EHCI_HRTIMER_UNLINK_INTR,	/* Wait for interrupt QH unlink */
99 	EHCI_HRTIMER_FREE_ITDS,		/* Wait for unused iTDs and siTDs */
100 	EHCI_HRTIMER_ACTIVE_UNLINK,	/* Wait while unlinking an active QH */
101 	EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
102 	EHCI_HRTIMER_ASYNC_UNLINKS,	/* Unlink empty async QHs */
103 	EHCI_HRTIMER_IAA_WATCHDOG,	/* Handle lost IAA interrupts */
104 	EHCI_HRTIMER_DISABLE_PERIODIC,	/* Wait to disable periodic sched */
105 	EHCI_HRTIMER_DISABLE_ASYNC,	/* Wait to disable async sched */
106 	EHCI_HRTIMER_IO_WATCHDOG,	/* Check for missing IRQs */
107 	EHCI_HRTIMER_NUM_EVENTS		/* Must come last */
108 };
109 #define EHCI_HRTIMER_NO_EVENT	99
110 
111 struct ehci_hcd {			/* one per controller */
112 	/* timing support */
113 	enum ehci_hrtimer_event	next_hrtimer_event;
114 	unsigned		enabled_hrtimer_events;
115 	ktime_t			hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 	struct hrtimer		hrtimer;
117 
118 	int			PSS_poll_count;
119 	int			ASS_poll_count;
120 	int			died_poll_count;
121 
122 	/* glue to PCI and HCD framework */
123 	struct ehci_caps __iomem *caps;
124 	struct ehci_regs __iomem *regs;
125 	struct ehci_dbg_port __iomem *debug;
126 
127 	__u32			hcs_params;	/* cached register copy */
128 	spinlock_t		lock;
129 	enum ehci_rh_state	rh_state;
130 
131 	/* general schedule support */
132 	bool			scanning:1;
133 	bool			need_rescan:1;
134 	bool			intr_unlinking:1;
135 	bool			iaa_in_progress:1;
136 	bool			async_unlinking:1;
137 	bool			shutdown:1;
138 	struct ehci_qh		*qh_scan_next;
139 
140 	/* async schedule support */
141 	struct ehci_qh		*async;
142 	struct ehci_qh		*dummy;		/* For AMD quirk use */
143 	struct list_head	async_unlink;
144 	struct list_head	async_idle;
145 	unsigned		async_unlink_cycle;
146 	unsigned		async_count;	/* async activity count */
147 	__hc32			old_current;	/* Test for QH becoming */
148 	__hc32			old_token;	/*  inactive during unlink */
149 
150 	/* periodic schedule support */
151 #define	DEFAULT_I_TDPS		1024		/* some HCs can do less */
152 	unsigned		periodic_size;
153 	__hc32			*periodic;	/* hw periodic table */
154 	dma_addr_t		periodic_dma;
155 	struct list_head	intr_qh_list;
156 	unsigned		i_thresh;	/* uframes HC might cache */
157 
158 	union ehci_shadow	*pshadow;	/* mirror hw periodic table */
159 	struct list_head	intr_unlink_wait;
160 	struct list_head	intr_unlink;
161 	unsigned		intr_unlink_wait_cycle;
162 	unsigned		intr_unlink_cycle;
163 	unsigned		now_frame;	/* frame from HC hardware */
164 	unsigned		last_iso_frame;	/* last frame scanned for iso */
165 	unsigned		intr_count;	/* intr activity count */
166 	unsigned		isoc_count;	/* isoc activity count */
167 	unsigned		periodic_count;	/* periodic activity count */
168 	unsigned		uframe_periodic_max; /* max periodic time per uframe */
169 
170 
171 	/* list of itds & sitds completed while now_frame was still active */
172 	struct list_head	cached_itd_list;
173 	struct ehci_itd		*last_itd_to_free;
174 	struct list_head	cached_sitd_list;
175 	struct ehci_sitd	*last_sitd_to_free;
176 
177 	/* per root hub port */
178 	unsigned long		reset_done[EHCI_MAX_ROOT_PORTS];
179 
180 	/* bit vectors (one bit per port) */
181 	unsigned long		bus_suspended;		/* which ports were
182 			already suspended at the start of a bus suspend */
183 	unsigned long		companion_ports;	/* which ports are
184 			dedicated to the companion controller */
185 	unsigned long		owned_ports;		/* which ports are
186 			owned by the companion during a bus suspend */
187 	unsigned long		port_c_suspend;		/* which ports have
188 			the change-suspend feature turned on */
189 	unsigned long		suspended_ports;	/* which ports are
190 			suspended */
191 	unsigned long		resuming_ports;		/* which ports have
192 			started to resume */
193 
194 	/* per-HC memory pools (could be per-bus, but ...) */
195 	struct dma_pool		*qh_pool;	/* qh per active urb */
196 	struct dma_pool		*qtd_pool;	/* one or more per qh */
197 	struct dma_pool		*itd_pool;	/* itd per iso urb */
198 	struct dma_pool		*sitd_pool;	/* sitd per split iso urb */
199 
200 	unsigned		random_frame;
201 	unsigned long		next_statechange;
202 	ktime_t			last_periodic_enable;
203 	u32			command;
204 
205 	/* SILICON QUIRKS */
206 	unsigned		no_selective_suspend:1;
207 	unsigned		has_fsl_port_bug:1; /* FreeScale */
208 	unsigned		has_fsl_hs_errata:1;	/* Freescale HS quirk */
209 	unsigned		has_fsl_susp_errata:1;	/* NXP SUSP quirk */
210 	unsigned		has_ci_pec_bug:1;	/* ChipIdea PEC bug */
211 	unsigned		big_endian_mmio:1;
212 	unsigned		big_endian_desc:1;
213 	unsigned		big_endian_capbase:1;
214 	unsigned		has_amcc_usb23:1;
215 	unsigned		need_io_watchdog:1;
216 	unsigned		amd_pll_fix:1;
217 	unsigned		use_dummy_qh:1;	/* AMD Frame List table quirk*/
218 	unsigned		has_synopsys_hc_bug:1; /* Synopsys HC */
219 	unsigned		frame_index_bug:1; /* MosChip (AKA NetMos) */
220 	unsigned		need_oc_pp_cycle:1; /* MPC834X port power */
221 	unsigned		imx28_write_fix:1; /* For Freescale i.MX28 */
222 	unsigned		spurious_oc:1;
223 	unsigned		is_aspeed:1;
224 	unsigned		zx_wakeup_clear_needed:1;
225 
226 	/* required for usb32 quirk */
227 	#define OHCI_CTRL_HCFS          (3 << 6)
228 	#define OHCI_USB_OPER           (2 << 6)
229 	#define OHCI_USB_SUSPEND        (3 << 6)
230 
231 	#define OHCI_HCCTRL_OFFSET      0x4
232 	#define OHCI_HCCTRL_LEN         0x4
233 	__hc32			*ohci_hcctrl_reg;
234 	unsigned		has_hostpc:1;
235 	unsigned		has_tdi_phy_lpm:1;
236 	unsigned		has_ppcd:1; /* support per-port change bits */
237 	u8			sbrn;		/* packed release number */
238 
239 	/* irq statistics */
240 #ifdef EHCI_STATS
241 	struct ehci_stats	stats;
242 #	define INCR(x) ((x)++)
243 #else
244 #	define INCR(x) do {} while (0)
245 #endif
246 
247 	/* debug files */
248 #ifdef CONFIG_DYNAMIC_DEBUG
249 	struct dentry		*debug_dir;
250 #endif
251 
252 	/* bandwidth usage */
253 #define EHCI_BANDWIDTH_SIZE	64
254 #define EHCI_BANDWIDTH_FRAMES	(EHCI_BANDWIDTH_SIZE >> 3)
255 	u8			bandwidth[EHCI_BANDWIDTH_SIZE];
256 						/* us allocated per uframe */
257 	u8			tt_budget[EHCI_BANDWIDTH_SIZE];
258 						/* us budgeted per uframe */
259 	struct list_head	tt_list;
260 
261 	/* platform-specific data -- must come last */
262 	unsigned long		priv[] __aligned(sizeof(s64));
263 };
264 
265 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_ehci(struct usb_hcd * hcd)266 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
267 {
268 	return (struct ehci_hcd *) (hcd->hcd_priv);
269 }
ehci_to_hcd(struct ehci_hcd * ehci)270 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
271 {
272 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);
273 }
274 
275 /*-------------------------------------------------------------------------*/
276 
277 #include <linux/usb/ehci_def.h>
278 
279 /*-------------------------------------------------------------------------*/
280 
281 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)
282 
283 /*
284  * EHCI Specification 0.95 Section 3.5
285  * QTD: describe data transfer components (buffer, direction, ...)
286  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
287  *
288  * These are associated only with "QH" (Queue Head) structures,
289  * used with control, bulk, and interrupt transfers.
290  */
291 struct ehci_qtd {
292 	/* first part defined by EHCI spec */
293 	__hc32			hw_next;	/* see EHCI 3.5.1 */
294 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
295 	__hc32			hw_token;       /* see EHCI 3.5.3 */
296 #define	QTD_TOGGLE	(1 << 31)	/* data toggle */
297 #define	QTD_LENGTH(tok)	(((tok)>>16) & 0x7fff)
298 #define	QTD_IOC		(1 << 15)	/* interrupt on complete */
299 #define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
300 #define	QTD_PID(tok)	(((tok)>>8) & 0x3)
301 #define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
302 #define	QTD_STS_HALT	(1 << 6)	/* halted on error */
303 #define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
304 #define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
305 #define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
306 #define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
307 #define	QTD_STS_STS	(1 << 1)	/* split transaction state */
308 #define	QTD_STS_PING	(1 << 0)	/* issue PING? */
309 
310 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)
311 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)
312 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)
313 
314 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
315 	__hc32			hw_buf_hi[5];        /* Appendix B */
316 
317 	/* the rest is HCD-private */
318 	dma_addr_t		qtd_dma;		/* qtd address */
319 	struct list_head	qtd_list;		/* sw qtd list */
320 	struct urb		*urb;			/* qtd's urb */
321 	size_t			length;			/* length of buffer */
322 } __aligned(32);
323 
324 /* mask NakCnt+T in qh->hw_alt_next */
325 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)
326 
327 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
328 
329 /*-------------------------------------------------------------------------*/
330 
331 /* type tag from {qh,itd,sitd,fstn}->hw_next */
332 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))
333 
334 /*
335  * Now the following defines are not converted using the
336  * cpu_to_le32() macro anymore, since we have to support
337  * "dynamic" switching between be and le support, so that the driver
338  * can be used on one system with SoC EHCI controller using big-endian
339  * descriptors as well as a normal little-endian PCI EHCI controller.
340  */
341 /* values for that type tag */
342 #define Q_TYPE_ITD	(0 << 1)
343 #define Q_TYPE_QH	(1 << 1)
344 #define Q_TYPE_SITD	(2 << 1)
345 #define Q_TYPE_FSTN	(3 << 1)
346 
347 /* next async queue entry, or pointer to interrupt/periodic QH */
348 #define QH_NEXT(ehci, dma) \
349 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
350 
351 /* for periodic/async schedules and qtd lists, mark end of list */
352 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
353 
354 /*
355  * Entries in periodic shadow table are pointers to one of four kinds
356  * of data structure.  That's dictated by the hardware; a type tag is
357  * encoded in the low bits of the hardware's periodic schedule.  Use
358  * Q_NEXT_TYPE to get the tag.
359  *
360  * For entries in the async schedule, the type tag always says "qh".
361  */
362 union ehci_shadow {
363 	struct ehci_qh		*qh;		/* Q_TYPE_QH */
364 	struct ehci_itd		*itd;		/* Q_TYPE_ITD */
365 	struct ehci_sitd	*sitd;		/* Q_TYPE_SITD */
366 	struct ehci_fstn	*fstn;		/* Q_TYPE_FSTN */
367 	__hc32			*hw_next;	/* (all types) */
368 	void			*ptr;
369 };
370 
371 /*-------------------------------------------------------------------------*/
372 
373 /*
374  * EHCI Specification 0.95 Section 3.6
375  * QH: describes control/bulk/interrupt endpoints
376  * See Fig 3-7 "Queue Head Structure Layout".
377  *
378  * These appear in both the async and (for interrupt) periodic schedules.
379  */
380 
381 /* first part defined by EHCI spec */
382 struct ehci_qh_hw {
383 	__hc32			hw_next;	/* see EHCI 3.6.1 */
384 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
385 #define	QH_CONTROL_EP	(1 << 27)	/* FS/LS control endpoint */
386 #define	QH_HEAD		(1 << 15)	/* Head of async reclamation list */
387 #define	QH_TOGGLE_CTL	(1 << 14)	/* Data toggle control */
388 #define	QH_HIGH_SPEED	(2 << 12)	/* Endpoint speed */
389 #define	QH_LOW_SPEED	(1 << 12)
390 #define	QH_FULL_SPEED	(0 << 12)
391 #define	QH_INACTIVATE	(1 << 7)	/* Inactivate on next transaction */
392 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
393 #define	QH_SMASK	0x000000ff
394 #define	QH_CMASK	0x0000ff00
395 #define	QH_HUBADDR	0x007f0000
396 #define	QH_HUBPORT	0x3f800000
397 #define	QH_MULT		0xc0000000
398 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
399 
400 	/* qtd overlay (hardware parts of a struct ehci_qtd) */
401 	__hc32			hw_qtd_next;
402 	__hc32			hw_alt_next;
403 	__hc32			hw_token;
404 	__hc32			hw_buf[5];
405 	__hc32			hw_buf_hi[5];
406 } __aligned(32);
407 
408 struct ehci_qh {
409 	struct ehci_qh_hw	*hw;		/* Must come first */
410 	/* the rest is HCD-private */
411 	dma_addr_t		qh_dma;		/* address of qh */
412 	union ehci_shadow	qh_next;	/* ptr to qh; or periodic */
413 	struct list_head	qtd_list;	/* sw qtd list */
414 	struct list_head	intr_node;	/* list of intr QHs */
415 	struct ehci_qtd		*dummy;
416 	struct list_head	unlink_node;
417 	struct ehci_per_sched	ps;		/* scheduling info */
418 
419 	unsigned		unlink_cycle;
420 
421 	u8			qh_state;
422 #define	QH_STATE_LINKED		1		/* HC sees this */
423 #define	QH_STATE_UNLINK		2		/* HC may still see this */
424 #define	QH_STATE_IDLE		3		/* HC doesn't see this */
425 #define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on unlink q */
426 #define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
427 
428 	u8			xacterrs;	/* XactErr retry counter */
429 #define	QH_XACTERR_MAX		32		/* XactErr retry limit */
430 
431 	u8			unlink_reason;
432 #define QH_UNLINK_HALTED	0x01		/* Halt flag is set */
433 #define QH_UNLINK_SHORT_READ	0x02		/* Recover from a short read */
434 #define QH_UNLINK_DUMMY_OVERLAY	0x04		/* QH overlayed the dummy TD */
435 #define QH_UNLINK_SHUTDOWN	0x08		/* The HC isn't running */
436 #define QH_UNLINK_QUEUE_EMPTY	0x10		/* Reached end of the queue */
437 #define QH_UNLINK_REQUESTED	0x20		/* Disable, reset, or dequeue */
438 
439 	u8			gap_uf;		/* uframes split/csplit gap */
440 
441 	unsigned		is_out:1;	/* bulk or intr OUT */
442 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
443 	unsigned		dequeue_during_giveback:1;
444 	unsigned		should_be_inactive:1;
445 };
446 
447 /*-------------------------------------------------------------------------*/
448 
449 /* description of one iso transaction (up to 3 KB data if highspeed) */
450 struct ehci_iso_packet {
451 	/* These will be copied to iTD when scheduling */
452 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
453 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
454 	u8			cross;		/* buf crosses pages */
455 	/* for full speed OUT splits */
456 	u32			buf1;
457 };
458 
459 /* temporary schedule data for packets from iso urbs (both speeds)
460  * each packet is one logical usb transaction to the device (not TT),
461  * beginning at stream->next_uframe
462  */
463 struct ehci_iso_sched {
464 	struct list_head	td_list;
465 	unsigned		span;
466 	unsigned		first_packet;
467 	struct ehci_iso_packet	packet[];
468 };
469 
470 /*
471  * ehci_iso_stream - groups all (s)itds for this endpoint.
472  * acts like a qh would, if EHCI had them for ISO.
473  */
474 struct ehci_iso_stream {
475 	/* first field matches ehci_qh, but is NULL */
476 	struct ehci_qh_hw	*hw;
477 
478 	u8			bEndpointAddress;
479 	u8			highspeed;
480 	struct list_head	td_list;	/* queued itds/sitds */
481 	struct list_head	free_list;	/* list of unused itds/sitds */
482 
483 	/* output of (re)scheduling */
484 	struct ehci_per_sched	ps;		/* scheduling info */
485 	unsigned		next_uframe;
486 	__hc32			splits;
487 
488 	/* the rest is derived from the endpoint descriptor,
489 	 * including the extra info for hw_bufp[0..2]
490 	 */
491 	u16			uperiod;	/* period in uframes */
492 	u16			maxp;
493 	unsigned		bandwidth;
494 
495 	/* This is used to initialize iTD's hw_bufp fields */
496 	__hc32			buf0;
497 	__hc32			buf1;
498 	__hc32			buf2;
499 
500 	/* this is used to initialize sITD's tt info */
501 	__hc32			address;
502 };
503 
504 /*-------------------------------------------------------------------------*/
505 
506 /*
507  * EHCI Specification 0.95 Section 3.3
508  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
509  *
510  * Schedule records for high speed iso xfers
511  */
512 struct ehci_itd {
513 	/* first part defined by EHCI spec */
514 	__hc32			hw_next;           /* see EHCI 3.3.1 */
515 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
516 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
517 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
518 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
519 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
520 #define	EHCI_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)
521 #define	EHCI_ITD_IOC		(1 << 15)	/* interrupt on complete */
522 
523 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
524 
525 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
526 	__hc32			hw_bufp_hi[7];	/* Appendix B */
527 
528 	/* the rest is HCD-private */
529 	dma_addr_t		itd_dma;	/* for this itd */
530 	union ehci_shadow	itd_next;	/* ptr to periodic q entry */
531 
532 	struct urb		*urb;
533 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
534 	struct list_head	itd_list;	/* list of stream's itds */
535 
536 	/* any/all hw_transactions here may be used by that urb */
537 	unsigned		frame;		/* where scheduled */
538 	unsigned		pg;
539 	unsigned		index[8];	/* in urb->iso_frame_desc */
540 } __aligned(32);
541 
542 /*-------------------------------------------------------------------------*/
543 
544 /*
545  * EHCI Specification 0.95 Section 3.4
546  * siTD, aka split-transaction isochronous Transfer Descriptor
547  *       ... describe full speed iso xfers through TT in hubs
548  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
549  */
550 struct ehci_sitd {
551 	/* first part defined by EHCI spec */
552 	__hc32			hw_next;
553 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
554 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
555 	__hc32			hw_uframe;		/* EHCI table 3-10 */
556 	__hc32			hw_results;		/* EHCI table 3-11 */
557 #define	SITD_IOC	(1 << 31)	/* interrupt on completion */
558 #define	SITD_PAGE	(1 << 30)	/* buffer 0/1 */
559 #define	SITD_LENGTH(x)	(((x) >> 16) & 0x3ff)
560 #define	SITD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
561 #define	SITD_STS_ERR	(1 << 6)	/* error from TT */
562 #define	SITD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
563 #define	SITD_STS_BABBLE	(1 << 4)	/* device was babbling */
564 #define	SITD_STS_XACT	(1 << 3)	/* illegal IN response */
565 #define	SITD_STS_MMF	(1 << 2)	/* incomplete split transaction */
566 #define	SITD_STS_STS	(1 << 1)	/* split transaction state */
567 
568 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)
569 
570 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
571 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
572 	__hc32			hw_buf_hi[2];		/* Appendix B */
573 
574 	/* the rest is HCD-private */
575 	dma_addr_t		sitd_dma;
576 	union ehci_shadow	sitd_next;	/* ptr to periodic q entry */
577 
578 	struct urb		*urb;
579 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
580 	struct list_head	sitd_list;	/* list of stream's sitds */
581 	unsigned		frame;
582 	unsigned		index;
583 } __aligned(32);
584 
585 /*-------------------------------------------------------------------------*/
586 
587 /*
588  * EHCI Specification 0.96 Section 3.7
589  * Periodic Frame Span Traversal Node (FSTN)
590  *
591  * Manages split interrupt transactions (using TT) that span frame boundaries
592  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
593  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
594  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
595  */
596 struct ehci_fstn {
597 	__hc32			hw_next;	/* any periodic q entry */
598 	__hc32			hw_prev;	/* qh or EHCI_LIST_END */
599 
600 	/* the rest is HCD-private */
601 	dma_addr_t		fstn_dma;
602 	union ehci_shadow	fstn_next;	/* ptr to periodic q entry */
603 } __aligned(32);
604 
605 /*-------------------------------------------------------------------------*/
606 
607 /*
608  * USB-2.0 Specification Sections 11.14 and 11.18
609  * Scheduling and budgeting split transactions using TTs
610  *
611  * A hub can have a single TT for all its ports, or multiple TTs (one for each
612  * port).  The bandwidth and budgeting information for the full/low-speed bus
613  * below each TT is self-contained and independent of the other TTs or the
614  * high-speed bus.
615  *
616  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
617  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
618  * the best-case estimate of the number of full-speed bytes allocated to an
619  * endpoint for each microframe within an allocated frame.
620  *
621  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
622  * keep an up-to-date record, we recompute the budget when it is needed.
623  */
624 
625 struct ehci_tt {
626 	u16			bandwidth[EHCI_BANDWIDTH_FRAMES];
627 
628 	struct list_head	tt_list;	/* List of all ehci_tt's */
629 	struct list_head	ps_list;	/* Items using this TT */
630 	struct usb_tt		*usb_tt;
631 	int			tt_port;	/* TT port number */
632 };
633 
634 /*-------------------------------------------------------------------------*/
635 
636 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
637 
638 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\
639 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
640 
641 #define ehci_prepare_ports_for_controller_resume(ehci)			\
642 		ehci_adjust_port_wakeup_flags(ehci, false, false)
643 
644 /*-------------------------------------------------------------------------*/
645 
646 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
647 
648 /*
649  * Some EHCI controllers have a Transaction Translator built into the
650  * root hub. This is a non-standard feature.  Each controller will need
651  * to add code to the following inline functions, and call them as
652  * needed (mostly in root hub code).
653  */
654 
655 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
656 
657 /* Returns the speed of a device attached to a port on the root hub. */
658 static inline unsigned int
ehci_port_speed(struct ehci_hcd * ehci,unsigned int portsc)659 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
660 {
661 	if (ehci_is_TDI(ehci)) {
662 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
663 		case 0:
664 			return 0;
665 		case 1:
666 			return USB_PORT_STAT_LOW_SPEED;
667 		case 2:
668 		default:
669 			return USB_PORT_STAT_HIGH_SPEED;
670 		}
671 	}
672 	return USB_PORT_STAT_HIGH_SPEED;
673 }
674 
675 #else
676 
677 #define	ehci_is_TDI(e)			(0)
678 
679 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED
680 #endif
681 
682 /*-------------------------------------------------------------------------*/
683 
684 #ifdef CONFIG_PPC_83xx
685 /* Some Freescale processors have an erratum in which the TT
686  * port number in the queue head was 0..N-1 instead of 1..N.
687  */
688 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
689 #else
690 #define	ehci_has_fsl_portno_bug(e)		(0)
691 #endif
692 
693 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
694 
695 #if defined(CONFIG_PPC_85xx)
696 /* Some Freescale processors have an erratum (USB A-005275) in which
697  * incoming packets get corrupted in HS mode
698  */
699 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
700 #else
701 #define ehci_has_fsl_hs_errata(e)	(0)
702 #endif
703 
704 /*
705  * Some Freescale/NXP processors have an erratum (USB A-005697)
706  * in which we need to wait for 10ms for bus to enter suspend mode
707  * after setting SUSP bit.
708  */
709 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
710 
711 /*
712  * Some Freescale/NXP processors using ChipIdea IP have a bug in which
713  * disabling the port (PE is cleared) does not cause PEC to be asserted
714  * when frame babble is detected.
715  */
716 #define ehci_has_ci_pec_bug(e, portsc) \
717 	((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \
718 	 && !(portsc & PORT_PEC) && !(portsc & PORT_PE))
719 
720 /*
721  * While most USB host controllers implement their registers in
722  * little-endian format, a minority (celleb companion chip) implement
723  * them in big endian format.
724  *
725  * This attempts to support either format at compile time without a
726  * runtime penalty, or both formats with the additional overhead
727  * of checking a flag bit.
728  *
729  * ehci_big_endian_capbase is a special quirk for controllers that
730  * implement the HC capability registers as separate registers and not
731  * as fields of a 32-bit register.
732  */
733 
734 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
735 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
736 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
737 #else
738 #define ehci_big_endian_mmio(e)		0
739 #define ehci_big_endian_capbase(e)	0
740 #endif
741 
742 /*
743  * Big-endian read/write functions are arch-specific.
744  * Other arches can be added if/when they're needed.
745  */
746 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
747 #define readl_be(addr)		__raw_readl((__force unsigned *)addr)
748 #define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
749 #endif
750 
ehci_readl(const struct ehci_hcd * ehci,__u32 __iomem * regs)751 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
752 		__u32 __iomem *regs)
753 {
754 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
755 	return ehci_big_endian_mmio(ehci) ?
756 		readl_be(regs) :
757 		readl(regs);
758 #else
759 	return readl(regs);
760 #endif
761 }
762 
763 #ifdef CONFIG_SOC_IMX28
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)764 static inline void imx28_ehci_writel(const unsigned int val,
765 		volatile __u32 __iomem *addr)
766 {
767 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
768 }
769 #else
imx28_ehci_writel(const unsigned int val,volatile __u32 __iomem * addr)770 static inline void imx28_ehci_writel(const unsigned int val,
771 		volatile __u32 __iomem *addr)
772 {
773 }
774 #endif
ehci_writel(const struct ehci_hcd * ehci,const unsigned int val,__u32 __iomem * regs)775 static inline void ehci_writel(const struct ehci_hcd *ehci,
776 		const unsigned int val, __u32 __iomem *regs)
777 {
778 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
779 	ehci_big_endian_mmio(ehci) ?
780 		writel_be(val, regs) :
781 		writel(val, regs);
782 #else
783 	if (ehci->imx28_write_fix)
784 		imx28_ehci_writel(val, regs);
785 	else
786 		writel(val, regs);
787 #endif
788 }
789 
790 /*
791  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
792  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
793  * Other common bits are dependent on has_amcc_usb23 quirk flag.
794  */
795 #ifdef CONFIG_44x
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)796 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
797 {
798 	u32 hc_control;
799 
800 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
801 	if (operational)
802 		hc_control |= OHCI_USB_OPER;
803 	else
804 		hc_control |= OHCI_USB_SUSPEND;
805 
806 	writel_be(hc_control, ehci->ohci_hcctrl_reg);
807 	(void) readl_be(ehci->ohci_hcctrl_reg);
808 }
809 #else
set_ohci_hcfs(struct ehci_hcd * ehci,int operational)810 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
811 { }
812 #endif
813 
814 /*-------------------------------------------------------------------------*/
815 
816 /*
817  * The AMCC 440EPx not only implements its EHCI registers in big-endian
818  * format, but also its DMA data structures (descriptors).
819  *
820  * EHCI controllers accessed through PCI work normally (little-endian
821  * everywhere), so we won't bother supporting a BE-only mode for now.
822  */
823 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
824 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
825 
826 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)827 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
828 {
829 	return ehci_big_endian_desc(ehci)
830 		? (__force __hc32)cpu_to_be32(x)
831 		: (__force __hc32)cpu_to_le32(x);
832 }
833 
834 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)835 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
836 {
837 	return ehci_big_endian_desc(ehci)
838 		? be32_to_cpu((__force __be32)x)
839 		: le32_to_cpu((__force __le32)x);
840 }
841 
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)842 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
843 {
844 	return ehci_big_endian_desc(ehci)
845 		? be32_to_cpup((__force __be32 *)x)
846 		: le32_to_cpup((__force __le32 *)x);
847 }
848 
849 #else
850 
851 /* cpu to ehci */
cpu_to_hc32(const struct ehci_hcd * ehci,const u32 x)852 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
853 {
854 	return cpu_to_le32(x);
855 }
856 
857 /* ehci to cpu */
hc32_to_cpu(const struct ehci_hcd * ehci,const __hc32 x)858 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
859 {
860 	return le32_to_cpu(x);
861 }
862 
hc32_to_cpup(const struct ehci_hcd * ehci,const __hc32 * x)863 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
864 {
865 	return le32_to_cpup(x);
866 }
867 
868 #endif
869 
870 /*-------------------------------------------------------------------------*/
871 
872 #define ehci_dbg(ehci, fmt, args...) \
873 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
874 #define ehci_err(ehci, fmt, args...) \
875 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
876 #define ehci_info(ehci, fmt, args...) \
877 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
878 #define ehci_warn(ehci, fmt, args...) \
879 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
880 
881 /*-------------------------------------------------------------------------*/
882 
883 /* Declarations of things exported for use by ehci platform drivers */
884 
885 struct ehci_driver_overrides {
886 	size_t		extra_priv_size;
887 	int		(*reset)(struct usb_hcd *hcd);
888 	int		(*port_power)(struct usb_hcd *hcd,
889 				int portnum, bool enable);
890 };
891 
892 extern void	ehci_init_driver(struct hc_driver *drv,
893 				const struct ehci_driver_overrides *over);
894 extern int	ehci_setup(struct usb_hcd *hcd);
895 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
896 				u32 mask, u32 done, int usec);
897 extern int	ehci_reset(struct ehci_hcd *ehci);
898 
899 extern int	ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
900 extern int	ehci_resume(struct usb_hcd *hcd, bool force_reset);
901 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
902 			bool suspending, bool do_wakeup);
903 
904 extern int	ehci_hub_control(struct usb_hcd	*hcd, u16 typeReq, u16 wValue,
905 				 u16 wIndex, char *buf, u16 wLength);
906 
907 #endif /* __LINUX_EHCI_HCD_H */
908