1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 }; 23 24 #define NUM_TRGMII_CTRL 5 25 26 #define TRGMII_BASE(x) (0x10000 + (x)) 27 28 /* Registers to ethsys access */ 29 #define ETHSYS_CLKCFG0 0x2c 30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 31 32 #define SYSC_REG_RSTCTRL 0x34 33 #define RESET_MCM BIT(2) 34 35 /* Register for ARL global control */ 36 #define MT753X_AGC 0xc 37 #define LOCAL_EN BIT(7) 38 39 /* Registers to mac forward control for unknown frames */ 40 #define MT7530_MFC 0x10 41 #define BC_FFP(x) (((x) & 0xff) << 24) 42 #define BC_FFP_MASK BC_FFP(~0) 43 #define UNM_FFP(x) (((x) & 0xff) << 16) 44 #define UNM_FFP_MASK UNM_FFP(~0) 45 #define UNU_FFP(x) (((x) & 0xff) << 8) 46 #define UNU_FFP_MASK UNU_FFP(~0) 47 #define CPU_EN BIT(7) 48 #define CPU_PORT(x) ((x) << 4) 49 #define CPU_MASK (0xf << 4) 50 #define MIRROR_EN BIT(3) 51 #define MIRROR_PORT(x) ((x) & 0x7) 52 #define MIRROR_MASK 0x7 53 54 /* Registers for CPU forward control */ 55 #define MT7531_CFC 0x4 56 #define MT7531_MIRROR_EN BIT(19) 57 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 58 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 59 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 60 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 61 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 62 63 #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 64 MT7531_CFC : MT7530_MFC) 65 #define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 66 MT7531_MIRROR_EN : MIRROR_EN) 67 #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 68 MT7531_MIRROR_MASK : MIRROR_MASK) 69 70 /* Registers for BPDU and PAE frame control*/ 71 #define MT753X_BPC 0x24 72 #define MT753X_PAE_BPDU_FR BIT(25) 73 #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) 74 #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) 75 #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) 76 #define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) 77 #define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) 78 #define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) 79 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 80 81 /* Register for :01 and :02 MAC DA frame control */ 82 #define MT753X_RGAC1 0x28 83 #define MT753X_R02_BPDU_FR BIT(25) 84 #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) 85 #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) 86 #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) 87 #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) 88 #define MT753X_R01_BPDU_FR BIT(9) 89 #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) 90 #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) 91 #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) 92 93 /* Register for :03 and :0E MAC DA frame control */ 94 #define MT753X_RGAC2 0x2c 95 #define MT753X_R0E_BPDU_FR BIT(25) 96 #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) 97 #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) 98 #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) 99 #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) 100 #define MT753X_R03_BPDU_FR BIT(9) 101 #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) 102 #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) 103 #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) 104 105 enum mt753x_bpdu_port_fw { 106 MT753X_BPDU_FOLLOW_MFC, 107 MT753X_BPDU_CPU_EXCLUDE = 4, 108 MT753X_BPDU_CPU_INCLUDE = 5, 109 MT753X_BPDU_CPU_ONLY = 6, 110 MT753X_BPDU_DROP = 7, 111 }; 112 113 /* Registers for address table access */ 114 #define MT7530_ATA1 0x74 115 #define STATIC_EMP 0 116 #define STATIC_ENT 3 117 #define MT7530_ATA2 0x78 118 #define ATA2_IVL BIT(15) 119 #define ATA2_FID(x) (((x) & 0x7) << 12) 120 121 /* Register for address table write data */ 122 #define MT7530_ATWD 0x7c 123 124 /* Register for address table control */ 125 #define MT7530_ATC 0x80 126 #define ATC_HASH (((x) & 0xfff) << 16) 127 #define ATC_BUSY BIT(15) 128 #define ATC_SRCH_END BIT(14) 129 #define ATC_SRCH_HIT BIT(13) 130 #define ATC_INVALID BIT(12) 131 #define ATC_MAT(x) (((x) & 0xf) << 8) 132 #define ATC_MAT_MACTAB ATC_MAT(0) 133 134 enum mt7530_fdb_cmd { 135 MT7530_FDB_READ = 0, 136 MT7530_FDB_WRITE = 1, 137 MT7530_FDB_FLUSH = 2, 138 MT7530_FDB_START = 4, 139 MT7530_FDB_NEXT = 5, 140 }; 141 142 /* Registers for table search read address */ 143 #define MT7530_TSRA1 0x84 144 #define MAC_BYTE_0 24 145 #define MAC_BYTE_1 16 146 #define MAC_BYTE_2 8 147 #define MAC_BYTE_3 0 148 #define MAC_BYTE_MASK 0xff 149 150 #define MT7530_TSRA2 0x88 151 #define MAC_BYTE_4 24 152 #define MAC_BYTE_5 16 153 #define CVID 0 154 #define CVID_MASK 0xfff 155 156 #define MT7530_ATRD 0x8C 157 #define AGE_TIMER 24 158 #define AGE_TIMER_MASK 0xff 159 #define PORT_MAP 4 160 #define PORT_MAP_MASK 0xff 161 #define ENT_STATUS 2 162 #define ENT_STATUS_MASK 0x3 163 164 /* Register for vlan table control */ 165 #define MT7530_VTCR 0x90 166 #define VTCR_BUSY BIT(31) 167 #define VTCR_INVALID BIT(16) 168 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 169 #define VTCR_VID ((x) & 0xfff) 170 171 enum mt7530_vlan_cmd { 172 /* Read/Write the specified VID entry from VAWD register based 173 * on VID. 174 */ 175 MT7530_VTCR_RD_VID = 0, 176 MT7530_VTCR_WR_VID = 1, 177 }; 178 179 /* Register for setup vlan and acl write data */ 180 #define MT7530_VAWD1 0x94 181 #define PORT_STAG BIT(31) 182 /* Independent VLAN Learning */ 183 #define IVL_MAC BIT(30) 184 /* Egress Tag Consistent */ 185 #define EG_CON BIT(29) 186 /* Per VLAN Egress Tag Control */ 187 #define VTAG_EN BIT(28) 188 /* VLAN Member Control */ 189 #define PORT_MEM(x) (((x) & 0xff) << 16) 190 /* Filter ID */ 191 #define FID(x) (((x) & 0x7) << 1) 192 /* VLAN Entry Valid */ 193 #define VLAN_VALID BIT(0) 194 #define PORT_MEM_SHFT 16 195 #define PORT_MEM_MASK 0xff 196 197 enum mt7530_fid { 198 FID_STANDALONE = 0, 199 FID_BRIDGED = 1, 200 }; 201 202 #define MT7530_VAWD2 0x98 203 /* Egress Tag Control */ 204 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 205 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 206 207 enum mt7530_vlan_egress_attr { 208 MT7530_VLAN_EGRESS_UNTAG = 0, 209 MT7530_VLAN_EGRESS_TAG = 2, 210 MT7530_VLAN_EGRESS_STACK = 3, 211 }; 212 213 /* Register for address age control */ 214 #define MT7530_AAC 0xa0 215 /* Disable ageing */ 216 #define AGE_DIS BIT(20) 217 /* Age count */ 218 #define AGE_CNT_MASK GENMASK(19, 12) 219 #define AGE_CNT_MAX 0xff 220 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 221 /* Age unit */ 222 #define AGE_UNIT_MASK GENMASK(11, 0) 223 #define AGE_UNIT_MAX 0xfff 224 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 225 226 /* Register for port STP state control */ 227 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 228 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 229 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 230 231 enum mt7530_stp_state { 232 MT7530_STP_DISABLED = 0, 233 MT7530_STP_BLOCKING = 1, 234 MT7530_STP_LISTENING = 1, 235 MT7530_STP_LEARNING = 2, 236 MT7530_STP_FORWARDING = 3 237 }; 238 239 /* Register for port control */ 240 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 241 #define PORT_TX_MIR BIT(9) 242 #define PORT_RX_MIR BIT(8) 243 #define PORT_VLAN(x) ((x) & 0x3) 244 245 enum mt7530_port_mode { 246 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 247 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 248 249 /* Fallback Mode: Forward received frames with ingress ports that do 250 * not belong to the VLAN member. Frames whose VID is not listed on 251 * the VLAN table are forwarded by the PCR_MATRIX members. 252 */ 253 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 254 255 /* Security Mode: Discard any frame due to ingress membership 256 * violation or VID missed on the VLAN table. 257 */ 258 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 259 }; 260 261 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 262 #define PORT_PRI(x) (((x) & 0x7) << 24) 263 #define EG_TAG(x) (((x) & 0x3) << 28) 264 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 265 #define PCR_MATRIX_CLR PCR_MATRIX(0) 266 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 267 268 /* Register for port security control */ 269 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 270 #define SA_DIS BIT(4) 271 272 /* Register for port vlan control */ 273 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 274 #define PORT_SPEC_TAG BIT(5) 275 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 276 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 277 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 278 #define VLAN_ATTR_MASK VLAN_ATTR(3) 279 #define ACC_FRM_MASK GENMASK(1, 0) 280 281 enum mt7530_vlan_port_eg_tag { 282 MT7530_VLAN_EG_DISABLED = 0, 283 MT7530_VLAN_EG_CONSISTENT = 1, 284 MT7530_VLAN_EG_UNTAGGED = 4, 285 }; 286 287 enum mt7530_vlan_port_attr { 288 MT7530_VLAN_USER = 0, 289 MT7530_VLAN_TRANSPARENT = 3, 290 }; 291 292 enum mt7530_vlan_port_acc_frm { 293 MT7530_VLAN_ACC_ALL = 0, 294 MT7530_VLAN_ACC_TAGGED = 1, 295 MT7530_VLAN_ACC_UNTAGGED = 2, 296 }; 297 298 #define STAG_VPID (((x) & 0xffff) << 16) 299 300 /* Register for port port-and-protocol based vlan 1 control */ 301 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 302 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 303 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 304 #define G0_PORT_VID_DEF G0_PORT_VID(0) 305 306 /* Register for port MAC control register */ 307 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 308 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 309 #define PMCR_EXT_PHY BIT(17) 310 #define PMCR_MAC_MODE BIT(16) 311 #define PMCR_FORCE_MODE BIT(15) 312 #define PMCR_TX_EN BIT(14) 313 #define PMCR_RX_EN BIT(13) 314 #define PMCR_BACKOFF_EN BIT(9) 315 #define PMCR_BACKPR_EN BIT(8) 316 #define PMCR_FORCE_EEE1G BIT(7) 317 #define PMCR_FORCE_EEE100 BIT(6) 318 #define PMCR_TX_FC_EN BIT(5) 319 #define PMCR_RX_FC_EN BIT(4) 320 #define PMCR_FORCE_SPEED_1000 BIT(3) 321 #define PMCR_FORCE_SPEED_100 BIT(2) 322 #define PMCR_FORCE_FDX BIT(1) 323 #define PMCR_FORCE_LNK BIT(0) 324 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 325 PMCR_FORCE_SPEED_1000) 326 #define MT7531_FORCE_LNK BIT(31) 327 #define MT7531_FORCE_SPD BIT(30) 328 #define MT7531_FORCE_DPX BIT(29) 329 #define MT7531_FORCE_RX_FC BIT(28) 330 #define MT7531_FORCE_TX_FC BIT(27) 331 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 332 MT7531_FORCE_SPD | \ 333 MT7531_FORCE_DPX | \ 334 MT7531_FORCE_RX_FC | \ 335 MT7531_FORCE_TX_FC) 336 #define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 337 MT7531_FORCE_MODE : PMCR_FORCE_MODE) 338 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 339 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 340 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 341 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ 342 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) 343 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ 344 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 345 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 346 PMCR_TX_EN | PMCR_RX_EN | \ 347 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 348 PMCR_FORCE_SPEED_1000 | \ 349 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 350 351 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) 352 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) 353 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) 354 #define LPI_THRESH_MASK GENMASK(15, 4) 355 #define LPI_THRESH_SHT 4 356 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) 357 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) 358 #define LPI_MODE_EN BIT(0) 359 360 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 361 #define PMSR_EEE1G BIT(7) 362 #define PMSR_EEE100M BIT(6) 363 #define PMSR_RX_FC BIT(5) 364 #define PMSR_TX_FC BIT(4) 365 #define PMSR_SPEED_1000 BIT(3) 366 #define PMSR_SPEED_100 BIT(2) 367 #define PMSR_SPEED_10 0x00 368 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 369 #define PMSR_DPX BIT(1) 370 #define PMSR_LINK BIT(0) 371 372 /* Register for port debug count */ 373 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 374 #define MT7531_DIS_CLR BIT(31) 375 376 #define MT7530_GMACCR 0x30e0 377 #define MAX_RX_JUMBO(x) ((x) << 2) 378 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 379 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 380 #define MAX_RX_PKT_LEN_1522 0x0 381 #define MAX_RX_PKT_LEN_1536 0x1 382 #define MAX_RX_PKT_LEN_1552 0x2 383 #define MAX_RX_PKT_LEN_JUMBO 0x3 384 385 /* Register for MIB */ 386 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 387 #define MT7530_MIB_CCR 0x4fe0 388 #define CCR_MIB_ENABLE BIT(31) 389 #define CCR_RX_OCT_CNT_GOOD BIT(7) 390 #define CCR_RX_OCT_CNT_BAD BIT(6) 391 #define CCR_TX_OCT_CNT_GOOD BIT(5) 392 #define CCR_TX_OCT_CNT_BAD BIT(4) 393 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 394 CCR_RX_OCT_CNT_BAD | \ 395 CCR_TX_OCT_CNT_GOOD | \ 396 CCR_TX_OCT_CNT_BAD) 397 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 398 CCR_RX_OCT_CNT_GOOD | \ 399 CCR_RX_OCT_CNT_BAD | \ 400 CCR_TX_OCT_CNT_GOOD | \ 401 CCR_TX_OCT_CNT_BAD) 402 403 /* MT7531 SGMII register group */ 404 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 405 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 406 407 /* Register for system reset */ 408 #define MT7530_SYS_CTRL 0x7000 409 #define SYS_CTRL_PHY_RST BIT(2) 410 #define SYS_CTRL_SW_RST BIT(1) 411 #define SYS_CTRL_REG_RST BIT(0) 412 413 /* Register for system interrupt */ 414 #define MT7530_SYS_INT_EN 0x7008 415 416 /* Register for system interrupt status */ 417 #define MT7530_SYS_INT_STS 0x700c 418 419 /* Register for PHY Indirect Access Control */ 420 #define MT7531_PHY_IAC 0x701C 421 #define MT7531_PHY_ACS_ST BIT(31) 422 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 423 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 424 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 425 #define MT7531_MDIO_ST_MASK (0x3 << 16) 426 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 427 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 428 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 429 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 430 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 431 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 432 433 enum mt7531_phy_iac_cmd { 434 MT7531_MDIO_ADDR = 0, 435 MT7531_MDIO_WRITE = 1, 436 MT7531_MDIO_READ = 2, 437 MT7531_MDIO_READ_CL45 = 3, 438 }; 439 440 /* MDIO_ST: MDIO start field */ 441 enum mt7531_mdio_st { 442 MT7531_MDIO_ST_CL45 = 0, 443 MT7531_MDIO_ST_CL22 = 1, 444 }; 445 446 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 447 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 448 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 449 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 450 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 451 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 452 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 453 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 454 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 455 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 456 457 /* Register for RGMII clock phase */ 458 #define MT7531_CLKGEN_CTRL 0x7500 459 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 460 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 461 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 462 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 463 #define RXCLK_NO_DELAY BIT(5) 464 #define TXCLK_NO_REVERSE BIT(4) 465 #define GP_MODE(x) (((x) & 0x3) << 1) 466 #define GP_MODE_MASK GENMASK(2, 1) 467 #define GP_CLK_EN BIT(0) 468 469 enum mt7531_gp_mode { 470 MT7531_GP_MODE_RGMII = 0, 471 MT7531_GP_MODE_MII = 1, 472 MT7531_GP_MODE_REV_MII = 2 473 }; 474 475 enum mt7531_clk_skew { 476 MT7531_CLK_SKEW_NO_CHG = 0, 477 MT7531_CLK_SKEW_DLY_100PPS = 1, 478 MT7531_CLK_SKEW_DLY_200PPS = 2, 479 MT7531_CLK_SKEW_REVERSE = 3, 480 }; 481 482 /* Register for hw trap status */ 483 #define MT7530_HWTRAP 0x7800 484 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 485 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 486 #define HWTRAP_XTAL_40MHZ (BIT(10)) 487 #define HWTRAP_XTAL_20MHZ (BIT(9)) 488 489 #define MT7531_HWTRAP 0x7800 490 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 491 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 492 #define HWTRAP_XTAL_FSEL_40MHZ 0 493 /* Unique fields of (M)HWSTRAP for MT7531 */ 494 #define XTAL_FSEL_S 7 495 #define XTAL_FSEL_M BIT(7) 496 #define PHY_EN BIT(6) 497 #define CHG_STRAP BIT(8) 498 499 /* Register for hw trap modification */ 500 #define MT7530_MHWTRAP 0x7804 501 #define MHWTRAP_PHY0_SEL BIT(20) 502 #define MHWTRAP_MANUAL BIT(16) 503 #define MHWTRAP_P5_MAC_SEL BIT(13) 504 #define MHWTRAP_P6_DIS BIT(8) 505 #define MHWTRAP_P5_RGMII_MODE BIT(7) 506 #define MHWTRAP_P5_DIS BIT(6) 507 #define MHWTRAP_PHY_ACCESS BIT(5) 508 509 /* Register for TOP signal control */ 510 #define MT7530_TOP_SIG_CTRL 0x7808 511 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 512 513 #define MT7531_TOP_SIG_SR 0x780c 514 #define PAD_DUAL_SGMII_EN BIT(1) 515 #define PAD_MCM_SMI_EN BIT(0) 516 517 #define MT7530_IO_DRV_CR 0x7810 518 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 519 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 520 521 #define MT7531_CHIP_REV 0x781C 522 523 #define MT7531_PLLGP_EN 0x7820 524 #define EN_COREPLL BIT(2) 525 #define SW_CLKSW BIT(1) 526 #define SW_PLLGP BIT(0) 527 528 #define MT7530_P6ECR 0x7830 529 #define P6_INTF_MODE_MASK 0x3 530 #define P6_INTF_MODE(x) ((x) & 0x3) 531 532 #define MT7531_PLLGP_CR0 0x78a8 533 #define RG_COREPLL_EN BIT(22) 534 #define RG_COREPLL_POSDIV_S 23 535 #define RG_COREPLL_POSDIV_M 0x3800000 536 #define RG_COREPLL_SDM_PCW_S 1 537 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 538 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 539 540 /* Registers for RGMII and SGMII PLL clock */ 541 #define MT7531_ANA_PLLGP_CR2 0x78b0 542 #define MT7531_ANA_PLLGP_CR5 0x78bc 543 544 /* Registers for TRGMII on the both side */ 545 #define MT7530_TRGMII_RCK_CTRL 0x7a00 546 #define RX_RST BIT(31) 547 #define RXC_DQSISEL BIT(30) 548 #define DQSI1_TAP_MASK (0x7f << 8) 549 #define DQSI0_TAP_MASK 0x7f 550 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 551 #define DQSI0_TAP(x) ((x) & 0x7f) 552 553 #define MT7530_TRGMII_RCK_RTT 0x7a04 554 #define DQS1_GATE BIT(31) 555 #define DQS0_GATE BIT(30) 556 557 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 558 #define BSLIP_EN BIT(31) 559 #define EDGE_CHK BIT(30) 560 #define RD_TAP_MASK 0x7f 561 #define RD_TAP(x) ((x) & 0x7f) 562 563 #define MT7530_TRGMII_TXCTRL 0x7a40 564 #define TRAIN_TXEN BIT(31) 565 #define TXC_INV BIT(30) 566 #define TX_RST BIT(28) 567 568 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 569 #define TD_DM_DRVP(x) ((x) & 0xf) 570 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 571 572 #define MT7530_TRGMII_TCK_CTRL 0x7a78 573 #define TCK_TAP(x) (((x) & 0xf) << 8) 574 575 #define MT7530_P5RGMIIRXCR 0x7b00 576 #define CSR_RGMII_EDGE_ALIGN BIT(8) 577 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 578 579 #define MT7530_P5RGMIITXCR 0x7b04 580 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 581 582 /* Registers for GPIO mode */ 583 #define MT7531_GPIO_MODE0 0x7c0c 584 #define MT7531_GPIO0_MASK GENMASK(3, 0) 585 #define MT7531_GPIO0_INTERRUPT 1 586 587 #define MT7531_GPIO_MODE1 0x7c10 588 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 589 #define MT7531_EXT_P_MDC_11 (2 << 12) 590 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 591 #define MT7531_EXT_P_MDIO_12 (2 << 16) 592 593 /* Registers for LED GPIO control (MT7530 only) 594 * All registers follow this pattern: 595 * [ 2: 0] port 0 596 * [ 6: 4] port 1 597 * [10: 8] port 2 598 * [14:12] port 3 599 * [18:16] port 4 600 */ 601 602 /* LED enable, 0: Disable, 1: Enable (Default) */ 603 #define MT7530_LED_EN 0x7d00 604 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 605 #define MT7530_LED_IO_MODE 0x7d04 606 /* GPIO direction, 0: Input, 1: Output */ 607 #define MT7530_LED_GPIO_DIR 0x7d10 608 /* GPIO output enable, 0: Disable, 1: Enable */ 609 #define MT7530_LED_GPIO_OE 0x7d14 610 /* GPIO value, 0: Low, 1: High */ 611 #define MT7530_LED_GPIO_DATA 0x7d18 612 613 #define MT7530_CREV 0x7ffc 614 #define CHIP_NAME_SHIFT 16 615 #define MT7530_ID 0x7530 616 617 #define MT7531_CREV 0x781C 618 #define CHIP_REV_M 0x0f 619 #define MT7531_ID 0x7531 620 621 /* Registers for core PLL access through mmd indirect */ 622 #define CORE_PLL_GROUP2 0x401 623 #define RG_SYSPLL_EN_NORMAL BIT(15) 624 #define RG_SYSPLL_VODEN BIT(14) 625 #define RG_SYSPLL_LF BIT(13) 626 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 627 #define RG_SYSPLL_LVROD_EN BIT(10) 628 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 629 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 630 #define RG_SYSPLL_FBKSEL BIT(4) 631 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 632 633 #define CORE_PLL_GROUP4 0x403 634 #define RG_SYSPLL_DDSFBK_EN BIT(12) 635 #define RG_SYSPLL_BIAS_EN BIT(11) 636 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 637 #define MT7531_RG_SYSPLL_DMY2 BIT(6) 638 #define MT7531_PHY_PLL_OFF BIT(5) 639 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 640 641 #define MT753X_CTRL_PHY_ADDR 0 642 643 #define CORE_PLL_GROUP5 0x404 644 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 645 646 #define CORE_PLL_GROUP6 0x405 647 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 648 649 #define CORE_PLL_GROUP7 0x406 650 #define RG_LCDDS_PWDB BIT(15) 651 #define RG_LCDDS_ISO_EN BIT(13) 652 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 653 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 654 655 #define CORE_PLL_GROUP10 0x409 656 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 657 658 #define CORE_PLL_GROUP11 0x40a 659 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 660 661 #define CORE_GSWPLL_GRP1 0x40d 662 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 663 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 664 #define RG_GSWPLL_EN_PRE BIT(11) 665 #define RG_GSWPLL_FBKSEL BIT(10) 666 #define RG_GSWPLL_BP BIT(9) 667 #define RG_GSWPLL_BR BIT(8) 668 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 669 670 #define CORE_GSWPLL_GRP2 0x40e 671 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 672 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 673 674 #define CORE_TRGMII_GSW_CLK_CG 0x410 675 #define REG_GSWCK_EN BIT(0) 676 #define REG_TRGMIICK_EN BIT(1) 677 678 #define MIB_DESC(_s, _o, _n) \ 679 { \ 680 .size = (_s), \ 681 .offset = (_o), \ 682 .name = (_n), \ 683 } 684 685 struct mt7530_mib_desc { 686 unsigned int size; 687 unsigned int offset; 688 const char *name; 689 }; 690 691 struct mt7530_fdb { 692 u16 vid; 693 u8 port_mask; 694 u8 aging; 695 u8 mac[6]; 696 bool noarp; 697 }; 698 699 /* struct mt7530_port - This is the main data structure for holding the state 700 * of the port. 701 * @enable: The status used for show port is enabled or not. 702 * @pm: The matrix used to show all connections with the port. 703 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 704 * untagged frames will be assigned to the related VLAN. 705 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 706 */ 707 struct mt7530_port { 708 bool enable; 709 u32 pm; 710 u16 pvid; 711 struct phylink_pcs *sgmii_pcs; 712 }; 713 714 /* Port 5 interface select definitions */ 715 enum p5_interface_select { 716 P5_DISABLED = 0, 717 P5_INTF_SEL_PHY_P0, 718 P5_INTF_SEL_PHY_P4, 719 P5_INTF_SEL_GMAC5, 720 P5_INTF_SEL_GMAC5_SGMII, 721 }; 722 723 struct mt7530_priv; 724 725 struct mt753x_pcs { 726 struct phylink_pcs pcs; 727 struct mt7530_priv *priv; 728 int port; 729 }; 730 731 /* struct mt753x_info - This is the main data structure for holding the specific 732 * part for each supported device 733 * @sw_setup: Holding the handler to a device initialization 734 * @phy_read_c22: Holding the way reading PHY port using C22 735 * @phy_write_c22: Holding the way writing PHY port using C22 736 * @phy_read_c45: Holding the way reading PHY port using C45 737 * @phy_write_c45: Holding the way writing PHY port using C45 738 * @pad_setup: Holding the way setting up the bus pad for a certain 739 * MAC port 740 * @phy_mode_supported: Check if the PHY type is being supported on a certain 741 * port 742 * @mac_port_validate: Holding the way to set addition validate type for a 743 * certan MAC port 744 * @mac_port_config: Holding the way setting up the PHY attribute to a 745 * certain MAC port 746 */ 747 struct mt753x_info { 748 enum mt753x_id id; 749 750 const struct phylink_pcs_ops *pcs_ops; 751 752 int (*sw_setup)(struct dsa_switch *ds); 753 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 754 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 755 u16 val); 756 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 757 int regnum); 758 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 759 int regnum, u16 val); 760 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); 761 int (*cpu_port_config)(struct dsa_switch *ds, int port); 762 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 763 struct phylink_config *config); 764 void (*mac_port_validate)(struct dsa_switch *ds, int port, 765 phy_interface_t interface, 766 unsigned long *supported); 767 int (*mac_port_config)(struct dsa_switch *ds, int port, 768 unsigned int mode, 769 phy_interface_t interface); 770 }; 771 772 /* struct mt7530_priv - This is the main data structure for holding the state 773 * of the driver 774 * @dev: The device pointer 775 * @ds: The pointer to the dsa core structure 776 * @bus: The bus used for the device and built-in PHY 777 * @regmap: The regmap instance representing all switch registers 778 * @rstc: The pointer to reset control used by MCM 779 * @core_pwr: The power supplied into the core 780 * @io_pwr: The power supplied into the I/O 781 * @reset: The descriptor for GPIO line tied to its reset pin 782 * @mcm: Flag for distinguishing if standalone IC or module 783 * coupling 784 * @ports: Holding the state among ports 785 * @reg_mutex: The lock for protecting among process accessing 786 * registers 787 * @p6_interface Holding the current port 6 interface 788 * @p5_intf_sel: Holding the current port 5 interface select 789 * @irq: IRQ number of the switch 790 * @irq_domain: IRQ domain of the switch irq_chip 791 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN 792 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 793 */ 794 struct mt7530_priv { 795 struct device *dev; 796 struct dsa_switch *ds; 797 struct mii_bus *bus; 798 struct regmap *regmap; 799 struct reset_control *rstc; 800 struct regulator *core_pwr; 801 struct regulator *io_pwr; 802 struct gpio_desc *reset; 803 const struct mt753x_info *info; 804 unsigned int id; 805 bool mcm; 806 phy_interface_t p6_interface; 807 phy_interface_t p5_interface; 808 unsigned int p5_intf_sel; 809 u8 mirror_rx; 810 u8 mirror_tx; 811 struct mt7530_port ports[MT7530_NUM_PORTS]; 812 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 813 /* protect among processes for registers access*/ 814 struct mutex reg_mutex; 815 int irq; 816 struct irq_domain *irq_domain; 817 u32 irq_enable; 818 int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); 819 }; 820 821 struct mt7530_hw_vlan_entry { 822 int port; 823 u8 old_members; 824 bool untagged; 825 }; 826 mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry * e,int port,bool untagged)827 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 828 int port, bool untagged) 829 { 830 e->port = port; 831 e->untagged = untagged; 832 } 833 834 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 835 struct mt7530_hw_vlan_entry *); 836 837 struct mt7530_hw_stats { 838 const char *string; 839 u16 reg; 840 u8 sizeof_stat; 841 }; 842 843 struct mt7530_dummy_poll { 844 struct mt7530_priv *priv; 845 u32 reg; 846 }; 847 INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll * p,struct mt7530_priv * priv,u32 reg)848 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 849 struct mt7530_priv *priv, u32 reg) 850 { 851 p->priv = priv; 852 p->reg = reg; 853 } 854 855 int mt7530_probe_common(struct mt7530_priv *priv); 856 void mt7530_remove_common(struct mt7530_priv *priv); 857 858 extern const struct dsa_switch_ops mt7530_switch_ops; 859 extern const struct mt753x_info mt753x_table[]; 860 861 #endif /* __MT7530_H */ 862