1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3  * Driver for Solarflare network controllers and boards
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
6  */
7 
8 /* Common definitions for all Efx net driver code */
9 
10 #ifndef EFX_NET_DRIVER_H
11 #define EFX_NET_DRIVER_H
12 
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/timer.h>
18 #include <linux/mdio.h>
19 #include <linux/list.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/highmem.h>
23 #include <linux/workqueue.h>
24 #include <linux/mutex.h>
25 #include <linux/rwsem.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mtd/mtd.h>
28 #include <net/busy_poll.h>
29 #include <net/xdp.h>
30 #include <net/netevent.h>
31 
32 #include "enum.h"
33 #include "bitfield.h"
34 #include "filter.h"
35 
36 /**************************************************************************
37  *
38  * Build definitions
39  *
40  **************************************************************************/
41 
42 #ifdef DEBUG
43 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
45 #else
46 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
47 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
48 #endif
49 
50 /**************************************************************************
51  *
52  * Efx data structures
53  *
54  **************************************************************************/
55 
56 #define EFX_MAX_CHANNELS 32U
57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
58 #define EFX_EXTRA_CHANNEL_IOV	0
59 #define EFX_EXTRA_CHANNEL_PTP	1
60 #define EFX_EXTRA_CHANNEL_TC	2
61 #define EFX_MAX_EXTRA_CHANNELS	3U
62 
63 /* Checksum generation is a per-queue option in hardware, so each
64  * queue visible to the networking core is backed by two hardware TX
65  * queues. */
66 #define EFX_MAX_TX_TC		2
67 #define EFX_MAX_CORE_TX_QUEUES	(EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
68 #define EFX_TXQ_TYPE_OUTER_CSUM	1	/* Outer checksum offload */
69 #define EFX_TXQ_TYPE_INNER_CSUM	2	/* Inner checksum offload */
70 #define EFX_TXQ_TYPES		4
71 #define EFX_MAX_TXQ_PER_CHANNEL	4
72 #define EFX_MAX_TX_QUEUES	(EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
73 
74 /* Maximum possible MTU the driver supports */
75 #define EFX_MAX_MTU (9 * 1024)
76 
77 /* Minimum MTU, from RFC791 (IP) */
78 #define EFX_MIN_MTU 68
79 
80 /* Maximum total header length for TSOv2 */
81 #define EFX_TSO2_MAX_HDRLEN	208
82 
83 /* Size of an RX scatter buffer.  Small enough to pack 2 into a 4K page,
84  * and should be a multiple of the cache line size.
85  */
86 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
87 
88 /* If possible, we should ensure cache line alignment at start and end
89  * of every buffer.  Otherwise, we just need to ensure 4-byte
90  * alignment of the network header.
91  */
92 #if NET_IP_ALIGN == 0
93 #define EFX_RX_BUF_ALIGNMENT	L1_CACHE_BYTES
94 #else
95 #define EFX_RX_BUF_ALIGNMENT	4
96 #endif
97 
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
99  * still fit two standard MTU size packets into a single 4K page.
100  */
101 #define EFX_XDP_HEADROOM	128
102 #define EFX_XDP_TAILROOM	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
103 
104 /* Forward declare Precision Time Protocol (PTP) support structure. */
105 struct efx_ptp_data;
106 struct hwtstamp_config;
107 
108 struct efx_self_tests;
109 
110 /**
111  * struct efx_buffer - A general-purpose DMA buffer
112  * @addr: host base address of the buffer
113  * @dma_addr: DMA base address of the buffer
114  * @len: Buffer length, in bytes
115  *
116  * The NIC uses these buffers for its interrupt status registers and
117  * MAC stats dumps.
118  */
119 struct efx_buffer {
120 	void *addr;
121 	dma_addr_t dma_addr;
122 	unsigned int len;
123 };
124 
125 /**
126  * struct efx_tx_buffer - buffer state for a TX descriptor
127  * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
128  *	freed when descriptor completes
129  * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
130  *	member is the associated buffer to drop a page reference on.
131  * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
132  *	descriptor.
133  * @dma_addr: DMA address of the fragment.
134  * @flags: Flags for allocation and DMA mapping type
135  * @len: Length of this fragment.
136  *	This field is zero when the queue slot is empty.
137  * @unmap_len: Length of this fragment to unmap
138  * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
139  * Only valid if @unmap_len != 0.
140  */
141 struct efx_tx_buffer {
142 	union {
143 		const struct sk_buff *skb;
144 		struct xdp_frame *xdpf;
145 	};
146 	union {
147 		efx_qword_t option;    /* EF10 */
148 		dma_addr_t dma_addr;
149 	};
150 	unsigned short flags;
151 	unsigned short len;
152 	unsigned short unmap_len;
153 	unsigned short dma_offset;
154 };
155 #define EFX_TX_BUF_CONT		1	/* not last descriptor of packet */
156 #define EFX_TX_BUF_SKB		2	/* buffer is last part of skb */
157 #define EFX_TX_BUF_MAP_SINGLE	8	/* buffer was mapped with dma_map_single() */
158 #define EFX_TX_BUF_OPTION	0x10	/* empty buffer for option descriptor */
159 #define EFX_TX_BUF_XDP		0x20	/* buffer was sent with XDP */
160 #define EFX_TX_BUF_TSO_V3	0x40	/* empty buffer for a TSO_V3 descriptor */
161 #define EFX_TX_BUF_EFV		0x100	/* buffer was sent from representor */
162 
163 /**
164  * struct efx_tx_queue - An Efx TX queue
165  *
166  * This is a ring buffer of TX fragments.
167  * Since the TX completion path always executes on the same
168  * CPU and the xmit path can operate on different CPUs,
169  * performance is increased by ensuring that the completion
170  * path and the xmit path operate on different cache lines.
171  * This is particularly important if the xmit path is always
172  * executing on one CPU which is different from the completion
173  * path.  There is also a cache line for members which are
174  * read but not written on the fast path.
175  *
176  * @efx: The associated Efx NIC
177  * @queue: DMA queue number
178  * @label: Label for TX completion events.
179  *	Is our index within @channel->tx_queue array.
180  * @type: configuration type of this TX queue.  A bitmask of %EFX_TXQ_TYPE_* flags.
181  * @tso_version: Version of TSO in use for this queue.
182  * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series.
183  * @channel: The associated channel
184  * @core_txq: The networking core TX queue structure
185  * @buffer: The software buffer ring
186  * @cb_page: Array of pages of copy buffers.  Carved up according to
187  *	%EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
188  * @txd: The hardware descriptor ring
189  * @ptr_mask: The size of the ring minus 1.
190  * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191  *	Size of the region is efx_piobuf_size.
192  * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193  * @initialised: Has hardware queue been initialised?
194  * @timestamping: Is timestamping enabled for this channel?
195  * @xdp_tx: Is this an XDP tx queue?
196  * @read_count: Current read pointer.
197  *	This is the number of buffers that have been removed from both rings.
198  * @old_write_count: The value of @write_count when last checked.
199  *	This is here for performance reasons.  The xmit path will
200  *	only get the up-to-date value of @write_count if this
201  *	variable indicates that the queue is empty.  This is to
202  *	avoid cache-line ping-pong between the xmit path and the
203  *	completion path.
204  * @merge_events: Number of TX merged completion events
205  * @completed_timestamp_major: Top part of the most recent tx timestamp.
206  * @completed_timestamp_minor: Low part of the most recent tx timestamp.
207  * @insert_count: Current insert pointer
208  *	This is the number of buffers that have been added to the
209  *	software ring.
210  * @write_count: Current write pointer
211  *	This is the number of buffers that have been added to the
212  *	hardware ring.
213  * @packet_write_count: Completable write pointer
214  *	This is the write pointer of the last packet written.
215  *	Normally this will equal @write_count, but as option descriptors
216  *	don't produce completion events, they won't update this.
217  *	Filled in iff @efx->type->option_descriptors; only used for PIO.
218  *	Thus, this is only written and used on EF10.
219  * @old_read_count: The value of read_count when last checked.
220  *	This is here for performance reasons.  The xmit path will
221  *	only get the up-to-date value of read_count if this
222  *	variable indicates that the queue is full.  This is to
223  *	avoid cache-line ping-pong between the xmit path and the
224  *	completion path.
225  * @tso_bursts: Number of times TSO xmit invoked by kernel
226  * @tso_long_headers: Number of packets with headers too long for standard
227  *	blocks
228  * @tso_packets: Number of packets via the TSO xmit path
229  * @tso_fallbacks: Number of times TSO fallback used
230  * @pushes: Number of times the TX push feature has been used
231  * @pio_packets: Number of times the TX PIO feature has been used
232  * @xmit_pending: Are any packets waiting to be pushed to the NIC
233  * @cb_packets: Number of times the TX copybreak feature has been used
234  * @notify_count: Count of notified descriptors to the NIC
235  * @empty_read_count: If the completion path has seen the queue as empty
236  *	and the transmission path has not yet checked this, the value of
237  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
238  */
239 struct efx_tx_queue {
240 	/* Members which don't change on the fast path */
241 	struct efx_nic *efx ____cacheline_aligned_in_smp;
242 	unsigned int queue;
243 	unsigned int label;
244 	unsigned int type;
245 	unsigned int tso_version;
246 	bool tso_encap;
247 	struct efx_channel *channel;
248 	struct netdev_queue *core_txq;
249 	struct efx_tx_buffer *buffer;
250 	struct efx_buffer *cb_page;
251 	struct efx_buffer txd;
252 	unsigned int ptr_mask;
253 	void __iomem *piobuf;
254 	unsigned int piobuf_offset;
255 	bool initialised;
256 	bool timestamping;
257 	bool xdp_tx;
258 
259 	/* Members used mainly on the completion path */
260 	unsigned int read_count ____cacheline_aligned_in_smp;
261 	unsigned int old_write_count;
262 	unsigned int merge_events;
263 	unsigned int bytes_compl;
264 	unsigned int pkts_compl;
265 	u32 completed_timestamp_major;
266 	u32 completed_timestamp_minor;
267 
268 	/* Members used only on the xmit path */
269 	unsigned int insert_count ____cacheline_aligned_in_smp;
270 	unsigned int write_count;
271 	unsigned int packet_write_count;
272 	unsigned int old_read_count;
273 	unsigned int tso_bursts;
274 	unsigned int tso_long_headers;
275 	unsigned int tso_packets;
276 	unsigned int tso_fallbacks;
277 	unsigned int pushes;
278 	unsigned int pio_packets;
279 	bool xmit_pending;
280 	unsigned int cb_packets;
281 	unsigned int notify_count;
282 	/* Statistics to supplement MAC stats */
283 	unsigned long tx_packets;
284 
285 	/* Members shared between paths and sometimes updated */
286 	unsigned int empty_read_count ____cacheline_aligned_in_smp;
287 #define EFX_EMPTY_COUNT_VALID 0x80000000
288 	atomic_t flush_outstanding;
289 };
290 
291 #define EFX_TX_CB_ORDER	7
292 #define EFX_TX_CB_SIZE	(1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
293 
294 /**
295  * struct efx_rx_buffer - An Efx RX data buffer
296  * @dma_addr: DMA base address of the buffer
297  * @page: The associated page buffer.
298  *	Will be %NULL if the buffer slot is currently free.
299  * @page_offset: If pending: offset in @page of DMA base address.
300  *	If completed: offset in @page of Ethernet header.
301  * @len: If pending: length for DMA descriptor.
302  *	If completed: received length, excluding hash prefix.
303  * @flags: Flags for buffer and packet state.  These are only set on the
304  *	first buffer of a scattered packet.
305  */
306 struct efx_rx_buffer {
307 	dma_addr_t dma_addr;
308 	struct page *page;
309 	u16 page_offset;
310 	u16 len;
311 	u16 flags;
312 };
313 #define EFX_RX_BUF_LAST_IN_PAGE	0x0001
314 #define EFX_RX_PKT_CSUMMED	0x0002
315 #define EFX_RX_PKT_DISCARD	0x0004
316 #define EFX_RX_PKT_TCP		0x0040
317 #define EFX_RX_PKT_PREFIX_LEN	0x0080	/* length is in prefix only */
318 #define EFX_RX_PKT_CSUM_LEVEL	0x0200
319 
320 /**
321  * struct efx_rx_page_state - Page-based rx buffer state
322  *
323  * Inserted at the start of every page allocated for receive buffers.
324  * Used to facilitate sharing dma mappings between recycled rx buffers
325  * and those passed up to the kernel.
326  *
327  * @dma_addr: The dma address of this page.
328  */
329 struct efx_rx_page_state {
330 	dma_addr_t dma_addr;
331 
332 	unsigned int __pad[] ____cacheline_aligned;
333 };
334 
335 /**
336  * struct efx_rx_queue - An Efx RX queue
337  * @efx: The associated Efx NIC
338  * @core_index:  Index of network core RX queue.  Will be >= 0 iff this
339  *	is associated with a real RX queue.
340  * @buffer: The software buffer ring
341  * @rxd: The hardware descriptor ring
342  * @ptr_mask: The size of the ring minus 1.
343  * @refill_enabled: Enable refill whenever fill level is low
344  * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
345  *	@rxq_flush_pending.
346  * @grant_credits: Posted RX descriptors need to be granted to the MAE with
347  *	%MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS.  For %EFX_EXTRA_CHANNEL_TC,
348  *	and only supported on EF100.
349  * @added_count: Number of buffers added to the receive queue.
350  * @notified_count: Number of buffers given to NIC (<= @added_count).
351  * @granted_count: Number of buffers granted to the MAE (<= @notified_count).
352  * @removed_count: Number of buffers removed from the receive queue.
353  * @scatter_n: Used by NIC specific receive code.
354  * @scatter_len: Used by NIC specific receive code.
355  * @page_ring: The ring to store DMA mapped pages for reuse.
356  * @page_add: Counter to calculate the write pointer for the recycle ring.
357  * @page_remove: Counter to calculate the read pointer for the recycle ring.
358  * @page_recycle_count: The number of pages that have been recycled.
359  * @page_recycle_failed: The number of pages that couldn't be recycled because
360  *      the kernel still held a reference to them.
361  * @page_recycle_full: The number of pages that were released because the
362  *      recycle ring was full.
363  * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
364  * @max_fill: RX descriptor maximum fill level (<= ring size)
365  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
366  *	(<= @max_fill)
367  * @min_fill: RX descriptor minimum non-zero fill level.
368  *	This records the minimum fill level observed when a ring
369  *	refill was triggered.
370  * @recycle_count: RX buffer recycle counter.
371  * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
372  * @grant_work: workitem used to grant credits to the MAE if @grant_credits
373  * @xdp_rxq_info: XDP specific RX queue information.
374  * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?.
375  */
376 struct efx_rx_queue {
377 	struct efx_nic *efx;
378 	int core_index;
379 	struct efx_rx_buffer *buffer;
380 	struct efx_buffer rxd;
381 	unsigned int ptr_mask;
382 	bool refill_enabled;
383 	bool flush_pending;
384 	bool grant_credits;
385 
386 	unsigned int added_count;
387 	unsigned int notified_count;
388 	unsigned int granted_count;
389 	unsigned int removed_count;
390 	unsigned int scatter_n;
391 	unsigned int scatter_len;
392 	struct page **page_ring;
393 	unsigned int page_add;
394 	unsigned int page_remove;
395 	unsigned int page_recycle_count;
396 	unsigned int page_recycle_failed;
397 	unsigned int page_recycle_full;
398 	unsigned int page_ptr_mask;
399 	unsigned int max_fill;
400 	unsigned int fast_fill_trigger;
401 	unsigned int min_fill;
402 	unsigned int min_overfill;
403 	unsigned int recycle_count;
404 	struct timer_list slow_fill;
405 	unsigned int slow_fill_count;
406 	struct work_struct grant_work;
407 	/* Statistics to supplement MAC stats */
408 	unsigned long rx_packets;
409 	struct xdp_rxq_info xdp_rxq_info;
410 	bool xdp_rxq_info_valid;
411 };
412 
413 enum efx_sync_events_state {
414 	SYNC_EVENTS_DISABLED = 0,
415 	SYNC_EVENTS_QUIESCENT,
416 	SYNC_EVENTS_REQUESTED,
417 	SYNC_EVENTS_VALID,
418 };
419 
420 /**
421  * struct efx_channel - An Efx channel
422  *
423  * A channel comprises an event queue, at least one TX queue, at least
424  * one RX queue, and an associated tasklet for processing the event
425  * queue.
426  *
427  * @efx: Associated Efx NIC
428  * @channel: Channel instance number
429  * @type: Channel type definition
430  * @eventq_init: Event queue initialised flag
431  * @enabled: Channel enabled indicator
432  * @irq: IRQ number (MSI and MSI-X only)
433  * @irq_moderation_us: IRQ moderation value (in microseconds)
434  * @napi_dev: Net device used with NAPI
435  * @napi_str: NAPI control structure
436  * @state: state for NAPI vs busy polling
437  * @state_lock: lock protecting @state
438  * @eventq: Event queue buffer
439  * @eventq_mask: Event queue pointer mask
440  * @eventq_read_ptr: Event queue read pointer
441  * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
442  * @irq_count: Number of IRQs since last adaptive moderation decision
443  * @irq_mod_score: IRQ moderation score
444  * @rfs_filter_count: number of accelerated RFS filters currently in place;
445  *	equals the count of @rps_flow_id slots filled
446  * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters
447  *	were checked for expiry
448  * @rfs_expire_index: next accelerated RFS filter ID to check for expiry
449  * @n_rfs_succeeded: number of successful accelerated RFS filter insertions
450  * @n_rfs_failed: number of failed accelerated RFS filter insertions
451  * @filter_work: Work item for efx_filter_rfs_expire()
452  * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
453  *      indexed by filter ID
454  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
455  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
456  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
457  * @n_rx_mcast_mismatch: Count of unmatched multicast frames
458  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
459  * @n_rx_overlength: Count of RX_OVERLENGTH errors
460  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
461  * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
462  *	lack of descriptors
463  * @n_rx_merge_events: Number of RX merged completion events
464  * @n_rx_merge_packets: Number of RX packets completed by merged events
465  * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
466  * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
467  * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
468  * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
469  * @n_rx_mport_bad: Count of RX packets dropped because their ingress mport was
470  *	not recognised
471  * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
472  *	__efx_rx_packet(), or zero if there is none
473  * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
474  *	by __efx_rx_packet(), if @rx_pkt_n_frags != 0
475  * @rx_list: list of SKBs from current RX, awaiting processing
476  * @rx_queue: RX queue for this channel
477  * @tx_queue: TX queues for this channel
478  * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type
479  * @sync_events_state: Current state of sync events on this channel
480  * @sync_timestamp_major: Major part of the last ptp sync event
481  * @sync_timestamp_minor: Minor part of the last ptp sync event
482  */
483 struct efx_channel {
484 	struct efx_nic *efx;
485 	int channel;
486 	const struct efx_channel_type *type;
487 	bool eventq_init;
488 	bool enabled;
489 	int irq;
490 	unsigned int irq_moderation_us;
491 	struct net_device *napi_dev;
492 	struct napi_struct napi_str;
493 #ifdef CONFIG_NET_RX_BUSY_POLL
494 	unsigned long busy_poll_state;
495 #endif
496 	struct efx_buffer eventq;
497 	unsigned int eventq_mask;
498 	unsigned int eventq_read_ptr;
499 	int event_test_cpu;
500 
501 	unsigned int irq_count;
502 	unsigned int irq_mod_score;
503 #ifdef CONFIG_RFS_ACCEL
504 	unsigned int rfs_filter_count;
505 	unsigned int rfs_last_expiry;
506 	unsigned int rfs_expire_index;
507 	unsigned int n_rfs_succeeded;
508 	unsigned int n_rfs_failed;
509 	struct delayed_work filter_work;
510 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
511 	u32 *rps_flow_id;
512 #endif
513 
514 	unsigned int n_rx_tobe_disc;
515 	unsigned int n_rx_ip_hdr_chksum_err;
516 	unsigned int n_rx_tcp_udp_chksum_err;
517 	unsigned int n_rx_outer_ip_hdr_chksum_err;
518 	unsigned int n_rx_outer_tcp_udp_chksum_err;
519 	unsigned int n_rx_inner_ip_hdr_chksum_err;
520 	unsigned int n_rx_inner_tcp_udp_chksum_err;
521 	unsigned int n_rx_eth_crc_err;
522 	unsigned int n_rx_mcast_mismatch;
523 	unsigned int n_rx_frm_trunc;
524 	unsigned int n_rx_overlength;
525 	unsigned int n_skbuff_leaks;
526 	unsigned int n_rx_nodesc_trunc;
527 	unsigned int n_rx_merge_events;
528 	unsigned int n_rx_merge_packets;
529 	unsigned int n_rx_xdp_drops;
530 	unsigned int n_rx_xdp_bad_drops;
531 	unsigned int n_rx_xdp_tx;
532 	unsigned int n_rx_xdp_redirect;
533 	unsigned int n_rx_mport_bad;
534 
535 	unsigned int rx_pkt_n_frags;
536 	unsigned int rx_pkt_index;
537 
538 	struct list_head *rx_list;
539 
540 	struct efx_rx_queue rx_queue;
541 	struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL];
542 	struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES];
543 
544 	enum efx_sync_events_state sync_events_state;
545 	u32 sync_timestamp_major;
546 	u32 sync_timestamp_minor;
547 };
548 
549 /**
550  * struct efx_msi_context - Context for each MSI
551  * @efx: The associated NIC
552  * @index: Index of the channel/IRQ
553  * @name: Name of the channel/IRQ
554  *
555  * Unlike &struct efx_channel, this is never reallocated and is always
556  * safe for the IRQ handler to access.
557  */
558 struct efx_msi_context {
559 	struct efx_nic *efx;
560 	unsigned int index;
561 	char name[IFNAMSIZ + 6];
562 };
563 
564 /**
565  * struct efx_channel_type - distinguishes traffic and extra channels
566  * @handle_no_channel: Handle failure to allocate an extra channel
567  * @pre_probe: Set up extra state prior to initialisation
568  * @start: called early in efx_start_channels()
569  * @stop: called early in efx_stop_channels()
570  * @post_remove: Tear down extra state after finalisation, if allocated.
571  *	May be called on channels that have not been probed.
572  * @get_name: Generate the channel's name (used for its IRQ handler)
573  * @copy: Copy the channel state prior to reallocation.  May be %NULL if
574  *	reallocation is not supported.
575  * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
576  * @receive_raw: Handle an RX buffer ready to be passed to __efx_rx_packet()
577  * @want_txqs: Determine whether this channel should have TX queues
578  *	created.  If %NULL, TX queues are not created.
579  * @keep_eventq: Flag for whether event queue should be kept initialised
580  *	while the device is stopped
581  * @want_pio: Flag for whether PIO buffers should be linked to this
582  *	channel's TX queues.
583  */
584 struct efx_channel_type {
585 	void (*handle_no_channel)(struct efx_nic *);
586 	int (*pre_probe)(struct efx_channel *);
587 	int (*start)(struct efx_channel *);
588 	void (*stop)(struct efx_channel *);
589 	void (*post_remove)(struct efx_channel *);
590 	void (*get_name)(struct efx_channel *, char *buf, size_t len);
591 	struct efx_channel *(*copy)(const struct efx_channel *);
592 	bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
593 	bool (*receive_raw)(struct efx_rx_queue *, u32);
594 	bool (*want_txqs)(struct efx_channel *);
595 	bool keep_eventq;
596 	bool want_pio;
597 };
598 
599 enum efx_led_mode {
600 	EFX_LED_OFF	= 0,
601 	EFX_LED_ON	= 1,
602 	EFX_LED_DEFAULT	= 2
603 };
604 
605 #define STRING_TABLE_LOOKUP(val, member) \
606 	((val) < member ## _max) ? member ## _names[val] : "(invalid)"
607 
608 extern const char *const efx_loopback_mode_names[];
609 extern const unsigned int efx_loopback_mode_max;
610 #define LOOPBACK_MODE(efx) \
611 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
612 
613 enum efx_int_mode {
614 	/* Be careful if altering to correct macro below */
615 	EFX_INT_MODE_MSIX = 0,
616 	EFX_INT_MODE_MSI = 1,
617 	EFX_INT_MODE_LEGACY = 2,
618 	EFX_INT_MODE_MAX	/* Insert any new items before this */
619 };
620 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
621 
622 enum nic_state {
623 	STATE_UNINIT = 0,	/* device being probed/removed */
624 	STATE_PROBED,		/* hardware probed */
625 	STATE_NET_DOWN,		/* netdev registered */
626 	STATE_NET_UP,		/* ready for traffic */
627 	STATE_DISABLED,		/* device disabled due to hardware errors */
628 
629 	STATE_RECOVERY = 0x100,/* recovering from PCI error */
630 	STATE_FROZEN = 0x200,	/* frozen by power management */
631 };
632 
efx_net_active(enum nic_state state)633 static inline bool efx_net_active(enum nic_state state)
634 {
635 	return state == STATE_NET_DOWN || state == STATE_NET_UP;
636 }
637 
efx_frozen(enum nic_state state)638 static inline bool efx_frozen(enum nic_state state)
639 {
640 	return state & STATE_FROZEN;
641 }
642 
efx_recovering(enum nic_state state)643 static inline bool efx_recovering(enum nic_state state)
644 {
645 	return state & STATE_RECOVERY;
646 }
647 
efx_freeze(enum nic_state state)648 static inline enum nic_state efx_freeze(enum nic_state state)
649 {
650 	WARN_ON(!efx_net_active(state));
651 	return state | STATE_FROZEN;
652 }
653 
efx_thaw(enum nic_state state)654 static inline enum nic_state efx_thaw(enum nic_state state)
655 {
656 	WARN_ON(!efx_frozen(state));
657 	return state & ~STATE_FROZEN;
658 }
659 
efx_recover(enum nic_state state)660 static inline enum nic_state efx_recover(enum nic_state state)
661 {
662 	WARN_ON(!efx_net_active(state));
663 	return state | STATE_RECOVERY;
664 }
665 
efx_recovered(enum nic_state state)666 static inline enum nic_state efx_recovered(enum nic_state state)
667 {
668 	WARN_ON(!efx_recovering(state));
669 	return state & ~STATE_RECOVERY;
670 }
671 
672 /* Forward declaration */
673 struct efx_nic;
674 
675 /* Pseudo bit-mask flow control field */
676 #define EFX_FC_RX	FLOW_CTRL_RX
677 #define EFX_FC_TX	FLOW_CTRL_TX
678 #define EFX_FC_AUTO	4
679 
680 /**
681  * struct efx_link_state - Current state of the link
682  * @up: Link is up
683  * @fd: Link is full-duplex
684  * @fc: Actual flow control flags
685  * @speed: Link speed (Mbps)
686  */
687 struct efx_link_state {
688 	bool up;
689 	bool fd;
690 	u8 fc;
691 	unsigned int speed;
692 };
693 
efx_link_state_equal(const struct efx_link_state * left,const struct efx_link_state * right)694 static inline bool efx_link_state_equal(const struct efx_link_state *left,
695 					const struct efx_link_state *right)
696 {
697 	return left->up == right->up && left->fd == right->fd &&
698 		left->fc == right->fc && left->speed == right->speed;
699 }
700 
701 /**
702  * enum efx_phy_mode - PHY operating mode flags
703  * @PHY_MODE_NORMAL: on and should pass traffic
704  * @PHY_MODE_TX_DISABLED: on with TX disabled
705  * @PHY_MODE_LOW_POWER: set to low power through MDIO
706  * @PHY_MODE_OFF: switched off through external control
707  * @PHY_MODE_SPECIAL: on but will not pass traffic
708  */
709 enum efx_phy_mode {
710 	PHY_MODE_NORMAL		= 0,
711 	PHY_MODE_TX_DISABLED	= 1,
712 	PHY_MODE_LOW_POWER	= 2,
713 	PHY_MODE_OFF		= 4,
714 	PHY_MODE_SPECIAL	= 8,
715 };
716 
efx_phy_mode_disabled(enum efx_phy_mode mode)717 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
718 {
719 	return !!(mode & ~PHY_MODE_TX_DISABLED);
720 }
721 
722 /**
723  * struct efx_hw_stat_desc - Description of a hardware statistic
724  * @name: Name of the statistic as visible through ethtool, or %NULL if
725  *	it should not be exposed
726  * @dma_width: Width in bits (0 for non-DMA statistics)
727  * @offset: Offset within stats (ignored for non-DMA statistics)
728  */
729 struct efx_hw_stat_desc {
730 	const char *name;
731 	u16 dma_width;
732 	u16 offset;
733 };
734 
735 struct vfdi_status;
736 
737 /* The reserved RSS context value */
738 #define EFX_MCDI_RSS_CONTEXT_INVALID	0xffffffff
739 /**
740  * struct efx_rss_context - A user-defined RSS context for filtering
741  * @list: node of linked list on which this struct is stored
742  * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
743  *	%EFX_MCDI_RSS_CONTEXT_INVALID if this context is not present on the NIC.
744  *	For Siena, 0 if RSS is active, else %EFX_MCDI_RSS_CONTEXT_INVALID.
745  * @user_id: the rss_context ID exposed to userspace over ethtool.
746  * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
747  * @rx_hash_key: Toeplitz hash key for this RSS context
748  * @indir_table: Indirection table for this RSS context
749  */
750 struct efx_rss_context {
751 	struct list_head list;
752 	u32 context_id;
753 	u32 user_id;
754 	bool rx_hash_udp_4tuple;
755 	u8 rx_hash_key[40];
756 	u32 rx_indir_table[128];
757 };
758 
759 #ifdef CONFIG_RFS_ACCEL
760 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
761  * is used to test if filter does or will exist.
762  */
763 #define EFX_ARFS_FILTER_ID_PENDING	-1
764 #define EFX_ARFS_FILTER_ID_ERROR	-2
765 #define EFX_ARFS_FILTER_ID_REMOVING	-3
766 /**
767  * struct efx_arfs_rule - record of an ARFS filter and its IDs
768  * @node: linkage into hash table
769  * @spec: details of the filter (used as key for hash table).  Use efx->type to
770  *	determine which member to use.
771  * @rxq_index: channel to which the filter will steer traffic.
772  * @arfs_id: filter ID which was returned to ARFS
773  * @filter_id: index in software filter table.  May be
774  *	%EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
775  *	%EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
776  *	%EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
777  */
778 struct efx_arfs_rule {
779 	struct hlist_node node;
780 	struct efx_filter_spec spec;
781 	u16 rxq_index;
782 	u16 arfs_id;
783 	s32 filter_id;
784 };
785 
786 /* Size chosen so that the table is one page (4kB) */
787 #define EFX_ARFS_HASH_TABLE_SIZE	512
788 
789 /**
790  * struct efx_async_filter_insertion - Request to asynchronously insert a filter
791  * @net_dev: Reference to the netdevice
792  * @spec: The filter to insert
793  * @work: Workitem for this request
794  * @rxq_index: Identifies the channel for which this request was made
795  * @flow_id: Identifies the kernel-side flow for which this request was made
796  */
797 struct efx_async_filter_insertion {
798 	struct net_device *net_dev;
799 	struct efx_filter_spec spec;
800 	struct work_struct work;
801 	u16 rxq_index;
802 	u32 flow_id;
803 };
804 
805 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */
806 #define EFX_RPS_MAX_IN_FLIGHT	8
807 #endif /* CONFIG_RFS_ACCEL */
808 
809 enum efx_xdp_tx_queues_mode {
810 	EFX_XDP_TX_QUEUES_DEDICATED,	/* one queue per core, locking not needed */
811 	EFX_XDP_TX_QUEUES_SHARED,	/* each queue used by more than 1 core */
812 	EFX_XDP_TX_QUEUES_BORROWED	/* queues borrowed from net stack */
813 };
814 
815 struct efx_mae;
816 
817 /**
818  * struct efx_nic - an Efx NIC
819  * @name: Device name (net device name or bus id before net device registered)
820  * @pci_dev: The PCI device
821  * @node: List node for maintaning primary/secondary function lists
822  * @primary: &struct efx_nic instance for the primary function of this
823  *	controller.  May be the same structure, and may be %NULL if no
824  *	primary function is bound.  Serialised by rtnl_lock.
825  * @secondary_list: List of &struct efx_nic instances for the secondary PCI
826  *	functions of the controller, if this is for the primary function.
827  *	Serialised by rtnl_lock.
828  * @type: Controller type attributes
829  * @legacy_irq: IRQ number
830  * @workqueue: Workqueue for port reconfigures and the HW monitor.
831  *	Work items do not hold and must not acquire RTNL.
832  * @workqueue_name: Name of workqueue
833  * @reset_work: Scheduled reset workitem
834  * @membase_phys: Memory BAR value as physical address
835  * @membase: Memory BAR value
836  * @vi_stride: step between per-VI registers / memory regions
837  * @interrupt_mode: Interrupt mode
838  * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
839  * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
840  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
841  * @irqs_hooked: Channel interrupts are hooked
842  * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
843  * @irq_rx_moderation_us: IRQ moderation time for RX event queues
844  * @msg_enable: Log message enable flags
845  * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
846  * @reset_pending: Bitmask for pending resets
847  * @tx_queue: TX DMA queues
848  * @rx_queue: RX DMA queues
849  * @channel: Channels
850  * @msi_context: Context for each MSI
851  * @extra_channel_types: Types of extra (non-traffic) channels that
852  *	should be allocated for this NIC
853  * @mae: Details of the Match Action Engine
854  * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
855  * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
856  * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
857  * @rxq_entries: Size of receive queues requested by user.
858  * @txq_entries: Size of transmit queues requested by user.
859  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
860  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
861  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
862  * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
863  * @sram_lim_qw: Qword address limit of SRAM
864  * @n_channels: Number of channels in use
865  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
866  * @n_tx_channels: Number of channels used for TX
867  * @n_extra_tx_channels: Number of extra channels with TX queues
868  * @tx_queues_per_channel: number of TX queues probed on each channel
869  * @n_xdp_channels: Number of channels used for XDP TX
870  * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
871  * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
872  * @rx_ip_align: RX DMA address offset to have IP header aligned in
873  *	in accordance with NET_IP_ALIGN
874  * @rx_dma_len: Current maximum RX DMA length
875  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
876  * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
877  *	for use in sk_buff::truesize
878  * @rx_prefix_size: Size of RX prefix before packet data
879  * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
880  *	(valid only if @rx_prefix_size != 0; always negative)
881  * @rx_packet_len_offset: Offset of RX packet length from start of packet data
882  *	(valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
883  * @rx_packet_ts_offset: Offset of timestamp from start of packet data
884  *	(valid only if channel->sync_timestamps_enabled; always negative)
885  * @rx_scatter: Scatter mode enabled for receives
886  * @rss_context: Main RSS context.  Its @list member is the head of the list of
887  *	RSS contexts created by user requests
888  * @rss_lock: Protects custom RSS context software state in @rss_context.list
889  * @vport_id: The function's vport ID, only relevant for PFs
890  * @int_error_count: Number of internal errors seen recently
891  * @int_error_expire: Time at which error count will be expired
892  * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
893  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
894  *	acknowledge but do nothing else.
895  * @irq_status: Interrupt status buffer
896  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
897  * @irq_level: IRQ level/index for IRQs not triggered by an event queue
898  * @selftest_work: Work item for asynchronous self-test
899  * @mtd_list: List of MTDs attached to the NIC
900  * @nic_data: Hardware dependent state
901  * @mcdi: Management-Controller-to-Driver Interface state
902  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
903  *	efx_monitor() and efx_reconfigure_port()
904  * @port_enabled: Port enabled indicator.
905  *	Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
906  *	efx_mac_work() with kernel interfaces. Safe to read under any
907  *	one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
908  *	be held to modify it.
909  * @port_initialized: Port initialized?
910  * @net_dev: Operating system network device. Consider holding the rtnl lock
911  * @fixed_features: Features which cannot be turned off
912  * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
913  *	field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
914  * @stats_buffer: DMA buffer for statistics
915  * @phy_type: PHY type
916  * @phy_data: PHY private data (including PHY-specific stats)
917  * @mdio: PHY MDIO interface
918  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
919  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
920  * @link_advertising: Autonegotiation advertising flags
921  * @fec_config: Forward Error Correction configuration flags.  For bit positions
922  *	see &enum ethtool_fec_config_bits.
923  * @link_state: Current state of the link
924  * @n_link_state_changes: Number of times the link has changed state
925  * @wanted_fc: Wanted flow control flags
926  * @fc_disable: When non-zero flow control is disabled. Typically used to
927  *	ensure that network back pressure doesn't delay dma queue flushes.
928  *	Serialised by the rtnl lock.
929  * @mac_work: Work item for changing MAC promiscuity and multicast hash
930  * @loopback_mode: Loopback status
931  * @loopback_modes: Supported loopback mode bitmask
932  * @loopback_selftest: Offline self-test private state
933  * @xdp_prog: Current XDP programme for this interface
934  * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
935  * @filter_state: Architecture-dependent filter table state
936  * @rps_mutex: Protects RPS state of all channels
937  * @rps_slot_map: bitmap of in-flight entries in @rps_slot
938  * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
939  * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
940  *	@rps_next_id).
941  * @rps_hash_table: Mapping between ARFS filters and their various IDs
942  * @rps_next_id: next arfs_id for an ARFS filter
943  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
944  * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
945  *	Decremented when the efx_flush_rx_queue() is called.
946  * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
947  *	completed (either success or failure). Not used when MCDI is used to
948  *	flush receive queues.
949  * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
950  * @vf_count: Number of VFs intended to be enabled.
951  * @vf_init_count: Number of VFs that have been fully initialised.
952  * @vi_scale: log2 number of vnics per VF.
953  * @vf_reps_lock: Protects vf_reps list
954  * @vf_reps: local VF reps
955  * @ptp_data: PTP state data
956  * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
957  * @vpd_sn: Serial number read from VPD
958  * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
959  *      xdp_rxq_info structures?
960  * @netdev_notifier: Netdevice notifier.
961  * @netevent_notifier: Netevent notifier (for neighbour updates).
962  * @tc: state for TC offload (EF100).
963  * @devlink: reference to devlink structure owned by this device
964  * @dl_port: devlink port associated with the PF
965  * @mem_bar: The BAR that is mapped into membase.
966  * @reg_base: Offset from the start of the bar to the function control window.
967  * @monitor_work: Hardware monitor workitem
968  * @biu_lock: BIU (bus interface unit) lock
969  * @last_irq_cpu: Last CPU to handle a possible test interrupt.  This
970  *	field is used by efx_test_interrupts() to verify that an
971  *	interrupt has occurred.
972  * @stats_lock: Statistics update lock. Must be held when calling
973  *	efx_nic_type::{update,start,stop}_stats.
974  * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
975  *
976  * This is stored in the private area of the &struct net_device.
977  */
978 struct efx_nic {
979 	/* The following fields should be written very rarely */
980 
981 	char name[IFNAMSIZ];
982 	struct list_head node;
983 	struct efx_nic *primary;
984 	struct list_head secondary_list;
985 	struct pci_dev *pci_dev;
986 	unsigned int port_num;
987 	const struct efx_nic_type *type;
988 	int legacy_irq;
989 	bool eeh_disabled_legacy_irq;
990 	struct workqueue_struct *workqueue;
991 	char workqueue_name[16];
992 	struct work_struct reset_work;
993 	resource_size_t membase_phys;
994 	void __iomem *membase;
995 
996 	unsigned int vi_stride;
997 
998 	enum efx_int_mode interrupt_mode;
999 	unsigned int timer_quantum_ns;
1000 	unsigned int timer_max_ns;
1001 	bool irq_rx_adaptive;
1002 	bool irqs_hooked;
1003 	unsigned int irq_mod_step_us;
1004 	unsigned int irq_rx_moderation_us;
1005 	u32 msg_enable;
1006 
1007 	enum nic_state state;
1008 	unsigned long reset_pending;
1009 
1010 	struct efx_channel *channel[EFX_MAX_CHANNELS];
1011 	struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
1012 	const struct efx_channel_type *
1013 	extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
1014 	struct efx_mae *mae;
1015 
1016 	unsigned int xdp_tx_queue_count;
1017 	struct efx_tx_queue **xdp_tx_queues;
1018 	enum efx_xdp_tx_queues_mode xdp_txq_queues_mode;
1019 
1020 	unsigned rxq_entries;
1021 	unsigned txq_entries;
1022 	unsigned int txq_stop_thresh;
1023 	unsigned int txq_wake_thresh;
1024 
1025 	unsigned tx_dc_base;
1026 	unsigned rx_dc_base;
1027 	unsigned sram_lim_qw;
1028 
1029 	unsigned int max_channels;
1030 	unsigned int max_vis;
1031 	unsigned int max_tx_channels;
1032 	unsigned n_channels;
1033 	unsigned n_rx_channels;
1034 	unsigned rss_spread;
1035 	unsigned tx_channel_offset;
1036 	unsigned n_tx_channels;
1037 	unsigned n_extra_tx_channels;
1038 	unsigned int tx_queues_per_channel;
1039 	unsigned int n_xdp_channels;
1040 	unsigned int xdp_channel_offset;
1041 	unsigned int xdp_tx_per_channel;
1042 	unsigned int rx_ip_align;
1043 	unsigned int rx_dma_len;
1044 	unsigned int rx_buffer_order;
1045 	unsigned int rx_buffer_truesize;
1046 	unsigned int rx_page_buf_step;
1047 	unsigned int rx_bufs_per_page;
1048 	unsigned int rx_pages_per_batch;
1049 	unsigned int rx_prefix_size;
1050 	int rx_packet_hash_offset;
1051 	int rx_packet_len_offset;
1052 	int rx_packet_ts_offset;
1053 	bool rx_scatter;
1054 	struct efx_rss_context rss_context;
1055 	struct mutex rss_lock;
1056 	u32 vport_id;
1057 
1058 	unsigned int_error_count;
1059 	unsigned long int_error_expire;
1060 
1061 	bool must_realloc_vis;
1062 	bool irq_soft_enabled;
1063 	struct efx_buffer irq_status;
1064 	unsigned irq_zero_count;
1065 	unsigned irq_level;
1066 	struct delayed_work selftest_work;
1067 
1068 #ifdef CONFIG_SFC_MTD
1069 	struct list_head mtd_list;
1070 #endif
1071 
1072 	void *nic_data;
1073 	struct efx_mcdi_data *mcdi;
1074 
1075 	struct mutex mac_lock;
1076 	struct work_struct mac_work;
1077 	bool port_enabled;
1078 
1079 	bool mc_bist_for_other_fn;
1080 	bool port_initialized;
1081 	struct net_device *net_dev;
1082 
1083 	netdev_features_t fixed_features;
1084 
1085 	u16 num_mac_stats;
1086 	struct efx_buffer stats_buffer;
1087 	u64 rx_nodesc_drops_total;
1088 	u64 rx_nodesc_drops_while_down;
1089 	bool rx_nodesc_drops_prev_state;
1090 
1091 	unsigned int phy_type;
1092 	void *phy_data;
1093 	struct mdio_if_info mdio;
1094 	unsigned int mdio_bus;
1095 	enum efx_phy_mode phy_mode;
1096 
1097 	__ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1098 	u32 fec_config;
1099 	struct efx_link_state link_state;
1100 	unsigned int n_link_state_changes;
1101 
1102 	u8 wanted_fc;
1103 	unsigned fc_disable;
1104 
1105 	atomic_t rx_reset;
1106 	enum efx_loopback_mode loopback_mode;
1107 	u64 loopback_modes;
1108 
1109 	void *loopback_selftest;
1110 	/* We access loopback_selftest immediately before running XDP,
1111 	 * so we want them next to each other.
1112 	 */
1113 	struct bpf_prog __rcu *xdp_prog;
1114 
1115 	struct rw_semaphore filter_sem;
1116 	void *filter_state;
1117 #ifdef CONFIG_RFS_ACCEL
1118 	struct mutex rps_mutex;
1119 	unsigned long rps_slot_map;
1120 	struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1121 	spinlock_t rps_hash_lock;
1122 	struct hlist_head *rps_hash_table;
1123 	u32 rps_next_id;
1124 #endif
1125 
1126 	atomic_t active_queues;
1127 	atomic_t rxq_flush_pending;
1128 	atomic_t rxq_flush_outstanding;
1129 	wait_queue_head_t flush_wq;
1130 
1131 #ifdef CONFIG_SFC_SRIOV
1132 	unsigned vf_count;
1133 	unsigned vf_init_count;
1134 	unsigned vi_scale;
1135 #endif
1136 	spinlock_t vf_reps_lock;
1137 	struct list_head vf_reps;
1138 
1139 	struct efx_ptp_data *ptp_data;
1140 	bool ptp_warned;
1141 
1142 	char *vpd_sn;
1143 	bool xdp_rxq_info_failed;
1144 
1145 	struct notifier_block netdev_notifier;
1146 	struct notifier_block netevent_notifier;
1147 	struct efx_tc_state *tc;
1148 
1149 	struct devlink *devlink;
1150 	struct devlink_port *dl_port;
1151 	unsigned int mem_bar;
1152 	u32 reg_base;
1153 
1154 	/* The following fields may be written more often */
1155 
1156 	struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1157 	spinlock_t biu_lock;
1158 	int last_irq_cpu;
1159 	spinlock_t stats_lock;
1160 	atomic_t n_rx_noskb_drops;
1161 };
1162 
1163 /**
1164  * struct efx_probe_data - State after hardware probe
1165  * @pci_dev: The PCI device
1166  * @efx: Efx NIC details
1167  */
1168 struct efx_probe_data {
1169 	struct pci_dev *pci_dev;
1170 	struct efx_nic efx;
1171 };
1172 
efx_netdev_priv(struct net_device * dev)1173 static inline struct efx_nic *efx_netdev_priv(struct net_device *dev)
1174 {
1175 	struct efx_probe_data **probe_ptr = netdev_priv(dev);
1176 	struct efx_probe_data *probe_data = *probe_ptr;
1177 
1178 	return &probe_data->efx;
1179 }
1180 
efx_dev_registered(struct efx_nic * efx)1181 static inline int efx_dev_registered(struct efx_nic *efx)
1182 {
1183 	return efx->net_dev->reg_state == NETREG_REGISTERED;
1184 }
1185 
efx_port_num(struct efx_nic * efx)1186 static inline unsigned int efx_port_num(struct efx_nic *efx)
1187 {
1188 	return efx->port_num;
1189 }
1190 
1191 struct efx_mtd_partition {
1192 	struct list_head node;
1193 	struct mtd_info mtd;
1194 	const char *dev_type_name;
1195 	const char *type_name;
1196 	char name[IFNAMSIZ + 20];
1197 };
1198 
1199 struct efx_udp_tunnel {
1200 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID	0xffff
1201 	u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1202 	__be16 port;
1203 };
1204 
1205 /**
1206  * struct efx_nic_type - Efx device type definition
1207  * @mem_bar: Get the memory BAR
1208  * @mem_map_size: Get memory BAR mapped size
1209  * @probe: Probe the controller
1210  * @remove: Free resources allocated by probe()
1211  * @init: Initialise the controller
1212  * @dimension_resources: Dimension controller resources (buffer table,
1213  *	and VIs once the available interrupt resources are clear)
1214  * @fini: Shut down the controller
1215  * @monitor: Periodic function for polling link state and hardware monitor
1216  * @map_reset_reason: Map ethtool reset reason to a reset method
1217  * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1218  * @reset: Reset the controller hardware and possibly the PHY.  This will
1219  *	be called while the controller is uninitialised.
1220  * @probe_port: Probe the MAC and PHY
1221  * @remove_port: Free resources allocated by probe_port()
1222  * @handle_global_event: Handle a "global" event (may be %NULL)
1223  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1224  * @prepare_flr: Prepare for an FLR
1225  * @finish_flr: Clean up after an FLR
1226  * @describe_stats: Describe statistics for ethtool
1227  * @update_stats: Update statistics not provided by event handling.
1228  *	Either argument may be %NULL.
1229  * @update_stats_atomic: Update statistics while in atomic context, if that
1230  *	is more limiting than @update_stats.  Otherwise, leave %NULL and
1231  *	driver core will call @update_stats.
1232  * @start_stats: Start the regular fetching of statistics
1233  * @pull_stats: Pull stats from the NIC and wait until they arrive.
1234  * @stop_stats: Stop the regular fetching of statistics
1235  * @push_irq_moderation: Apply interrupt moderation value
1236  * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1237  * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1238  * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1239  *	to the hardware.  Serialised by the mac_lock.
1240  * @check_mac_fault: Check MAC fault state. True if fault present.
1241  * @get_wol: Get WoL configuration from driver state
1242  * @set_wol: Push WoL configuration to the NIC
1243  * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1244  * @get_fec_stats: Get standard FEC statistics.
1245  * @test_chip: Test registers. This is expected to reset the NIC.
1246  * @test_nvram: Test validity of NVRAM contents
1247  * @mcdi_request: Send an MCDI request with the given header and SDU.
1248  *	The SDU length may be any value from 0 up to the protocol-
1249  *	defined maximum, but its buffer will be padded to a multiple
1250  *	of 4 bytes.
1251  * @mcdi_poll_response: Test whether an MCDI response is available.
1252  * @mcdi_read_response: Read the MCDI response PDU.  The offset will
1253  *	be a multiple of 4.  The length may not be, but the buffer
1254  *	will be padded so it is safe to round up.
1255  * @mcdi_poll_reboot: Test whether the MCDI has rebooted.  If so,
1256  *	return an appropriate error code for aborting any current
1257  *	request; otherwise return 0.
1258  * @irq_enable_master: Enable IRQs on the NIC.  Each event queue must
1259  *	be separately enabled after this.
1260  * @irq_test_generate: Generate a test IRQ
1261  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1262  *	queue must be separately disabled before this.
1263  * @irq_handle_msi: Handle MSI for a channel.  The @dev_id argument is
1264  *	a pointer to the &struct efx_msi_context for the channel.
1265  * @irq_handle_legacy: Handle legacy interrupt.  The @dev_id argument
1266  *	is a pointer to the &struct efx_nic.
1267  * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1268  * @tx_init: Initialise TX queue on the NIC
1269  * @tx_remove: Free resources for TX queue
1270  * @tx_write: Write TX descriptors and doorbell
1271  * @tx_enqueue: Add an SKB to TX queue
1272  * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1273  * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1274  * @rx_push_rss_context_config: Write RSS hash key and indirection table for
1275  *	user RSS context to the NIC
1276  * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user
1277  *	RSS context back from the NIC
1278  * @rx_probe: Allocate resources for RX queue
1279  * @rx_init: Initialise RX queue on the NIC
1280  * @rx_remove: Free resources for RX queue
1281  * @rx_write: Write RX descriptors and doorbell
1282  * @rx_defer_refill: Generate a refill reminder event
1283  * @rx_packet: Receive the queued RX buffer on a channel
1284  * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1285  * @ev_probe: Allocate resources for event queue
1286  * @ev_init: Initialise event queue on the NIC
1287  * @ev_fini: Deinitialise event queue on the NIC
1288  * @ev_remove: Free resources for event queue
1289  * @ev_process: Process events for a queue, up to the given NAPI quota
1290  * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1291  * @ev_test_generate: Generate a test event
1292  * @filter_table_probe: Probe filter capabilities and set up filter software state
1293  * @filter_table_restore: Restore filters removed from hardware
1294  * @filter_table_remove: Remove filters from hardware and tear down software state
1295  * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1296  * @filter_insert: add or replace a filter
1297  * @filter_remove_safe: remove a filter by ID, carefully
1298  * @filter_get_safe: retrieve a filter by ID, carefully
1299  * @filter_clear_rx: Remove all RX filters whose priority is less than or
1300  *	equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1301  * @filter_count_rx_used: Get the number of filters in use at a given priority
1302  * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1303  * @filter_get_rx_ids: Get list of RX filters at a given priority
1304  * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1305  *	This must check whether the specified table entry is used by RFS
1306  *	and that rps_may_expire_flow() returns true for it.
1307  * @mtd_probe: Probe and add MTD partitions associated with this net device,
1308  *	 using efx_mtd_add()
1309  * @mtd_rename: Set an MTD partition name using the net device name
1310  * @mtd_read: Read from an MTD partition
1311  * @mtd_erase: Erase part of an MTD partition
1312  * @mtd_write: Write to an MTD partition
1313  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1314  *	also notifies the driver that a writer has finished using this
1315  *	partition.
1316  * @ptp_write_host_time: Send host time to MC as part of sync protocol
1317  * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1318  *	timestamping, possibly only temporarily for the purposes of a reset.
1319  * @ptp_set_ts_config: Set hardware timestamp configuration.  The flags
1320  *	and tx_type will already have been validated but this operation
1321  *	must validate and update rx_filter.
1322  * @get_phys_port_id: Get the underlying physical port id.
1323  * @set_mac_address: Set the MAC address of the device
1324  * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1325  *	If %NULL, then device does not support any TSO version.
1326  * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1327  * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1328  * @print_additional_fwver: Dump NIC-specific additional FW version info
1329  * @sensor_event: Handle a sensor event from MCDI
1330  * @rx_recycle_ring_size: Size of the RX recycle ring
1331  * @revision: Hardware architecture revision
1332  * @txd_ptr_tbl_base: TX descriptor ring base address
1333  * @rxd_ptr_tbl_base: RX descriptor ring base address
1334  * @buf_tbl_base: Buffer table base address
1335  * @evq_ptr_tbl_base: Event queue pointer table base address
1336  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1337  * @max_dma_mask: Maximum possible DMA mask
1338  * @rx_prefix_size: Size of RX prefix before packet data
1339  * @rx_hash_offset: Offset of RX flow hash within prefix
1340  * @rx_ts_offset: Offset of timestamp within prefix
1341  * @rx_buffer_padding: Size of padding at end of RX packet
1342  * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1343  * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1344  * @option_descriptors: NIC supports TX option descriptors
1345  * @min_interrupt_mode: Lowest capability interrupt mode supported
1346  *	from &enum efx_int_mode.
1347  * @timer_period_max: Maximum period of interrupt timer (in ticks)
1348  * @offload_features: net_device feature flags for protocol offload
1349  *	features implemented in hardware
1350  * @mcdi_max_ver: Maximum MCDI version supported
1351  * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1352  */
1353 struct efx_nic_type {
1354 	bool is_vf;
1355 	unsigned int (*mem_bar)(struct efx_nic *efx);
1356 	unsigned int (*mem_map_size)(struct efx_nic *efx);
1357 	int (*probe)(struct efx_nic *efx);
1358 	void (*remove)(struct efx_nic *efx);
1359 	int (*init)(struct efx_nic *efx);
1360 	int (*dimension_resources)(struct efx_nic *efx);
1361 	void (*fini)(struct efx_nic *efx);
1362 	void (*monitor)(struct efx_nic *efx);
1363 	enum reset_type (*map_reset_reason)(enum reset_type reason);
1364 	int (*map_reset_flags)(u32 *flags);
1365 	int (*reset)(struct efx_nic *efx, enum reset_type method);
1366 	int (*probe_port)(struct efx_nic *efx);
1367 	void (*remove_port)(struct efx_nic *efx);
1368 	bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1369 	int (*fini_dmaq)(struct efx_nic *efx);
1370 	void (*prepare_flr)(struct efx_nic *efx);
1371 	void (*finish_flr)(struct efx_nic *efx);
1372 	size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1373 	size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1374 			       struct rtnl_link_stats64 *core_stats);
1375 	size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats,
1376 				      struct rtnl_link_stats64 *core_stats);
1377 	void (*start_stats)(struct efx_nic *efx);
1378 	void (*pull_stats)(struct efx_nic *efx);
1379 	void (*stop_stats)(struct efx_nic *efx);
1380 	void (*push_irq_moderation)(struct efx_channel *channel);
1381 	int (*reconfigure_port)(struct efx_nic *efx);
1382 	void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1383 	int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only);
1384 	bool (*check_mac_fault)(struct efx_nic *efx);
1385 	void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1386 	int (*set_wol)(struct efx_nic *efx, u32 type);
1387 	void (*resume_wol)(struct efx_nic *efx);
1388 	void (*get_fec_stats)(struct efx_nic *efx,
1389 			      struct ethtool_fec_stats *fec_stats);
1390 	unsigned int (*check_caps)(const struct efx_nic *efx,
1391 				   u8 flag,
1392 				   u32 offset);
1393 	int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1394 	int (*test_nvram)(struct efx_nic *efx);
1395 	void (*mcdi_request)(struct efx_nic *efx,
1396 			     const efx_dword_t *hdr, size_t hdr_len,
1397 			     const efx_dword_t *sdu, size_t sdu_len);
1398 	bool (*mcdi_poll_response)(struct efx_nic *efx);
1399 	void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1400 				   size_t pdu_offset, size_t pdu_len);
1401 	int (*mcdi_poll_reboot)(struct efx_nic *efx);
1402 	void (*mcdi_reboot_detected)(struct efx_nic *efx);
1403 	void (*irq_enable_master)(struct efx_nic *efx);
1404 	int (*irq_test_generate)(struct efx_nic *efx);
1405 	void (*irq_disable_non_ev)(struct efx_nic *efx);
1406 	irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1407 	irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1408 	int (*tx_probe)(struct efx_tx_queue *tx_queue);
1409 	void (*tx_init)(struct efx_tx_queue *tx_queue);
1410 	void (*tx_remove)(struct efx_tx_queue *tx_queue);
1411 	void (*tx_write)(struct efx_tx_queue *tx_queue);
1412 	netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
1413 	unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1414 				     dma_addr_t dma_addr, unsigned int len);
1415 	int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1416 				  const u32 *rx_indir_table, const u8 *key);
1417 	int (*rx_pull_rss_config)(struct efx_nic *efx);
1418 	int (*rx_push_rss_context_config)(struct efx_nic *efx,
1419 					  struct efx_rss_context *ctx,
1420 					  const u32 *rx_indir_table,
1421 					  const u8 *key);
1422 	int (*rx_pull_rss_context_config)(struct efx_nic *efx,
1423 					  struct efx_rss_context *ctx);
1424 	void (*rx_restore_rss_contexts)(struct efx_nic *efx);
1425 	int (*rx_probe)(struct efx_rx_queue *rx_queue);
1426 	void (*rx_init)(struct efx_rx_queue *rx_queue);
1427 	void (*rx_remove)(struct efx_rx_queue *rx_queue);
1428 	void (*rx_write)(struct efx_rx_queue *rx_queue);
1429 	void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1430 	void (*rx_packet)(struct efx_channel *channel);
1431 	bool (*rx_buf_hash_valid)(const u8 *prefix);
1432 	int (*ev_probe)(struct efx_channel *channel);
1433 	int (*ev_init)(struct efx_channel *channel);
1434 	void (*ev_fini)(struct efx_channel *channel);
1435 	void (*ev_remove)(struct efx_channel *channel);
1436 	int (*ev_process)(struct efx_channel *channel, int quota);
1437 	void (*ev_read_ack)(struct efx_channel *channel);
1438 	void (*ev_test_generate)(struct efx_channel *channel);
1439 	int (*filter_table_probe)(struct efx_nic *efx);
1440 	void (*filter_table_restore)(struct efx_nic *efx);
1441 	void (*filter_table_remove)(struct efx_nic *efx);
1442 	void (*filter_update_rx_scatter)(struct efx_nic *efx);
1443 	s32 (*filter_insert)(struct efx_nic *efx,
1444 			     struct efx_filter_spec *spec, bool replace);
1445 	int (*filter_remove_safe)(struct efx_nic *efx,
1446 				  enum efx_filter_priority priority,
1447 				  u32 filter_id);
1448 	int (*filter_get_safe)(struct efx_nic *efx,
1449 			       enum efx_filter_priority priority,
1450 			       u32 filter_id, struct efx_filter_spec *);
1451 	int (*filter_clear_rx)(struct efx_nic *efx,
1452 			       enum efx_filter_priority priority);
1453 	u32 (*filter_count_rx_used)(struct efx_nic *efx,
1454 				    enum efx_filter_priority priority);
1455 	u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1456 	s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1457 				 enum efx_filter_priority priority,
1458 				 u32 *buf, u32 size);
1459 #ifdef CONFIG_RFS_ACCEL
1460 	bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1461 				      unsigned int index);
1462 #endif
1463 #ifdef CONFIG_SFC_MTD
1464 	int (*mtd_probe)(struct efx_nic *efx);
1465 	void (*mtd_rename)(struct efx_mtd_partition *part);
1466 	int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1467 			size_t *retlen, u8 *buffer);
1468 	int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1469 	int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1470 			 size_t *retlen, const u8 *buffer);
1471 	int (*mtd_sync)(struct mtd_info *mtd);
1472 #endif
1473 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1474 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1475 	int (*ptp_set_ts_config)(struct efx_nic *efx,
1476 				 struct hwtstamp_config *init);
1477 	int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1478 	int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1479 	int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1480 	int (*get_phys_port_id)(struct efx_nic *efx,
1481 				struct netdev_phys_item_id *ppid);
1482 	int (*sriov_init)(struct efx_nic *efx);
1483 	void (*sriov_fini)(struct efx_nic *efx);
1484 	bool (*sriov_wanted)(struct efx_nic *efx);
1485 	int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, const u8 *mac);
1486 	int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1487 				 u8 qos);
1488 	int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1489 				     bool spoofchk);
1490 	int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1491 				   struct ifla_vf_info *ivi);
1492 	int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1493 				       int link_state);
1494 	int (*vswitching_probe)(struct efx_nic *efx);
1495 	int (*vswitching_restore)(struct efx_nic *efx);
1496 	void (*vswitching_remove)(struct efx_nic *efx);
1497 	int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1498 	int (*set_mac_address)(struct efx_nic *efx);
1499 	u32 (*tso_versions)(struct efx_nic *efx);
1500 	int (*udp_tnl_push_ports)(struct efx_nic *efx);
1501 	bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1502 	size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf,
1503 					 size_t len);
1504 	void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev);
1505 	unsigned int (*rx_recycle_ring_size)(const struct efx_nic *efx);
1506 
1507 	int revision;
1508 	unsigned int txd_ptr_tbl_base;
1509 	unsigned int rxd_ptr_tbl_base;
1510 	unsigned int buf_tbl_base;
1511 	unsigned int evq_ptr_tbl_base;
1512 	unsigned int evq_rptr_tbl_base;
1513 	u64 max_dma_mask;
1514 	unsigned int rx_prefix_size;
1515 	unsigned int rx_hash_offset;
1516 	unsigned int rx_ts_offset;
1517 	unsigned int rx_buffer_padding;
1518 	bool can_rx_scatter;
1519 	bool always_rx_scatter;
1520 	bool option_descriptors;
1521 	unsigned int min_interrupt_mode;
1522 	unsigned int timer_period_max;
1523 	netdev_features_t offload_features;
1524 	int mcdi_max_ver;
1525 	unsigned int max_rx_ip_filters;
1526 	u32 hwtstamp_filters;
1527 	unsigned int rx_hash_key_size;
1528 };
1529 
1530 /**************************************************************************
1531  *
1532  * Prototypes and inline functions
1533  *
1534  *************************************************************************/
1535 
1536 static inline struct efx_channel *
efx_get_channel(struct efx_nic * efx,unsigned index)1537 efx_get_channel(struct efx_nic *efx, unsigned index)
1538 {
1539 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1540 	return efx->channel[index];
1541 }
1542 
1543 /* Iterate over all used channels */
1544 #define efx_for_each_channel(_channel, _efx)				\
1545 	for (_channel = (_efx)->channel[0];				\
1546 	     _channel;							\
1547 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1548 		     (_efx)->channel[_channel->channel + 1] : NULL)
1549 
1550 /* Iterate over all used channels in reverse */
1551 #define efx_for_each_channel_rev(_channel, _efx)			\
1552 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1553 	     _channel;							\
1554 	     _channel = _channel->channel ?				\
1555 		     (_efx)->channel[_channel->channel - 1] : NULL)
1556 
1557 static inline struct efx_channel *
efx_get_tx_channel(struct efx_nic * efx,unsigned int index)1558 efx_get_tx_channel(struct efx_nic *efx, unsigned int index)
1559 {
1560 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1561 	return efx->channel[efx->tx_channel_offset + index];
1562 }
1563 
1564 static inline struct efx_channel *
efx_get_xdp_channel(struct efx_nic * efx,unsigned int index)1565 efx_get_xdp_channel(struct efx_nic *efx, unsigned int index)
1566 {
1567 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1568 	return efx->channel[efx->xdp_channel_offset + index];
1569 }
1570 
efx_channel_is_xdp_tx(struct efx_channel * channel)1571 static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel)
1572 {
1573 	return channel->channel - channel->efx->xdp_channel_offset <
1574 	       channel->efx->n_xdp_channels;
1575 }
1576 
efx_channel_has_tx_queues(struct efx_channel * channel)1577 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1578 {
1579 	return channel && channel->channel >= channel->efx->tx_channel_offset;
1580 }
1581 
efx_channel_num_tx_queues(struct efx_channel * channel)1582 static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel)
1583 {
1584 	if (efx_channel_is_xdp_tx(channel))
1585 		return channel->efx->xdp_tx_per_channel;
1586 	return channel->efx->tx_queues_per_channel;
1587 }
1588 
1589 static inline struct efx_tx_queue *
efx_channel_get_tx_queue(struct efx_channel * channel,unsigned int type)1590 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type)
1591 {
1592 	EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES);
1593 	return channel->tx_queue_by_type[type];
1594 }
1595 
1596 static inline struct efx_tx_queue *
efx_get_tx_queue(struct efx_nic * efx,unsigned int index,unsigned int type)1597 efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type)
1598 {
1599 	struct efx_channel *channel = efx_get_tx_channel(efx, index);
1600 
1601 	return efx_channel_get_tx_queue(channel, type);
1602 }
1603 
1604 /* Iterate over all TX queues belonging to a channel */
1605 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)		\
1606 	if (!efx_channel_has_tx_queues(_channel))			\
1607 		;							\
1608 	else								\
1609 		for (_tx_queue = (_channel)->tx_queue;			\
1610 		     _tx_queue < (_channel)->tx_queue +			\
1611 				 efx_channel_num_tx_queues(_channel);		\
1612 		     _tx_queue++)
1613 
efx_channel_has_rx_queue(struct efx_channel * channel)1614 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1615 {
1616 	return channel->rx_queue.core_index >= 0;
1617 }
1618 
1619 static inline struct efx_rx_queue *
efx_channel_get_rx_queue(struct efx_channel * channel)1620 efx_channel_get_rx_queue(struct efx_channel *channel)
1621 {
1622 	EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1623 	return &channel->rx_queue;
1624 }
1625 
1626 /* Iterate over all RX queues belonging to a channel */
1627 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)		\
1628 	if (!efx_channel_has_rx_queue(_channel))			\
1629 		;							\
1630 	else								\
1631 		for (_rx_queue = &(_channel)->rx_queue;			\
1632 		     _rx_queue;						\
1633 		     _rx_queue = NULL)
1634 
1635 static inline struct efx_channel *
efx_rx_queue_channel(struct efx_rx_queue * rx_queue)1636 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1637 {
1638 	return container_of(rx_queue, struct efx_channel, rx_queue);
1639 }
1640 
efx_rx_queue_index(struct efx_rx_queue * rx_queue)1641 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1642 {
1643 	return efx_rx_queue_channel(rx_queue)->channel;
1644 }
1645 
1646 /* Returns a pointer to the specified receive buffer in the RX
1647  * descriptor queue.
1648  */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)1649 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1650 						  unsigned int index)
1651 {
1652 	return &rx_queue->buffer[index];
1653 }
1654 
1655 static inline struct efx_rx_buffer *
efx_rx_buf_next(struct efx_rx_queue * rx_queue,struct efx_rx_buffer * rx_buf)1656 efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
1657 {
1658 	if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1659 		return efx_rx_buffer(rx_queue, 0);
1660 	else
1661 		return rx_buf + 1;
1662 }
1663 
1664 /**
1665  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1666  *
1667  * This calculates the maximum frame length that will be used for a
1668  * given MTU.  The frame length will be equal to the MTU plus a
1669  * constant amount of header space and padding.  This is the quantity
1670  * that the net driver will program into the MAC as the maximum frame
1671  * length.
1672  *
1673  * The 10G MAC requires 8-byte alignment on the frame
1674  * length, so we round up to the nearest 8.
1675  *
1676  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1677  * XGMII cycle).  If the frame length reaches the maximum value in the
1678  * same cycle, the XMAC can miss the IPG altogether.  We work around
1679  * this by adding a further 16 bytes.
1680  */
1681 #define EFX_FRAME_PAD	16
1682 #define EFX_MAX_FRAME_LEN(mtu) \
1683 	(ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1684 
efx_xmit_with_hwtstamp(struct sk_buff * skb)1685 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1686 {
1687 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1688 }
efx_xmit_hwtstamp_pending(struct sk_buff * skb)1689 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1690 {
1691 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1692 }
1693 
1694 /* Get the max fill level of the TX queues on this channel */
1695 static inline unsigned int
efx_channel_tx_fill_level(struct efx_channel * channel)1696 efx_channel_tx_fill_level(struct efx_channel *channel)
1697 {
1698 	struct efx_tx_queue *tx_queue;
1699 	unsigned int fill_level = 0;
1700 
1701 	efx_for_each_channel_tx_queue(tx_queue, channel)
1702 		fill_level = max(fill_level,
1703 				 tx_queue->insert_count - tx_queue->read_count);
1704 
1705 	return fill_level;
1706 }
1707 
1708 /* Conservative approximation of efx_channel_tx_fill_level using cached value */
1709 static inline unsigned int
efx_channel_tx_old_fill_level(struct efx_channel * channel)1710 efx_channel_tx_old_fill_level(struct efx_channel *channel)
1711 {
1712 	struct efx_tx_queue *tx_queue;
1713 	unsigned int fill_level = 0;
1714 
1715 	efx_for_each_channel_tx_queue(tx_queue, channel)
1716 		fill_level = max(fill_level,
1717 				 tx_queue->insert_count - tx_queue->old_read_count);
1718 
1719 	return fill_level;
1720 }
1721 
1722 /* Get all supported features.
1723  * If a feature is not fixed, it is present in hw_features.
1724  * If a feature is fixed, it does not present in hw_features, but
1725  * always in features.
1726  */
efx_supported_features(const struct efx_nic * efx)1727 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1728 {
1729 	const struct net_device *net_dev = efx->net_dev;
1730 
1731 	return net_dev->features | net_dev->hw_features;
1732 }
1733 
1734 /* Get the current TX queue insert index. */
1735 static inline unsigned int
efx_tx_queue_get_insert_index(const struct efx_tx_queue * tx_queue)1736 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1737 {
1738 	return tx_queue->insert_count & tx_queue->ptr_mask;
1739 }
1740 
1741 /* Get a TX buffer. */
1742 static inline struct efx_tx_buffer *
__efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1743 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1744 {
1745 	return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1746 }
1747 
1748 /* Get a TX buffer, checking it's not currently in use. */
1749 static inline struct efx_tx_buffer *
efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1750 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1751 {
1752 	struct efx_tx_buffer *buffer =
1753 		__efx_tx_queue_get_insert_buffer(tx_queue);
1754 
1755 	EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1756 	EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1757 	EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1758 
1759 	return buffer;
1760 }
1761 
1762 #endif /* EFX_NET_DRIVER_H */
1763