xref: /openbmc/linux/drivers/usb/dwc2/core.h (revision 3e417f31)
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * core.h - DesignWare HS OTG Controller common declarations
4  *
5  * Copyright (C) 2004-2013 Synopsys, Inc.
6  */
7 
8 #ifndef __DWC2_CORE_H__
9 #define __DWC2_CORE_H__
10 
11 #include <linux/acpi.h>
12 #include <linux/phy/phy.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/usb/gadget.h>
15 #include <linux/usb/otg.h>
16 #include <linux/usb/phy.h>
17 #include "hw.h"
18 
19 /*
20  * Suggested defines for tracers:
21  * - no_printk:    Disable tracing
22  * - pr_info:      Print this info to the console
23  * - trace_printk: Print this info to trace buffer (good for verbose logging)
24  */
25 
26 #define DWC2_TRACE_SCHEDULER		no_printk
27 #define DWC2_TRACE_SCHEDULER_VB		no_printk
28 
29 /* Detailed scheduler tracing, but won't overwhelm console */
30 #define dwc2_sch_dbg(hsotg, fmt, ...)					\
31 	DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt),			\
32 			     dev_name(hsotg->dev), ##__VA_ARGS__)
33 
34 /* Verbose scheduler tracing */
35 #define dwc2_sch_vdbg(hsotg, fmt, ...)					\
36 	DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt),		\
37 				dev_name(hsotg->dev), ##__VA_ARGS__)
38 
39 /* Maximum number of Endpoints/HostChannels */
40 #define MAX_EPS_CHANNELS	16
41 
42 /* dwc2-hsotg declarations */
43 static const char * const dwc2_hsotg_supply_names[] = {
44 	"vusb_d",               /* digital USB supply, 1.2V */
45 	"vusb_a",               /* analog USB supply, 1.1V */
46 };
47 
48 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
49 
50 /*
51  * EP0_MPS_LIMIT
52  *
53  * Unfortunately there seems to be a limit of the amount of data that can
54  * be transferred by IN transactions on EP0. This is either 127 bytes or 3
55  * packets (which practically means 1 packet and 63 bytes of data) when the
56  * MPS is set to 64.
57  *
58  * This means if we are wanting to move >127 bytes of data, we need to
59  * split the transactions up, but just doing one packet at a time does
60  * not work (this may be an implicit DATA0 PID on first packet of the
61  * transaction) and doing 2 packets is outside the controller's limits.
62  *
63  * If we try to lower the MPS size for EP0, then no transfers work properly
64  * for EP0, and the system will fail basic enumeration. As no cause for this
65  * has currently been found, we cannot support any large IN transfers for
66  * EP0.
67  */
68 #define EP0_MPS_LIMIT   64
69 
70 struct dwc2_hsotg;
71 struct dwc2_hsotg_req;
72 
73 /**
74  * struct dwc2_hsotg_ep - driver endpoint definition.
75  * @ep: The gadget layer representation of the endpoint.
76  * @name: The driver generated name for the endpoint.
77  * @queue: Queue of requests for this endpoint.
78  * @parent: Reference back to the parent device structure.
79  * @req: The current request that the endpoint is processing. This is
80  *       used to indicate an request has been loaded onto the endpoint
81  *       and has yet to be completed (maybe due to data move, or simply
82  *       awaiting an ack from the core all the data has been completed).
83  * @debugfs: File entry for debugfs file for this endpoint.
84  * @dir_in: Set to true if this endpoint is of the IN direction, which
85  *          means that it is sending data to the Host.
86  * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
87  * @index: The index for the endpoint registers.
88  * @mc: Multi Count - number of transactions per microframe
89  * @interval: Interval for periodic endpoints, in frames or microframes.
90  * @name: The name array passed to the USB core.
91  * @halted: Set if the endpoint has been halted.
92  * @periodic: Set if this is a periodic ep, such as Interrupt
93  * @isochronous: Set if this is a isochronous ep
94  * @send_zlp: Set if we need to send a zero-length packet.
95  * @wedged: Set if ep is wedged.
96  * @desc_list_dma: The DMA address of descriptor chain currently in use.
97  * @desc_list: Pointer to descriptor DMA chain head currently in use.
98  * @desc_count: Count of entries within the DMA descriptor chain of EP.
99  * @next_desc: index of next free descriptor in the ISOC chain under SW control.
100  * @compl_desc: index of next descriptor to be completed by xFerComplete
101  * @total_data: The total number of data bytes done.
102  * @fifo_size: The size of the FIFO (for periodic IN endpoints)
103  * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
104  * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
105  * @last_load: The offset of data for the last start of request.
106  * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
107  * @target_frame: Targeted frame num to setup next ISOC transfer
108  * @frame_overrun: Indicates SOF number overrun in DSTS
109  *
110  * This is the driver's state for each registered endpoint, allowing it
111  * to keep track of transactions that need doing. Each endpoint has a
112  * lock to protect the state, to try and avoid using an overall lock
113  * for the host controller as much as possible.
114  *
115  * For periodic IN endpoints, we have fifo_size and fifo_load to try
116  * and keep track of the amount of data in the periodic FIFO for each
117  * of these as we don't have a status register that tells us how much
118  * is in each of them. (note, this may actually be useless information
119  * as in shared-fifo mode periodic in acts like a single-frame packet
120  * buffer than a fifo)
121  */
122 struct dwc2_hsotg_ep {
123 	struct usb_ep           ep;
124 	struct list_head        queue;
125 	struct dwc2_hsotg       *parent;
126 	struct dwc2_hsotg_req    *req;
127 	struct dentry           *debugfs;
128 
129 	unsigned long           total_data;
130 	unsigned int            size_loaded;
131 	unsigned int            last_load;
132 	unsigned int            fifo_load;
133 	unsigned short          fifo_size;
134 	unsigned short		fifo_index;
135 
136 	unsigned char           dir_in;
137 	unsigned char           map_dir;
138 	unsigned char           index;
139 	unsigned char           mc;
140 	u16                     interval;
141 
142 	unsigned int            halted:1;
143 	unsigned int            periodic:1;
144 	unsigned int            isochronous:1;
145 	unsigned int            send_zlp:1;
146 	unsigned int            wedged:1;
147 	unsigned int            target_frame;
148 #define TARGET_FRAME_INITIAL   0xFFFFFFFF
149 	bool			frame_overrun;
150 
151 	dma_addr_t		desc_list_dma;
152 	struct dwc2_dma_desc	*desc_list;
153 	u8			desc_count;
154 
155 	unsigned int		next_desc;
156 	unsigned int		compl_desc;
157 
158 	char                    name[10];
159 };
160 
161 /**
162  * struct dwc2_hsotg_req - data transfer request
163  * @req: The USB gadget request
164  * @queue: The list of requests for the endpoint this is queued for.
165  * @saved_req_buf: variable to save req.buf when bounce buffers are used.
166  */
167 struct dwc2_hsotg_req {
168 	struct usb_request      req;
169 	struct list_head        queue;
170 	void *saved_req_buf;
171 };
172 
173 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
174 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
175 #define call_gadget(_hs, _entry) \
176 do { \
177 	if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
178 		(_hs)->driver && (_hs)->driver->_entry) { \
179 		spin_unlock(&_hs->lock); \
180 		(_hs)->driver->_entry(&(_hs)->gadget); \
181 		spin_lock(&_hs->lock); \
182 	} \
183 } while (0)
184 #else
185 #define call_gadget(_hs, _entry)	do {} while (0)
186 #endif
187 
188 struct dwc2_hsotg;
189 struct dwc2_host_chan;
190 
191 /* Device States */
192 enum dwc2_lx_state {
193 	DWC2_L0,	/* On state */
194 	DWC2_L1,	/* LPM sleep state */
195 	DWC2_L2,	/* USB suspend state */
196 	DWC2_L3,	/* Off state */
197 };
198 
199 /* Gadget ep0 states */
200 enum dwc2_ep0_state {
201 	DWC2_EP0_SETUP,
202 	DWC2_EP0_DATA_IN,
203 	DWC2_EP0_DATA_OUT,
204 	DWC2_EP0_STATUS_IN,
205 	DWC2_EP0_STATUS_OUT,
206 };
207 
208 /**
209  * struct dwc2_core_params - Parameters for configuring the core
210  *
211  * @otg_caps:           Specifies the OTG capabilities. OTG caps from the platform parameters,
212  *                      used to setup the:
213  *                       - HNP and SRP capable
214  *                       - SRP Only capable
215  *                       - No HNP/SRP capable (always available)
216  *                       Defaults to best available option
217  *                       - OTG revision number the device is compliant with, in binary-coded
218  *                         decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps)
219  * @host_dma:           Specifies whether to use slave or DMA mode for accessing
220  *                      the data FIFOs. The driver will automatically detect the
221  *                      value for this parameter if none is specified.
222  *                       0 - Slave (always available)
223  *                       1 - DMA (default, if available)
224  * @dma_desc_enable:    When DMA mode is enabled, specifies whether to use
225  *                      address DMA mode or descriptor DMA mode for accessing
226  *                      the data FIFOs. The driver will automatically detect the
227  *                      value for this if none is specified.
228  *                       0 - Address DMA
229  *                       1 - Descriptor DMA (default, if available)
230  * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
231  *                      address DMA mode or descriptor DMA mode for accessing
232  *                      the data FIFOs in Full Speed mode only. The driver
233  *                      will automatically detect the value for this if none is
234  *                      specified.
235  *                       0 - Address DMA
236  *                       1 - Descriptor DMA in FS (default, if available)
237  * @speed:              Specifies the maximum speed of operation in host and
238  *                      device mode. The actual speed depends on the speed of
239  *                      the attached device and the value of phy_type.
240  *                       0 - High Speed
241  *                           (default when phy_type is UTMI+ or ULPI)
242  *                       1 - Full Speed
243  *                           (default when phy_type is Full Speed)
244  * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
245  *                       1 - Allow dynamic FIFO sizing (default, if available)
246  * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
247  *                      are enabled for non-periodic IN endpoints in device
248  *                      mode.
249  * @host_rx_fifo_size:  Number of 4-byte words in the Rx FIFO in host mode when
250  *                      dynamic FIFO sizing is enabled
251  *                       16 to 32768
252  *                      Actual maximum value is autodetected and also
253  *                      the default.
254  * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
255  *                      in host mode when dynamic FIFO sizing is enabled
256  *                       16 to 32768
257  *                      Actual maximum value is autodetected and also
258  *                      the default.
259  * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
260  *                      host mode when dynamic FIFO sizing is enabled
261  *                       16 to 32768
262  *                      Actual maximum value is autodetected and also
263  *                      the default.
264  * @max_transfer_size:  The maximum transfer size supported, in bytes
265  *                       2047 to 65,535
266  *                      Actual maximum value is autodetected and also
267  *                      the default.
268  * @max_packet_count:   The maximum number of packets in a transfer
269  *                       15 to 511
270  *                      Actual maximum value is autodetected and also
271  *                      the default.
272  * @host_channels:      The number of host channel registers to use
273  *                       1 to 16
274  *                      Actual maximum value is autodetected and also
275  *                      the default.
276  * @phy_type:           Specifies the type of PHY interface to use. By default,
277  *                      the driver will automatically detect the phy_type.
278  *                       0 - Full Speed Phy
279  *                       1 - UTMI+ Phy
280  *                       2 - ULPI Phy
281  *                      Defaults to best available option (2, 1, then 0)
282  * @phy_utmi_width:     Specifies the UTMI+ Data Width (in bits). This parameter
283  *                      is applicable for a phy_type of UTMI+ or ULPI. (For a
284  *                      ULPI phy_type, this parameter indicates the data width
285  *                      between the MAC and the ULPI Wrapper.) Also, this
286  *                      parameter is applicable only if the OTG_HSPHY_WIDTH cC
287  *                      parameter was set to "8 and 16 bits", meaning that the
288  *                      core has been configured to work at either data path
289  *                      width.
290  *                       8 or 16 (default 16 if available)
291  * @phy_ulpi_ddr:       Specifies whether the ULPI operates at double or single
292  *                      data rate. This parameter is only applicable if phy_type
293  *                      is ULPI.
294  *                       0 - single data rate ULPI interface with 8 bit wide
295  *                           data bus (default)
296  *                       1 - double data rate ULPI interface with 4 bit wide
297  *                           data bus
298  * @phy_ulpi_ext_vbus:  For a ULPI phy, specifies whether to use the internal or
299  *                      external supply to drive the VBus
300  *                       0 - Internal supply (default)
301  *                       1 - External supply
302  * @i2c_enable:         Specifies whether to use the I2Cinterface for a full
303  *                      speed PHY. This parameter is only applicable if phy_type
304  *                      is FS.
305  *                       0 - No (default)
306  *                       1 - Yes
307  * @ipg_isoc_en:        Indicates the IPG supports is enabled or disabled.
308  *                       0 - Disable (default)
309  *                       1 - Enable
310  * @acg_enable:		For enabling Active Clock Gating in the controller
311  *                       0 - No
312  *                       1 - Yes
313  * @ulpi_fs_ls:         Make ULPI phy operate in FS/LS mode only
314  *                       0 - No (default)
315  *                       1 - Yes
316  * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
317  *                      when attached to a Full Speed or Low Speed device in
318  *                      host mode.
319  *                       0 - Don't support low power mode (default)
320  *                       1 - Support low power mode
321  * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
322  *                      when connected to a Low Speed device in host
323  *                      mode. This parameter is applicable only if
324  *                      host_support_fs_ls_low_power is enabled.
325  *                       0 - 48 MHz
326  *                           (default when phy_type is UTMI+ or ULPI)
327  *                       1 - 6 MHz
328  *                           (default when phy_type is Full Speed)
329  * @oc_disable:		Flag to disable overcurrent condition.
330  *			0 - Allow overcurrent condition to get detected
331  *			1 - Disable overcurrent condtion to get detected
332  * @ts_dline:           Enable Term Select Dline pulsing
333  *                       0 - No (default)
334  *                       1 - Yes
335  * @reload_ctl:         Allow dynamic reloading of HFIR register during runtime
336  *                       0 - No (default for core < 2.92a)
337  *                       1 - Yes (default for core >= 2.92a)
338  * @ahbcfg:             This field allows the default value of the GAHBCFG
339  *                      register to be overridden
340  *                       -1         - GAHBCFG value will be set to 0x06
341  *                                    (INCR, default)
342  *                       all others - GAHBCFG value will be overridden with
343  *                                    this value
344  *                      Not all bits can be controlled like this, the
345  *                      bits defined by GAHBCFG_CTRL_MASK are controlled
346  *                      by the driver and are ignored in this
347  *                      configuration value.
348  * @uframe_sched:       True to enable the microframe scheduler
349  * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
350  *                      Disable CONIDSTSCHNG controller interrupt in such
351  *                      case.
352  *                      0 - No (default)
353  *                      1 - Yes
354  * @power_down:         Specifies whether the controller support power_down.
355  *			If power_down is enabled, the controller will enter
356  *			power_down in both peripheral and host mode when
357  *			needed.
358  *			0 - No (default)
359  *			1 - Partial power down
360  *			2 - Hibernation
361  * @no_clock_gating:	Specifies whether to avoid clock gating feature.
362  *			0 - No (use clock gating)
363  *			1 - Yes (avoid it)
364  * @lpm:		Enable LPM support.
365  *			0 - No
366  *			1 - Yes
367  * @lpm_clock_gating:		Enable core PHY clock gating.
368  *			0 - No
369  *			1 - Yes
370  * @besl:		Enable LPM Errata support.
371  *			0 - No
372  *			1 - Yes
373  * @hird_threshold_en:	HIRD or HIRD Threshold enable.
374  *			0 - No
375  *			1 - Yes
376  * @hird_threshold:	Value of BESL or HIRD Threshold.
377  * @ref_clk_per:        Indicates in terms of pico seconds the period
378  *                      of ref_clk.
379  *			62500 - 16MHz
380  *                      58823 - 17MHz
381  *                      52083 - 19.2MHz
382  *			50000 - 20MHz
383  *			41666 - 24MHz
384  *			33333 - 30MHz (default)
385  *			25000 - 40MHz
386  * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
387  *                      the controller should generate an interrupt if the
388  *                      device had been in L1 state until that period.
389  *                      This is used by SW to initiate Remote WakeUp in the
390  *                      controller so as to sync to the uF number from the host.
391  * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
392  *			register.
393  *			0 - Deactivate the transceiver (default)
394  *			1 - Activate the transceiver
395  * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
396  *			detection using GGPIO register.
397  *			0 - Deactivate the external level detection (default)
398  *			1 - Activate the external level detection
399  * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent
400  *			detection.
401  *			0 - Deactivate the overcurrent detection
402  *			1 - Activate the overcurrent detection (default)
403  * @g_dma:              Enables gadget dma usage (default: autodetect).
404  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
405  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in
406  *			DWORDS from 16-32768 (default: 2048 if
407  *			possible, otherwise autodetect).
408  * @g_np_tx_fifo_size:	The non-periodic tx fifo size for the device in
409  *			DWORDS from 16-32768 (default: 1024 if
410  *			possible, otherwise autodetect).
411  * @g_tx_fifo_size:	An array of TX fifo sizes in dedicated fifo
412  *			mode. Each value corresponds to one EP
413  *			starting from EP1 (max 15 values). Sizes are
414  *			in DWORDS with possible values from
415  *			16-32768 (default: 256, 256, 256, 256, 768,
416  *			768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
417  * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
418  *                      while full&low speed device connect. And change speed
419  *                      back to DWC2_SPEED_PARAM_HIGH while device is gone.
420  *			0 - No (default)
421  *			1 - Yes
422  * @service_interval:   Enable service interval based scheduling.
423  *                      0 - No
424  *                      1 - Yes
425  *
426  * The following parameters may be specified when starting the module. These
427  * parameters define how the DWC_otg controller should be configured. A
428  * value of -1 (or any other out of range value) for any parameter means
429  * to read the value from hardware (if possible) or use the builtin
430  * default described above.
431  */
432 struct dwc2_core_params {
433 	struct usb_otg_caps otg_caps;
434 	u8 phy_type;
435 #define DWC2_PHY_TYPE_PARAM_FS		0
436 #define DWC2_PHY_TYPE_PARAM_UTMI	1
437 #define DWC2_PHY_TYPE_PARAM_ULPI	2
438 
439 	u8 speed;
440 #define DWC2_SPEED_PARAM_HIGH	0
441 #define DWC2_SPEED_PARAM_FULL	1
442 #define DWC2_SPEED_PARAM_LOW	2
443 
444 	u8 phy_utmi_width;
445 	bool phy_ulpi_ddr;
446 	bool phy_ulpi_ext_vbus;
447 	bool enable_dynamic_fifo;
448 	bool en_multiple_tx_fifo;
449 	bool i2c_enable;
450 	bool acg_enable;
451 	bool ulpi_fs_ls;
452 	bool ts_dline;
453 	bool reload_ctl;
454 	bool uframe_sched;
455 	bool external_id_pin_ctl;
456 
457 	int power_down;
458 #define DWC2_POWER_DOWN_PARAM_NONE		0
459 #define DWC2_POWER_DOWN_PARAM_PARTIAL		1
460 #define DWC2_POWER_DOWN_PARAM_HIBERNATION	2
461 	bool no_clock_gating;
462 
463 	bool lpm;
464 	bool lpm_clock_gating;
465 	bool besl;
466 	bool hird_threshold_en;
467 	bool service_interval;
468 	u8 hird_threshold;
469 	bool activate_stm_fs_transceiver;
470 	bool activate_stm_id_vb_detection;
471 	bool activate_ingenic_overcurrent_detection;
472 	bool ipg_isoc_en;
473 	u16 max_packet_count;
474 	u32 max_transfer_size;
475 	u32 ahbcfg;
476 
477 	/* GREFCLK parameters */
478 	u32 ref_clk_per;
479 	u16 sof_cnt_wkup_alert;
480 
481 	/* Host parameters */
482 	bool host_dma;
483 	bool dma_desc_enable;
484 	bool dma_desc_fs_enable;
485 	bool host_support_fs_ls_low_power;
486 	bool host_ls_low_power_phy_clk;
487 	bool oc_disable;
488 
489 	u8 host_channels;
490 	u16 host_rx_fifo_size;
491 	u16 host_nperio_tx_fifo_size;
492 	u16 host_perio_tx_fifo_size;
493 
494 	/* Gadget parameters */
495 	bool g_dma;
496 	bool g_dma_desc;
497 	u32 g_rx_fifo_size;
498 	u32 g_np_tx_fifo_size;
499 	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
500 
501 	bool change_speed_quirk;
502 };
503 
504 /**
505  * struct dwc2_hw_params - Autodetected parameters.
506  *
507  * These parameters are the various parameters read from hardware
508  * registers during initialization. They typically contain the best
509  * supported or maximum value that can be configured in the
510  * corresponding dwc2_core_params value.
511  *
512  * The values that are not in dwc2_core_params are documented below.
513  *
514  * @op_mode:             Mode of Operation
515  *                       0 - HNP- and SRP-Capable OTG (Host & Device)
516  *                       1 - SRP-Capable OTG (Host & Device)
517  *                       2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
518  *                       3 - SRP-Capable Device
519  *                       4 - Non-OTG Device
520  *                       5 - SRP-Capable Host
521  *                       6 - Non-OTG Host
522  * @arch:                Architecture
523  *                       0 - Slave only
524  *                       1 - External DMA
525  *                       2 - Internal DMA
526  * @ipg_isoc_en:        This feature indicates that the controller supports
527  *                      the worst-case scenario of Rx followed by Rx
528  *                      Interpacket Gap (IPG) (32 bitTimes) as per the utmi
529  *                      specification for any token following ISOC OUT token.
530  *                       0 - Don't support
531  *                       1 - Support
532  * @power_optimized:    Are power optimizations enabled?
533  * @num_dev_ep:         Number of device endpoints available
534  * @num_dev_in_eps:     Number of device IN endpoints available
535  * @num_dev_perio_in_ep: Number of device periodic IN endpoints
536  *                       available
537  * @dev_token_q_depth:  Device Mode IN Token Sequence Learning Queue
538  *                      Depth
539  *                       0 to 30
540  * @host_perio_tx_q_depth:
541  *                      Host Mode Periodic Request Queue Depth
542  *                       2, 4 or 8
543  * @nperio_tx_q_depth:
544  *                      Non-Periodic Request Queue Depth
545  *                       2, 4 or 8
546  * @hs_phy_type:         High-speed PHY interface type
547  *                       0 - High-speed interface not supported
548  *                       1 - UTMI+
549  *                       2 - ULPI
550  *                       3 - UTMI+ and ULPI
551  * @fs_phy_type:         Full-speed PHY interface type
552  *                       0 - Full speed interface not supported
553  *                       1 - Dedicated full speed interface
554  *                       2 - FS pins shared with UTMI+ pins
555  *                       3 - FS pins shared with ULPI pins
556  * @total_fifo_size:    Total internal RAM for FIFOs (bytes)
557  * @hibernation:	Is hibernation enabled?
558  * @utmi_phy_data_width: UTMI+ PHY data width
559  *                       0 - 8 bits
560  *                       1 - 16 bits
561  *                       2 - 8 or 16 bits
562  * @snpsid:             Value from SNPSID register
563  * @dev_ep_dirs:        Direction of device endpoints (GHWCFG1)
564  * @g_tx_fifo_size:	Power-on values of TxFIFO sizes
565  * @dma_desc_enable:    When DMA mode is enabled, specifies whether to use
566  *                      address DMA mode or descriptor DMA mode for accessing
567  *                      the data FIFOs. The driver will automatically detect the
568  *                      value for this if none is specified.
569  *                       0 - Address DMA
570  *                       1 - Descriptor DMA (default, if available)
571  * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
572  *                       1 - Allow dynamic FIFO sizing (default, if available)
573  * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
574  *                      are enabled for non-periodic IN endpoints in device
575  *                      mode.
576  * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
577  *                      in host mode when dynamic FIFO sizing is enabled
578  *                       16 to 32768
579  *                      Actual maximum value is autodetected and also
580  *                      the default.
581  * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
582  *                      host mode when dynamic FIFO sizing is enabled
583  *                       16 to 32768
584  *                      Actual maximum value is autodetected and also
585  *                      the default.
586  * @max_transfer_size:  The maximum transfer size supported, in bytes
587  *                       2047 to 65,535
588  *                      Actual maximum value is autodetected and also
589  *                      the default.
590  * @max_packet_count:   The maximum number of packets in a transfer
591  *                       15 to 511
592  *                      Actual maximum value is autodetected and also
593  *                      the default.
594  * @host_channels:      The number of host channel registers to use
595  *                       1 to 16
596  *                      Actual maximum value is autodetected and also
597  *                      the default.
598  * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
599  *			     in device mode when dynamic FIFO sizing is enabled
600  *			     16 to 32768
601  *			     Actual maximum value is autodetected and also
602  *			     the default.
603  * @i2c_enable:         Specifies whether to use the I2Cinterface for a full
604  *                      speed PHY. This parameter is only applicable if phy_type
605  *                      is FS.
606  *                       0 - No (default)
607  *                       1 - Yes
608  * @acg_enable:		For enabling Active Clock Gating in the controller
609  *                       0 - Disable
610  *                       1 - Enable
611  * @lpm_mode:		For enabling Link Power Management in the controller
612  *                       0 - Disable
613  *                       1 - Enable
614  * @rx_fifo_size:	Number of 4-byte words in the  Rx FIFO when dynamic
615  *			FIFO sizing is enabled 16 to 32768
616  *			Actual maximum value is autodetected and also
617  *			the default.
618  * @service_interval_mode: For enabling service interval based scheduling in the
619  *                         controller.
620  *                           0 - Disable
621  *                           1 - Enable
622  */
623 struct dwc2_hw_params {
624 	unsigned op_mode:3;
625 	unsigned arch:2;
626 	unsigned dma_desc_enable:1;
627 	unsigned enable_dynamic_fifo:1;
628 	unsigned en_multiple_tx_fifo:1;
629 	unsigned rx_fifo_size:16;
630 	unsigned host_nperio_tx_fifo_size:16;
631 	unsigned dev_nperio_tx_fifo_size:16;
632 	unsigned host_perio_tx_fifo_size:16;
633 	unsigned nperio_tx_q_depth:3;
634 	unsigned host_perio_tx_q_depth:3;
635 	unsigned dev_token_q_depth:5;
636 	unsigned max_transfer_size:26;
637 	unsigned max_packet_count:11;
638 	unsigned host_channels:5;
639 	unsigned hs_phy_type:2;
640 	unsigned fs_phy_type:2;
641 	unsigned i2c_enable:1;
642 	unsigned acg_enable:1;
643 	unsigned num_dev_ep:4;
644 	unsigned num_dev_in_eps : 4;
645 	unsigned num_dev_perio_in_ep:4;
646 	unsigned total_fifo_size:16;
647 	unsigned power_optimized:1;
648 	unsigned hibernation:1;
649 	unsigned utmi_phy_data_width:2;
650 	unsigned lpm_mode:1;
651 	unsigned ipg_isoc_en:1;
652 	unsigned service_interval_mode:1;
653 	u32 snpsid;
654 	u32 dev_ep_dirs;
655 	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
656 };
657 
658 /* Size of control and EP0 buffers */
659 #define DWC2_CTRL_BUFF_SIZE 8
660 
661 /**
662  * struct dwc2_gregs_backup - Holds global registers state before
663  * entering partial power down
664  * @gotgctl:		Backup of GOTGCTL register
665  * @gintmsk:		Backup of GINTMSK register
666  * @gahbcfg:		Backup of GAHBCFG register
667  * @gusbcfg:		Backup of GUSBCFG register
668  * @grxfsiz:		Backup of GRXFSIZ register
669  * @gnptxfsiz:		Backup of GNPTXFSIZ register
670  * @gi2cctl:		Backup of GI2CCTL register
671  * @glpmcfg:		Backup of GLPMCFG register
672  * @gdfifocfg:		Backup of GDFIFOCFG register
673  * @pcgcctl:		Backup of PCGCCTL register
674  * @pcgcctl1:		Backup of PCGCCTL1 register
675  * @dtxfsiz:		Backup of DTXFSIZ registers for each endpoint
676  * @gpwrdn:		Backup of GPWRDN register
677  * @valid:		True if registers values backuped.
678  */
679 struct dwc2_gregs_backup {
680 	u32 gotgctl;
681 	u32 gintmsk;
682 	u32 gahbcfg;
683 	u32 gusbcfg;
684 	u32 grxfsiz;
685 	u32 gnptxfsiz;
686 	u32 gi2cctl;
687 	u32 glpmcfg;
688 	u32 pcgcctl;
689 	u32 pcgcctl1;
690 	u32 gdfifocfg;
691 	u32 gpwrdn;
692 	bool valid;
693 };
694 
695 /**
696  * struct dwc2_dregs_backup - Holds device registers state before
697  * entering partial power down
698  * @dcfg:		Backup of DCFG register
699  * @dctl:		Backup of DCTL register
700  * @daintmsk:		Backup of DAINTMSK register
701  * @diepmsk:		Backup of DIEPMSK register
702  * @doepmsk:		Backup of DOEPMSK register
703  * @diepctl:		Backup of DIEPCTL register
704  * @dieptsiz:		Backup of DIEPTSIZ register
705  * @diepdma:		Backup of DIEPDMA register
706  * @doepctl:		Backup of DOEPCTL register
707  * @doeptsiz:		Backup of DOEPTSIZ register
708  * @doepdma:		Backup of DOEPDMA register
709  * @dtxfsiz:		Backup of DTXFSIZ registers for each endpoint
710  * @valid:      True if registers values backuped.
711  */
712 struct dwc2_dregs_backup {
713 	u32 dcfg;
714 	u32 dctl;
715 	u32 daintmsk;
716 	u32 diepmsk;
717 	u32 doepmsk;
718 	u32 diepctl[MAX_EPS_CHANNELS];
719 	u32 dieptsiz[MAX_EPS_CHANNELS];
720 	u32 diepdma[MAX_EPS_CHANNELS];
721 	u32 doepctl[MAX_EPS_CHANNELS];
722 	u32 doeptsiz[MAX_EPS_CHANNELS];
723 	u32 doepdma[MAX_EPS_CHANNELS];
724 	u32 dtxfsiz[MAX_EPS_CHANNELS];
725 	bool valid;
726 };
727 
728 /**
729  * struct dwc2_hregs_backup - Holds host registers state before
730  * entering partial power down
731  * @hcfg:		Backup of HCFG register
732  * @hflbaddr:		Backup of HFLBADDR register
733  * @haintmsk:		Backup of HAINTMSK register
734  * @hcchar:		Backup of HCCHAR register
735  * @hcsplt:		Backup of HCSPLT register
736  * @hcintmsk:		Backup of HCINTMSK register
737  * @hctsiz:		Backup of HCTSIZ register
738  * @hdma:		Backup of HCDMA register
739  * @hcdmab:		Backup of HCDMAB register
740  * @hprt0:		Backup of HPTR0 register
741  * @hfir:		Backup of HFIR register
742  * @hptxfsiz:		Backup of HPTXFSIZ register
743  * @valid:      True if registers values backuped.
744  */
745 struct dwc2_hregs_backup {
746 	u32 hcfg;
747 	u32 hflbaddr;
748 	u32 haintmsk;
749 	u32 hcchar[MAX_EPS_CHANNELS];
750 	u32 hcsplt[MAX_EPS_CHANNELS];
751 	u32 hcintmsk[MAX_EPS_CHANNELS];
752 	u32 hctsiz[MAX_EPS_CHANNELS];
753 	u32 hcidma[MAX_EPS_CHANNELS];
754 	u32 hcidmab[MAX_EPS_CHANNELS];
755 	u32 hprt0;
756 	u32 hfir;
757 	u32 hptxfsiz;
758 	bool valid;
759 };
760 
761 /*
762  * Constants related to high speed periodic scheduling
763  *
764  * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long.  From a
765  * reservation point of view it's assumed that the schedule goes right back to
766  * the beginning after the end of the schedule.
767  *
768  * What does that mean for scheduling things with a long interval?  It means
769  * we'll reserve time for them in every possible microframe that they could
770  * ever be scheduled in.  ...but we'll still only actually schedule them as
771  * often as they were requested.
772  *
773  * We keep our schedule in a "bitmap" structure.  This simplifies having
774  * to keep track of and merge intervals: we just let the bitmap code do most
775  * of the heavy lifting.  In a way scheduling is much like memory allocation.
776  *
777  * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
778  * supposed to schedule for periodic transfers).  That's according to spec.
779  *
780  * Note that though we only schedule 80% of each microframe, the bitmap that we
781  * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
782  * space for each uFrame).
783  *
784  * Requirements:
785  * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
786  * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
787  *   could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
788  *   be bugs).  The 8 comes from the USB spec: number of microframes per frame.
789  */
790 #define DWC2_US_PER_UFRAME		125
791 #define DWC2_HS_PERIODIC_US_PER_UFRAME	100
792 
793 #define DWC2_HS_SCHEDULE_UFRAMES	8
794 #define DWC2_HS_SCHEDULE_US		(DWC2_HS_SCHEDULE_UFRAMES * \
795 					 DWC2_HS_PERIODIC_US_PER_UFRAME)
796 
797 /*
798  * Constants related to low speed scheduling
799  *
800  * For high speed we schedule every 1us.  For low speed that's a bit overkill,
801  * so we make up a unit called a "slice" that's worth 25us.  There are 40
802  * slices in a full frame and we can schedule 36 of those (90%) for periodic
803  * transfers.
804  *
805  * Our low speed schedule can be as short as 1 frame or could be longer.  When
806  * we only schedule 1 frame it means that we'll need to reserve a time every
807  * frame even for things that only transfer very rarely, so something that runs
808  * every 2048 frames will get time reserved in every frame.  Our low speed
809  * schedule can be longer and we'll be able to handle more overlap, but that
810  * will come at increased memory cost and increased time to schedule.
811  *
812  * Note: one other advantage of a short low speed schedule is that if we mess
813  * up and miss scheduling we can jump in and use any of the slots that we
814  * happened to reserve.
815  *
816  * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
817  * the schedule.  There will be one schedule per TT.
818  *
819  * Requirements:
820  * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
821  */
822 #define DWC2_US_PER_SLICE	25
823 #define DWC2_SLICES_PER_UFRAME	(DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
824 
825 #define DWC2_ROUND_US_TO_SLICE(us) \
826 				(DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
827 				 DWC2_US_PER_SLICE)
828 
829 #define DWC2_LS_PERIODIC_US_PER_FRAME \
830 				900
831 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
832 				(DWC2_LS_PERIODIC_US_PER_FRAME / \
833 				 DWC2_US_PER_SLICE)
834 
835 #define DWC2_LS_SCHEDULE_FRAMES	1
836 #define DWC2_LS_SCHEDULE_SLICES	(DWC2_LS_SCHEDULE_FRAMES * \
837 				 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
838 
839 /**
840  * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
841  * and periodic schedules
842  *
843  * These are common for both host and peripheral modes:
844  *
845  * @dev:                The struct device pointer
846  * @regs:		Pointer to controller regs
847  * @hw_params:          Parameters that were autodetected from the
848  *                      hardware registers
849  * @params:	Parameters that define how the core should be configured
850  * @op_state:           The operational State, during transitions (a_host=>
851  *                      a_peripheral and b_device=>b_host) this may not match
852  *                      the core, but allows the software to determine
853  *                      transitions
854  * @dr_mode:            Requested mode of operation, one of following:
855  *                      - USB_DR_MODE_PERIPHERAL
856  *                      - USB_DR_MODE_HOST
857  *                      - USB_DR_MODE_OTG
858  * @role_sw:		usb_role_switch handle
859  * @role_sw_default_mode: default operation mode of controller while usb role
860  *			is USB_ROLE_NONE
861  * @hcd_enabled:	Host mode sub-driver initialization indicator.
862  * @gadget_enabled:	Peripheral mode sub-driver initialization indicator.
863  * @ll_hw_enabled:	Status of low-level hardware resources.
864  * @hibernated:		True if core is hibernated
865  * @in_ppd:		True if core is partial power down mode.
866  * @bus_suspended:	True if bus is suspended
867  * @reset_phy_on_wake:	Quirk saying that we should assert PHY reset on a
868  *			remote wakeup.
869  * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
870  * @need_phy_for_wake:	Quirk saying that we should keep the PHY on at
871  *			suspend if we need USB to wake us up.
872  * @frame_number:       Frame number read from the core. For both device
873  *			and host modes. The value ranges are from 0
874  *			to HFNUM_MAX_FRNUM.
875  * @phy:                The otg phy transceiver structure for phy control.
876  * @uphy:               The otg phy transceiver structure for old USB phy
877  *                      control.
878  * @plat:               The platform specific configuration data. This can be
879  *                      removed once all SoCs support usb transceiver.
880  * @supplies:           Definition of USB power supplies
881  * @vbus_supply:        Regulator supplying vbus.
882  * @usb33d:		Optional 3.3v regulator used on some stm32 devices to
883  *			supply ID and VBUS detection hardware.
884  * @lock:		Spinlock that protects all the driver data structures
885  * @priv:		Stores a pointer to the struct usb_hcd
886  * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
887  *                      transfer are in process of being queued
888  * @srp_success:        Stores status of SRP request in the case of a FS PHY
889  *                      with an I2C interface
890  * @wq_otg:             Workqueue object used for handling of some interrupts
891  * @wf_otg:             Work object for handling Connector ID Status Change
892  *                      interrupt
893  * @wkp_timer:          Timer object for handling Wakeup Detected interrupt
894  * @lx_state:           Lx state of connected device
895  * @gr_backup: Backup of global registers during suspend
896  * @dr_backup: Backup of device registers during suspend
897  * @hr_backup: Backup of host registers during suspend
898  * @needs_byte_swap:		Specifies whether the opposite endianness.
899  *
900  * These are for host mode:
901  *
902  * @flags:              Flags for handling root port state changes
903  * @flags.d32:          Contain all root port flags
904  * @flags.b:            Separate root port flags from each other
905  * @flags.b.port_connect_status_change: True if root port connect status
906  *                      changed
907  * @flags.b.port_connect_status: True if device connected to root port
908  * @flags.b.port_reset_change: True if root port reset status changed
909  * @flags.b.port_enable_change: True if root port enable status changed
910  * @flags.b.port_suspend_change: True if root port suspend status changed
911  * @flags.b.port_over_current_change: True if root port over current state
912  *                       changed.
913  * @flags.b.port_l1_change: True if root port l1 status changed
914  * @flags.b.reserved:   Reserved bits of root port register
915  * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
916  *                      Transfers associated with these QHs are not currently
917  *                      assigned to a host channel.
918  * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
919  *                      Transfers associated with these QHs are currently
920  *                      assigned to a host channel.
921  * @non_periodic_qh_ptr: Pointer to next QH to process in the active
922  *                      non-periodic schedule
923  * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
924  *                      Transfers associated with these QHs are not currently
925  *                      assigned to a host channel.
926  * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
927  *                      list of QHs for periodic transfers that are _not_
928  *                      scheduled for the next frame. Each QH in the list has an
929  *                      interval counter that determines when it needs to be
930  *                      scheduled for execution. This scheduling mechanism
931  *                      allows only a simple calculation for periodic bandwidth
932  *                      used (i.e. must assume that all periodic transfers may
933  *                      need to execute in the same frame). However, it greatly
934  *                      simplifies scheduling and should be sufficient for the
935  *                      vast majority of OTG hosts, which need to connect to a
936  *                      small number of peripherals at one time. Items move from
937  *                      this list to periodic_sched_ready when the QH interval
938  *                      counter is 0 at SOF.
939  * @periodic_sched_ready:  List of periodic QHs that are ready for execution in
940  *                      the next frame, but have not yet been assigned to host
941  *                      channels. Items move from this list to
942  *                      periodic_sched_assigned as host channels become
943  *                      available during the current frame.
944  * @periodic_sched_assigned: List of periodic QHs to be executed in the next
945  *                      frame that are assigned to host channels. Items move
946  *                      from this list to periodic_sched_queued as the
947  *                      transactions for the QH are queued to the DWC_otg
948  *                      controller.
949  * @periodic_sched_queued: List of periodic QHs that have been queued for
950  *                      execution. Items move from this list to either
951  *                      periodic_sched_inactive or periodic_sched_ready when the
952  *                      channel associated with the transfer is released. If the
953  *                      interval for the QH is 1, the item moves to
954  *                      periodic_sched_ready because it must be rescheduled for
955  *                      the next frame. Otherwise, the item moves to
956  *                      periodic_sched_inactive.
957  * @split_order:        List keeping track of channels doing splits, in order.
958  * @periodic_usecs:     Total bandwidth claimed so far for periodic transfers.
959  *                      This value is in microseconds per (micro)frame. The
960  *                      assumption is that all periodic transfers may occur in
961  *                      the same (micro)frame.
962  * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
963  *                      host is in high speed mode; low speed schedules are
964  *                      stored elsewhere since we need one per TT.
965  * @periodic_qh_count:  Count of periodic QHs, if using several eps. Used for
966  *                      SOF enable/disable.
967  * @free_hc_list:       Free host channels in the controller. This is a list of
968  *                      struct dwc2_host_chan items.
969  * @periodic_channels:  Number of host channels assigned to periodic transfers.
970  *                      Currently assuming that there is a dedicated host
971  *                      channel for each periodic transaction and at least one
972  *                      host channel is available for non-periodic transactions.
973  * @non_periodic_channels: Number of host channels assigned to non-periodic
974  *                      transfers
975  * @available_host_channels: Number of host channels available for the
976  *			     microframe scheduler to use
977  * @hc_ptr_array:       Array of pointers to the host channel descriptors.
978  *                      Allows accessing a host channel descriptor given the
979  *                      host channel number. This is useful in interrupt
980  *                      handlers.
981  * @status_buf:         Buffer used for data received during the status phase of
982  *                      a control transfer.
983  * @status_buf_dma:     DMA address for status_buf
984  * @start_work:         Delayed work for handling host A-cable connection
985  * @reset_work:         Delayed work for handling a port reset
986  * @phy_reset_work:     Work structure for doing a PHY reset
987  * @otg_port:           OTG port number
988  * @frame_list:         Frame list
989  * @frame_list_dma:     Frame list DMA address
990  * @frame_list_sz:      Frame list size
991  * @desc_gen_cache:     Kmem cache for generic descriptors
992  * @desc_hsisoc_cache:  Kmem cache for hs isochronous descriptors
993  * @unaligned_cache:    Kmem cache for DMA mode to handle non-aligned buf
994  *
995  * These are for peripheral mode:
996  *
997  * @driver:             USB gadget driver
998  * @dedicated_fifos:    Set if the hardware has dedicated IN-EP fifos.
999  * @num_of_eps:         Number of available EPs (excluding EP0)
1000  * @debug_root:         Root directrory for debugfs.
1001  * @ep0_reply:          Request used for ep0 reply.
1002  * @ep0_buff:           Buffer for EP0 reply data, if needed.
1003  * @ctrl_buff:          Buffer for EP0 control requests.
1004  * @ctrl_req:           Request for EP0 control packets.
1005  * @ep0_state:          EP0 control transfers state
1006  * @delayed_status:		true when gadget driver asks for delayed status
1007  * @test_mode:          USB test mode requested by the host
1008  * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1009  *                      remote-wakeup signalling
1010  * @setup_desc_dma:	EP0 setup stage desc chain DMA address
1011  * @setup_desc:		EP0 setup stage desc chain pointer
1012  * @ctrl_in_desc_dma:	EP0 IN data phase desc chain DMA address
1013  * @ctrl_in_desc:	EP0 IN data phase desc chain pointer
1014  * @ctrl_out_desc_dma:	EP0 OUT data phase desc chain DMA address
1015  * @ctrl_out_desc:	EP0 OUT data phase desc chain pointer
1016  * @irq:		Interrupt request line number
1017  * @clk:		Pointer to otg clock
1018  * @utmi_clk:		Pointer to utmi_clk clock
1019  * @reset:		Pointer to dwc2 reset controller
1020  * @reset_ecc:          Pointer to dwc2 optional reset controller in Stratix10.
1021  * @regset:		A pointer to a struct debugfs_regset32, which contains
1022  *			a pointer to an array of register definitions, the
1023  *			array size and the base address where the register bank
1024  *			is to be found.
1025  * @last_frame_num:	Number of last frame. Range from 0 to  32768
1026  * @frame_num_array:    Used only  if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1027  *			defined, for missed SOFs tracking. Array holds that
1028  *			frame numbers, which not equal to last_frame_num +1
1029  * @last_frame_num_array:   Used only  if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1030  *			    defined, for missed SOFs tracking.
1031  *			    If current_frame_number != last_frame_num+1
1032  *			    then last_frame_num added to this array
1033  * @frame_num_idx:	Actual size of frame_num_array and last_frame_num_array
1034  * @dumped_frame_num_array:	1 - if missed SOFs frame numbers dumbed
1035  *				0 - if missed SOFs frame numbers not dumbed
1036  * @fifo_mem:			Total internal RAM for FIFOs (bytes)
1037  * @fifo_map:		Each bit intend for concrete fifo. If that bit is set,
1038  *			then that fifo is used
1039  * @gadget:		Represents a usb gadget device
1040  * @connected:		Used in slave mode. True if device connected with host
1041  * @eps_in:		The IN endpoints being supplied to the gadget framework
1042  * @eps_out:		The OUT endpoints being supplied to the gadget framework
1043  * @new_connection:	Used in host mode. True if there are new connected
1044  *			device
1045  * @enabled:		Indicates the enabling state of controller
1046  *
1047  */
1048 struct dwc2_hsotg {
1049 	struct device *dev;
1050 	void __iomem *regs;
1051 	/** Params detected from hardware */
1052 	struct dwc2_hw_params hw_params;
1053 	/** Params to actually use */
1054 	struct dwc2_core_params params;
1055 	enum usb_otg_state op_state;
1056 	enum usb_dr_mode dr_mode;
1057 	struct usb_role_switch *role_sw;
1058 	enum usb_dr_mode role_sw_default_mode;
1059 	unsigned int hcd_enabled:1;
1060 	unsigned int gadget_enabled:1;
1061 	unsigned int ll_hw_enabled:1;
1062 	unsigned int hibernated:1;
1063 	unsigned int in_ppd:1;
1064 	bool bus_suspended;
1065 	unsigned int reset_phy_on_wake:1;
1066 	unsigned int need_phy_for_wake:1;
1067 	unsigned int phy_off_for_suspend:1;
1068 	u16 frame_number;
1069 
1070 	struct phy *phy;
1071 	struct usb_phy *uphy;
1072 	struct dwc2_hsotg_plat *plat;
1073 	struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1074 	struct regulator *vbus_supply;
1075 	struct regulator *usb33d;
1076 
1077 	spinlock_t lock;
1078 	void *priv;
1079 	int     irq;
1080 	struct clk *clk;
1081 	struct clk *utmi_clk;
1082 	struct reset_control *reset;
1083 	struct reset_control *reset_ecc;
1084 
1085 	unsigned int queuing_high_bandwidth:1;
1086 	unsigned int srp_success:1;
1087 
1088 	struct workqueue_struct *wq_otg;
1089 	struct work_struct wf_otg;
1090 	struct timer_list wkp_timer;
1091 	enum dwc2_lx_state lx_state;
1092 	struct dwc2_gregs_backup gr_backup;
1093 	struct dwc2_dregs_backup dr_backup;
1094 	struct dwc2_hregs_backup hr_backup;
1095 
1096 	struct dentry *debug_root;
1097 	struct debugfs_regset32 *regset;
1098 	bool needs_byte_swap;
1099 
1100 	/* DWC OTG HW Release versions */
1101 #define DWC2_CORE_REV_4_30a	0x4f54430a
1102 #define DWC2_CORE_REV_2_71a	0x4f54271a
1103 #define DWC2_CORE_REV_2_72a     0x4f54272a
1104 #define DWC2_CORE_REV_2_80a	0x4f54280a
1105 #define DWC2_CORE_REV_2_90a	0x4f54290a
1106 #define DWC2_CORE_REV_2_91a	0x4f54291a
1107 #define DWC2_CORE_REV_2_92a	0x4f54292a
1108 #define DWC2_CORE_REV_2_94a	0x4f54294a
1109 #define DWC2_CORE_REV_3_00a	0x4f54300a
1110 #define DWC2_CORE_REV_3_10a	0x4f54310a
1111 #define DWC2_CORE_REV_4_00a	0x4f54400a
1112 #define DWC2_CORE_REV_4_20a	0x4f54420a
1113 #define DWC2_FS_IOT_REV_1_00a	0x5531100a
1114 #define DWC2_HS_IOT_REV_1_00a	0x5532100a
1115 #define DWC2_CORE_REV_MASK	0x0000ffff
1116 
1117 	/* DWC OTG HW Core ID */
1118 #define DWC2_OTG_ID		0x4f540000
1119 #define DWC2_FS_IOT_ID		0x55310000
1120 #define DWC2_HS_IOT_ID		0x55320000
1121 
1122 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1123 	union dwc2_hcd_internal_flags {
1124 		u32 d32;
1125 		struct {
1126 			unsigned port_connect_status_change:1;
1127 			unsigned port_connect_status:1;
1128 			unsigned port_reset_change:1;
1129 			unsigned port_enable_change:1;
1130 			unsigned port_suspend_change:1;
1131 			unsigned port_over_current_change:1;
1132 			unsigned port_l1_change:1;
1133 			unsigned reserved:25;
1134 		} b;
1135 	} flags;
1136 
1137 	struct list_head non_periodic_sched_inactive;
1138 	struct list_head non_periodic_sched_waiting;
1139 	struct list_head non_periodic_sched_active;
1140 	struct list_head *non_periodic_qh_ptr;
1141 	struct list_head periodic_sched_inactive;
1142 	struct list_head periodic_sched_ready;
1143 	struct list_head periodic_sched_assigned;
1144 	struct list_head periodic_sched_queued;
1145 	struct list_head split_order;
1146 	u16 periodic_usecs;
1147 	DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US);
1148 	u16 periodic_qh_count;
1149 	bool new_connection;
1150 
1151 	u16 last_frame_num;
1152 
1153 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1154 #define FRAME_NUM_ARRAY_SIZE 1000
1155 	u16 *frame_num_array;
1156 	u16 *last_frame_num_array;
1157 	int frame_num_idx;
1158 	int dumped_frame_num_array;
1159 #endif
1160 
1161 	struct list_head free_hc_list;
1162 	int periodic_channels;
1163 	int non_periodic_channels;
1164 	int available_host_channels;
1165 	struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1166 	u8 *status_buf;
1167 	dma_addr_t status_buf_dma;
1168 #define DWC2_HCD_STATUS_BUF_SIZE 64
1169 
1170 	struct delayed_work start_work;
1171 	struct delayed_work reset_work;
1172 	struct work_struct phy_reset_work;
1173 	u8 otg_port;
1174 	u32 *frame_list;
1175 	dma_addr_t frame_list_dma;
1176 	u32 frame_list_sz;
1177 	struct kmem_cache *desc_gen_cache;
1178 	struct kmem_cache *desc_hsisoc_cache;
1179 	struct kmem_cache *unaligned_cache;
1180 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1181 
1182 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1183 
1184 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1185 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1186 	/* Gadget structures */
1187 	struct usb_gadget_driver *driver;
1188 	int fifo_mem;
1189 	unsigned int dedicated_fifos:1;
1190 	unsigned char num_of_eps;
1191 	u32 fifo_map;
1192 
1193 	struct usb_request *ep0_reply;
1194 	struct usb_request *ctrl_req;
1195 	void *ep0_buff;
1196 	void *ctrl_buff;
1197 	enum dwc2_ep0_state ep0_state;
1198 	unsigned delayed_status : 1;
1199 	u8 test_mode;
1200 
1201 	dma_addr_t setup_desc_dma[2];
1202 	struct dwc2_dma_desc *setup_desc[2];
1203 	dma_addr_t ctrl_in_desc_dma;
1204 	struct dwc2_dma_desc *ctrl_in_desc;
1205 	dma_addr_t ctrl_out_desc_dma;
1206 	struct dwc2_dma_desc *ctrl_out_desc;
1207 
1208 	struct usb_gadget gadget;
1209 	unsigned int enabled:1;
1210 	unsigned int connected:1;
1211 	unsigned int remote_wakeup_allowed:1;
1212 	struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1213 	struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1214 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1215 };
1216 
1217 /* Normal architectures just use readl/write */
dwc2_readl(struct dwc2_hsotg * hsotg,u32 offset)1218 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1219 {
1220 	u32 val;
1221 
1222 	val = readl(hsotg->regs + offset);
1223 	if (hsotg->needs_byte_swap)
1224 		return swab32(val);
1225 	else
1226 		return val;
1227 }
1228 
dwc2_writel(struct dwc2_hsotg * hsotg,u32 value,u32 offset)1229 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1230 {
1231 	if (hsotg->needs_byte_swap)
1232 		writel(swab32(value), hsotg->regs + offset);
1233 	else
1234 		writel(value, hsotg->regs + offset);
1235 
1236 #ifdef DWC2_LOG_WRITES
1237 	pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1238 #endif
1239 }
1240 
dwc2_readl_rep(struct dwc2_hsotg * hsotg,u32 offset,void * buffer,unsigned int count)1241 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1242 				  void *buffer, unsigned int count)
1243 {
1244 	if (count) {
1245 		u32 *buf = buffer;
1246 
1247 		do {
1248 			u32 x = dwc2_readl(hsotg, offset);
1249 			*buf++ = x;
1250 		} while (--count);
1251 	}
1252 }
1253 
dwc2_writel_rep(struct dwc2_hsotg * hsotg,u32 offset,const void * buffer,unsigned int count)1254 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1255 				   const void *buffer, unsigned int count)
1256 {
1257 	if (count) {
1258 		const u32 *buf = buffer;
1259 
1260 		do {
1261 			dwc2_writel(hsotg, *buf++, offset);
1262 		} while (--count);
1263 	}
1264 }
1265 
1266 /* Reasons for halting a host channel */
1267 enum dwc2_halt_status {
1268 	DWC2_HC_XFER_NO_HALT_STATUS,
1269 	DWC2_HC_XFER_COMPLETE,
1270 	DWC2_HC_XFER_URB_COMPLETE,
1271 	DWC2_HC_XFER_ACK,
1272 	DWC2_HC_XFER_NAK,
1273 	DWC2_HC_XFER_NYET,
1274 	DWC2_HC_XFER_STALL,
1275 	DWC2_HC_XFER_XACT_ERR,
1276 	DWC2_HC_XFER_FRAME_OVERRUN,
1277 	DWC2_HC_XFER_BABBLE_ERR,
1278 	DWC2_HC_XFER_DATA_TOGGLE_ERR,
1279 	DWC2_HC_XFER_AHB_ERR,
1280 	DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1281 	DWC2_HC_XFER_URB_DEQUEUE,
1282 };
1283 
1284 /* Core version information */
dwc2_is_iot(struct dwc2_hsotg * hsotg)1285 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1286 {
1287 	return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1288 }
1289 
dwc2_is_fs_iot(struct dwc2_hsotg * hsotg)1290 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1291 {
1292 	return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1293 }
1294 
dwc2_is_hs_iot(struct dwc2_hsotg * hsotg)1295 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1296 {
1297 	return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1298 }
1299 
1300 /*
1301  * The following functions support initialization of the core driver component
1302  * and the DWC_otg controller
1303  */
1304 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1305 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1306 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
1307 				 bool restore);
1308 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1309 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1310 		int reset, int is_host);
1311 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1312 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1313 
1314 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1315 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1316 
1317 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1318 
1319 int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1320 
1321 /*
1322  * Common core Functions.
1323  * The following functions support managing the DWC_otg controller in either
1324  * device or host mode.
1325  */
1326 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1327 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1328 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1329 
1330 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1331 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1332 
1333 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1334 			     int is_host);
1335 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1336 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1337 
1338 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1339 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup);
1340 
1341 /* This function should be called on every hardware interrupt. */
1342 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1343 
1344 /* The device ID match table */
1345 extern const struct of_device_id dwc2_of_match_table[];
1346 extern const struct acpi_device_id dwc2_acpi_match[];
1347 extern const struct pci_device_id dwc2_pci_ids[];
1348 
1349 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1350 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1351 
1352 /* Common polling functions */
1353 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1354 			    u32 timeout);
1355 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1356 			      u32 timeout);
1357 /* Parameters */
1358 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1359 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1360 
1361 /*
1362  * The following functions check the controller's OTG operation mode
1363  * capability (GHWCFG2.OTG_MODE).
1364  *
1365  * These functions can be used before the internal hsotg->hw_params
1366  * are read in and cached so they always read directly from the
1367  * GHWCFG2 register.
1368  */
1369 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1370 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1371 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1372 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1373 
1374 /*
1375  * Returns the mode of operation, host or device
1376  */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1377 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1378 {
1379 	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1380 }
1381 
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1382 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1383 {
1384 	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1385 }
1386 
1387 int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1388 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1389 void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1390 void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1391 
1392 /*
1393  * Dump core registers and SPRAM
1394  */
1395 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1396 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1397 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1398 
1399 /* Gadget defines */
1400 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1401 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1402 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1403 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1404 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1405 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1406 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1407 				       bool reset);
1408 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1409 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1410 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1411 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1412 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1413 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1414 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1415 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1416 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1417 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1418 				 int rem_wakeup, int reset);
1419 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1420 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1421 					bool restore);
1422 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
1423 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1424 				   int rem_wakeup);
1425 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1426 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1427 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1428 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1429 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1430 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
1431 { hsotg->fifo_map = 0; }
1432 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1433 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1434 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1435 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1436 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1437 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1438 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg)1439 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1440 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1441 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1442 						     bool reset) {}
dwc2_hsotg_core_disconnect(struct dwc2_hsotg * hsotg)1443 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1444 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1445 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1446 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1447 					   int testmode)
1448 { return 0; }
1449 #define dwc2_is_device_connected(hsotg) (0)
1450 #define dwc2_is_device_enabled(hsotg) (0)
dwc2_backup_device_registers(struct dwc2_hsotg * hsotg)1451 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1452 { return 0; }
dwc2_restore_device_registers(struct dwc2_hsotg * hsotg,int remote_wakeup)1453 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1454 						int remote_wakeup)
1455 { return 0; }
dwc2_gadget_enter_hibernation(struct dwc2_hsotg * hsotg)1456 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1457 { return 0; }
dwc2_gadget_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1458 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1459 					       int rem_wakeup, int reset)
1460 { return 0; }
dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg * hsotg)1461 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1462 { return 0; }
dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg * hsotg,bool restore)1463 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1464 						      bool restore)
1465 { return 0; }
dwc2_gadget_enter_clock_gating(struct dwc2_hsotg * hsotg)1466 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1467 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1468 						 int rem_wakeup) {}
dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg * hsotg)1469 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1470 { return 0; }
dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg * hsotg)1471 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1472 { return 0; }
dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg * hsotg)1473 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1474 { return 0; }
dwc2_gadget_init_lpm(struct dwc2_hsotg * hsotg)1475 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_program_ref_clk(struct dwc2_hsotg * hsotg)1476 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
dwc2_clear_fifo_map(struct dwc2_hsotg * hsotg)1477 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
1478 #endif
1479 
1480 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1481 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1482 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1483 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1484 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1485 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1486 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1487 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
1488 int dwc2_port_resume(struct dwc2_hsotg *hsotg);
1489 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1490 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1491 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1492 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1493 			       int rem_wakeup, int reset);
1494 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1495 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1496 				      int rem_wakeup, bool restore);
1497 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
1498 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
1499 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1500 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1501 { schedule_work(&hsotg->phy_reset_work); }
1502 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1503 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1504 { return 0; }
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)1505 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1506 						   int us)
1507 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1508 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1509 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1510 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1511 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_core_init(struct dwc2_hsotg * hsotg,bool initial_setup)1512 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1513 { return 0; }
dwc2_port_suspend(struct dwc2_hsotg * hsotg,u16 windex)1514 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1515 { return 0; }
dwc2_port_resume(struct dwc2_hsotg * hsotg)1516 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
1517 { return 0; }
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1518 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1519 { return 0; }
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)1520 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1521 { return 0; }
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)1522 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1523 { return 0; }
dwc2_host_enter_hibernation(struct dwc2_hsotg * hsotg)1524 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1525 { return 0; }
dwc2_host_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1526 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1527 					     int rem_wakeup, int reset)
1528 { return 0; }
dwc2_host_enter_partial_power_down(struct dwc2_hsotg * hsotg)1529 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1530 { return 0; }
dwc2_host_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)1531 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1532 						    int rem_wakeup, bool restore)
1533 { return 0; }
dwc2_host_enter_clock_gating(struct dwc2_hsotg * hsotg)1534 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
dwc2_host_exit_clock_gating(struct dwc2_hsotg * hsotg,int rem_wakeup)1535 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
1536 					       int rem_wakeup) {}
dwc2_host_can_poweroff_phy(struct dwc2_hsotg * dwc2)1537 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1538 { return false; }
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1539 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1540 
1541 #endif
1542 
1543 #endif /* __DWC2_CORE_H__ */
1544