1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8998_MASK \ 25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 26 27 #define VIG_SDM845_MASK \ 28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 29 30 #define VIG_SDM845_MASK_SDMA \ 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 33 #define VIG_SC7180_MASK \ 34 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 35 36 #define VIG_SM6125_MASK \ 37 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 38 39 #define VIG_SC7180_MASK_SDMA \ 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 41 42 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 43 44 #define DMA_MSM8998_MASK \ 45 (BIT(DPU_SSPP_QOS) |\ 46 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 47 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 48 49 #define VIG_SC7280_MASK \ 50 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 51 52 #define VIG_SC7280_MASK_SDMA \ 53 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 54 55 #define DMA_SDM845_MASK \ 56 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 57 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 58 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 59 60 #define DMA_CURSOR_SDM845_MASK \ 61 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 62 63 #define DMA_SDM845_MASK_SDMA \ 64 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 65 66 #define DMA_CURSOR_SDM845_MASK_SDMA \ 67 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 68 69 #define DMA_CURSOR_MSM8998_MASK \ 70 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 71 72 #define MIXER_MSM8998_MASK \ 73 (BIT(DPU_MIXER_SOURCESPLIT)) 74 75 #define MIXER_SDM845_MASK \ 76 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 77 78 #define MIXER_QCM2290_MASK \ 79 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 80 81 #define PINGPONG_SDM845_MASK \ 82 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC)) 83 84 #define PINGPONG_SDM845_TE2_MASK \ 85 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 86 87 #define PINGPONG_SM8150_MASK \ 88 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 89 90 #define CTL_SC7280_MASK \ 91 (BIT(DPU_CTL_ACTIVE_CFG) | \ 92 BIT(DPU_CTL_FETCH_ACTIVE) | \ 93 BIT(DPU_CTL_VM_CFG) | \ 94 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 95 96 #define CTL_SM8550_MASK \ 97 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 98 99 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 100 101 #define INTF_SC7180_MASK \ 102 (BIT(DPU_INTF_INPUT_CTRL) | \ 103 BIT(DPU_INTF_TE) | \ 104 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 105 BIT(DPU_DATA_HCTL_EN)) 106 107 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 108 109 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 110 BIT(DPU_WB_UBWC) | \ 111 BIT(DPU_WB_YUV_CONFIG) | \ 112 BIT(DPU_WB_PIPE_ALPHA) | \ 113 BIT(DPU_WB_XY_ROI_OFFSET) | \ 114 BIT(DPU_WB_QOS) | \ 115 BIT(DPU_WB_QOS_8LVL) | \ 116 BIT(DPU_WB_CDP) | \ 117 BIT(DPU_WB_INPUT_CTRL)) 118 119 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 120 #define DEFAULT_DPU_LINE_WIDTH 2048 121 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 122 123 #define MAX_HORZ_DECIMATION 4 124 #define MAX_VERT_DECIMATION 4 125 126 #define MAX_UPSCALE_RATIO 20 127 #define MAX_DOWNSCALE_RATIO 4 128 #define SSPP_UNITY_SCALE 1 129 130 #define STRCAT(X, Y) (X Y) 131 132 static const uint32_t plane_formats[] = { 133 DRM_FORMAT_ARGB8888, 134 DRM_FORMAT_ABGR8888, 135 DRM_FORMAT_RGBA8888, 136 DRM_FORMAT_BGRA8888, 137 DRM_FORMAT_XRGB8888, 138 DRM_FORMAT_RGBX8888, 139 DRM_FORMAT_BGRX8888, 140 DRM_FORMAT_XBGR8888, 141 DRM_FORMAT_ARGB2101010, 142 DRM_FORMAT_XRGB2101010, 143 DRM_FORMAT_RGB888, 144 DRM_FORMAT_BGR888, 145 DRM_FORMAT_RGB565, 146 DRM_FORMAT_BGR565, 147 DRM_FORMAT_ARGB1555, 148 DRM_FORMAT_ABGR1555, 149 DRM_FORMAT_RGBA5551, 150 DRM_FORMAT_BGRA5551, 151 DRM_FORMAT_XRGB1555, 152 DRM_FORMAT_XBGR1555, 153 DRM_FORMAT_RGBX5551, 154 DRM_FORMAT_BGRX5551, 155 DRM_FORMAT_ARGB4444, 156 DRM_FORMAT_ABGR4444, 157 DRM_FORMAT_RGBA4444, 158 DRM_FORMAT_BGRA4444, 159 DRM_FORMAT_XRGB4444, 160 DRM_FORMAT_XBGR4444, 161 DRM_FORMAT_RGBX4444, 162 DRM_FORMAT_BGRX4444, 163 }; 164 165 static const uint32_t plane_formats_yuv[] = { 166 DRM_FORMAT_ARGB8888, 167 DRM_FORMAT_ABGR8888, 168 DRM_FORMAT_RGBA8888, 169 DRM_FORMAT_BGRX8888, 170 DRM_FORMAT_BGRA8888, 171 DRM_FORMAT_ARGB2101010, 172 DRM_FORMAT_XRGB2101010, 173 DRM_FORMAT_XRGB8888, 174 DRM_FORMAT_XBGR8888, 175 DRM_FORMAT_RGBX8888, 176 DRM_FORMAT_RGB888, 177 DRM_FORMAT_BGR888, 178 DRM_FORMAT_RGB565, 179 DRM_FORMAT_BGR565, 180 DRM_FORMAT_ARGB1555, 181 DRM_FORMAT_ABGR1555, 182 DRM_FORMAT_RGBA5551, 183 DRM_FORMAT_BGRA5551, 184 DRM_FORMAT_XRGB1555, 185 DRM_FORMAT_XBGR1555, 186 DRM_FORMAT_RGBX5551, 187 DRM_FORMAT_BGRX5551, 188 DRM_FORMAT_ARGB4444, 189 DRM_FORMAT_ABGR4444, 190 DRM_FORMAT_RGBA4444, 191 DRM_FORMAT_BGRA4444, 192 DRM_FORMAT_XRGB4444, 193 DRM_FORMAT_XBGR4444, 194 DRM_FORMAT_RGBX4444, 195 DRM_FORMAT_BGRX4444, 196 197 DRM_FORMAT_P010, 198 DRM_FORMAT_NV12, 199 DRM_FORMAT_NV21, 200 DRM_FORMAT_NV16, 201 DRM_FORMAT_NV61, 202 DRM_FORMAT_VYUY, 203 DRM_FORMAT_UYVY, 204 DRM_FORMAT_YUYV, 205 DRM_FORMAT_YVYU, 206 DRM_FORMAT_YUV420, 207 DRM_FORMAT_YVU420, 208 }; 209 210 static const u32 rotation_v2_formats[] = { 211 DRM_FORMAT_NV12, 212 /* TODO add formats after validation */ 213 }; 214 215 static const uint32_t wb2_formats[] = { 216 DRM_FORMAT_RGB565, 217 DRM_FORMAT_BGR565, 218 DRM_FORMAT_RGB888, 219 DRM_FORMAT_ARGB8888, 220 DRM_FORMAT_RGBA8888, 221 DRM_FORMAT_ABGR8888, 222 DRM_FORMAT_XRGB8888, 223 DRM_FORMAT_RGBX8888, 224 DRM_FORMAT_XBGR8888, 225 DRM_FORMAT_ARGB1555, 226 DRM_FORMAT_RGBA5551, 227 DRM_FORMAT_XRGB1555, 228 DRM_FORMAT_RGBX5551, 229 DRM_FORMAT_ARGB4444, 230 DRM_FORMAT_RGBA4444, 231 DRM_FORMAT_RGBX4444, 232 DRM_FORMAT_XRGB4444, 233 DRM_FORMAT_BGR565, 234 DRM_FORMAT_BGR888, 235 DRM_FORMAT_ABGR8888, 236 DRM_FORMAT_BGRA8888, 237 DRM_FORMAT_BGRX8888, 238 DRM_FORMAT_XBGR8888, 239 DRM_FORMAT_ABGR1555, 240 DRM_FORMAT_BGRA5551, 241 DRM_FORMAT_XBGR1555, 242 DRM_FORMAT_BGRX5551, 243 DRM_FORMAT_ABGR4444, 244 DRM_FORMAT_BGRA4444, 245 DRM_FORMAT_BGRX4444, 246 DRM_FORMAT_XBGR4444, 247 }; 248 249 /************************************************************* 250 * SSPP sub blocks config 251 *************************************************************/ 252 253 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) 254 255 /* SSPP common configuration */ 256 #define _VIG_SBLK(sdma_pri, qseed_ver, scaler_ver) \ 257 { \ 258 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 259 .maxupscale = MAX_UPSCALE_RATIO, \ 260 .smart_dma_priority = sdma_pri, \ 261 .scaler_blk = {.name = "scaler", \ 262 .id = qseed_ver, \ 263 .version = scaler_ver, \ 264 .base = 0xa00, .len = 0xa0,}, \ 265 .csc_blk = {.name = "csc", \ 266 .id = DPU_SSPP_CSC_10BIT, \ 267 .base = 0x1a00, .len = 0x100,}, \ 268 .format_list = plane_formats_yuv, \ 269 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 270 .virt_format_list = plane_formats, \ 271 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 272 .rotation_cfg = NULL, \ 273 } 274 275 #define _VIG_SBLK_ROT(sdma_pri, qseed_ver, scaler_ver, rot_cfg) \ 276 { \ 277 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 278 .maxupscale = MAX_UPSCALE_RATIO, \ 279 .smart_dma_priority = sdma_pri, \ 280 .scaler_blk = {.name = "scaler", \ 281 .id = qseed_ver, \ 282 .version = scaler_ver, \ 283 .base = 0xa00, .len = 0xa0,}, \ 284 .csc_blk = {.name = "csc", \ 285 .id = DPU_SSPP_CSC_10BIT, \ 286 .base = 0x1a00, .len = 0x100,}, \ 287 .format_list = plane_formats_yuv, \ 288 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 289 .virt_format_list = plane_formats, \ 290 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 291 .rotation_cfg = rot_cfg, \ 292 } 293 294 #define _DMA_SBLK(sdma_pri) \ 295 { \ 296 .maxdwnscale = SSPP_UNITY_SCALE, \ 297 .maxupscale = SSPP_UNITY_SCALE, \ 298 .smart_dma_priority = sdma_pri, \ 299 .format_list = plane_formats, \ 300 .num_formats = ARRAY_SIZE(plane_formats), \ 301 .virt_format_list = plane_formats, \ 302 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 303 } 304 305 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 306 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, 307 SSPP_SCALER_VER(1, 2)); 308 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 309 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, 310 SSPP_SCALER_VER(1, 2)); 311 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 312 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, 313 SSPP_SCALER_VER(1, 2)); 314 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 315 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3, 316 SSPP_SCALER_VER(1, 2)); 317 318 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 319 .rot_maxheight = 1088, 320 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 321 .rot_format_list = rotation_v2_formats, 322 }; 323 324 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 325 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3, 326 SSPP_SCALER_VER(1, 3)); 327 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 328 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3, 329 SSPP_SCALER_VER(1, 3)); 330 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 331 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3, 332 SSPP_SCALER_VER(1, 3)); 333 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 334 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3, 335 SSPP_SCALER_VER(1, 3)); 336 337 static const struct dpu_sspp_sub_blks sm8150_vig_sblk_0 = 338 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3, 339 SSPP_SCALER_VER(1, 4)); 340 static const struct dpu_sspp_sub_blks sm8150_vig_sblk_1 = 341 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3, 342 SSPP_SCALER_VER(1, 4)); 343 static const struct dpu_sspp_sub_blks sm8150_vig_sblk_2 = 344 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3, 345 SSPP_SCALER_VER(1, 4)); 346 static const struct dpu_sspp_sub_blks sm8150_vig_sblk_3 = 347 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3, 348 SSPP_SCALER_VER(1, 4)); 349 350 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); 351 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); 352 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); 353 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); 354 355 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 356 _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4, 357 SSPP_SCALER_VER(3, 0)); 358 359 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 360 _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, 361 SSPP_SCALER_VER(3, 0), 362 &dpu_rot_sc7280_cfg_v2); 363 364 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = 365 _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4, 366 SSPP_SCALER_VER(3, 0)); 367 368 static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = 369 _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE, 370 SSPP_SCALER_VER(2, 4)); 371 372 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 373 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4, 374 SSPP_SCALER_VER(3, 0)); 375 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 376 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4, 377 SSPP_SCALER_VER(3, 0)); 378 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 379 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, 380 SSPP_SCALER_VER(3, 0)); 381 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 382 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, 383 SSPP_SCALER_VER(3, 0)); 384 385 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = 386 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4, 387 SSPP_SCALER_VER(3, 1)); 388 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = 389 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4, 390 SSPP_SCALER_VER(3, 1)); 391 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = 392 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, 393 SSPP_SCALER_VER(3, 1)); 394 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = 395 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, 396 SSPP_SCALER_VER(3, 1)); 397 398 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = 399 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4, 400 SSPP_SCALER_VER(3, 2)); 401 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = 402 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4, 403 SSPP_SCALER_VER(3, 2)); 404 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = 405 _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4, 406 SSPP_SCALER_VER(3, 2)); 407 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = 408 _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4, 409 SSPP_SCALER_VER(3, 2)); 410 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); 411 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); 412 413 #define _VIG_SBLK_NOSCALE(sdma_pri) \ 414 { \ 415 .maxdwnscale = SSPP_UNITY_SCALE, \ 416 .maxupscale = SSPP_UNITY_SCALE, \ 417 .smart_dma_priority = sdma_pri, \ 418 .format_list = plane_formats_yuv, \ 419 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 420 .virt_format_list = plane_formats, \ 421 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 422 } 423 424 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); 425 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); 426 427 /************************************************************* 428 * MIXER sub blocks config 429 *************************************************************/ 430 431 /* MSM8998 */ 432 433 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 434 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 435 .maxblendstages = 7, /* excluding base layer */ 436 .blendstage_base = { /* offsets relative to mixer base */ 437 0x20, 0x50, 0x80, 0xb0, 0x230, 438 0x260, 0x290 439 }, 440 }; 441 442 /* SDM845 */ 443 444 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 445 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 446 .maxblendstages = 11, /* excluding base layer */ 447 .blendstage_base = { /* offsets relative to mixer base */ 448 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 449 0xb0, 0xc8, 0xe0, 0xf8, 0x110 450 }, 451 }; 452 453 /* SC7180 */ 454 455 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 456 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 457 .maxblendstages = 7, /* excluding base layer */ 458 .blendstage_base = { /* offsets relative to mixer base */ 459 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 460 }, 461 }; 462 463 /* QCM2290 */ 464 465 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 466 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 467 .maxblendstages = 4, /* excluding base layer */ 468 .blendstage_base = { /* offsets relative to mixer base */ 469 0x20, 0x38, 0x50, 0x68 470 }, 471 }; 472 473 /************************************************************* 474 * DSPP sub blocks config 475 *************************************************************/ 476 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 477 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 478 .len = 0x90, .version = 0x10007}, 479 }; 480 481 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 482 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 483 .len = 0x90, .version = 0x40000}, 484 }; 485 486 /************************************************************* 487 * PINGPONG sub blocks config 488 *************************************************************/ 489 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 490 .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 491 .version = 0x1}, 492 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 493 .len = 0x20, .version = 0x10000}, 494 }; 495 496 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 497 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 498 .len = 0x20, .version = 0x10000}, 499 }; 500 501 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 502 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, 503 .len = 0x20, .version = 0x20000}, 504 }; 505 506 /************************************************************* 507 * DSC sub blocks config 508 *************************************************************/ 509 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 510 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 511 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 512 }; 513 514 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 515 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 516 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 517 }; 518 519 /************************************************************* 520 * VBIF sub blocks config 521 *************************************************************/ 522 /* VBIF QOS remap */ 523 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 524 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 525 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 526 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 527 528 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 529 { 530 .pps = 1920 * 1080 * 30, 531 .ot_limit = 2, 532 }, 533 { 534 .pps = 1920 * 1080 * 60, 535 .ot_limit = 4, 536 }, 537 { 538 .pps = 3840 * 2160 * 30, 539 .ot_limit = 16, 540 }, 541 }; 542 543 static const struct dpu_vbif_cfg msm8998_vbif[] = { 544 { 545 .name = "vbif_rt", .id = VBIF_RT, 546 .base = 0, .len = 0x1040, 547 .default_ot_rd_limit = 32, 548 .default_ot_wr_limit = 32, 549 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 550 .xin_halt_timeout = 0x4000, 551 .qos_rp_remap_size = 0x20, 552 .dynamic_ot_rd_tbl = { 553 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 554 .cfg = msm8998_ot_rdwr_cfg, 555 }, 556 .dynamic_ot_wr_tbl = { 557 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 558 .cfg = msm8998_ot_rdwr_cfg, 559 }, 560 .qos_rt_tbl = { 561 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 562 .priority_lvl = msm8998_rt_pri_lvl, 563 }, 564 .qos_nrt_tbl = { 565 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 566 .priority_lvl = msm8998_nrt_pri_lvl, 567 }, 568 .memtype_count = 14, 569 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 570 }, 571 }; 572 573 static const struct dpu_vbif_cfg sdm845_vbif[] = { 574 { 575 .name = "vbif_rt", .id = VBIF_RT, 576 .base = 0, .len = 0x1040, 577 .features = BIT(DPU_VBIF_QOS_REMAP), 578 .xin_halt_timeout = 0x4000, 579 .qos_rp_remap_size = 0x40, 580 .qos_rt_tbl = { 581 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 582 .priority_lvl = sdm845_rt_pri_lvl, 583 }, 584 .qos_nrt_tbl = { 585 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 586 .priority_lvl = sdm845_nrt_pri_lvl, 587 }, 588 .memtype_count = 14, 589 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 590 }, 591 }; 592 593 static const struct dpu_vbif_cfg sm8550_vbif[] = { 594 { 595 .name = "vbif_rt", .id = VBIF_RT, 596 .base = 0, .len = 0x1040, 597 .features = BIT(DPU_VBIF_QOS_REMAP), 598 .xin_halt_timeout = 0x4000, 599 .qos_rp_remap_size = 0x40, 600 .qos_rt_tbl = { 601 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 602 .priority_lvl = sdm845_rt_pri_lvl, 603 }, 604 .qos_nrt_tbl = { 605 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 606 .priority_lvl = sdm845_nrt_pri_lvl, 607 }, 608 .memtype_count = 16, 609 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 610 }, 611 }; 612 613 /************************************************************* 614 * PERF data config 615 *************************************************************/ 616 617 /* SSPP QOS LUTs */ 618 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 619 {.fl = 4, .lut = 0x1b}, 620 {.fl = 5, .lut = 0x5b}, 621 {.fl = 6, .lut = 0x15b}, 622 {.fl = 7, .lut = 0x55b}, 623 {.fl = 8, .lut = 0x155b}, 624 {.fl = 9, .lut = 0x555b}, 625 {.fl = 10, .lut = 0x1555b}, 626 {.fl = 11, .lut = 0x5555b}, 627 {.fl = 12, .lut = 0x15555b}, 628 {.fl = 0, .lut = 0x55555b} 629 }; 630 631 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 632 {.fl = 4, .lut = 0x357}, 633 {.fl = 5, .lut = 0x3357}, 634 {.fl = 6, .lut = 0x23357}, 635 {.fl = 7, .lut = 0x223357}, 636 {.fl = 8, .lut = 0x2223357}, 637 {.fl = 9, .lut = 0x22223357}, 638 {.fl = 10, .lut = 0x222223357}, 639 {.fl = 11, .lut = 0x2222223357}, 640 {.fl = 12, .lut = 0x22222223357}, 641 {.fl = 13, .lut = 0x222222223357}, 642 {.fl = 14, .lut = 0x1222222223357}, 643 {.fl = 0, .lut = 0x11222222223357} 644 }; 645 646 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 647 {.fl = 10, .lut = 0x1aaff}, 648 {.fl = 11, .lut = 0x5aaff}, 649 {.fl = 12, .lut = 0x15aaff}, 650 {.fl = 0, .lut = 0x55aaff}, 651 }; 652 653 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 654 {.fl = 0, .lut = 0x0011222222335777}, 655 }; 656 657 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 658 {.fl = 0, .lut = 0x0011223445566777 }, 659 }; 660 661 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 662 {.fl = 0, .lut = 0x0011222222223357 }, 663 }; 664 665 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 666 {.fl = 4, .lut = 0x0000000000000357 }, 667 }; 668 669 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 670 {.fl = 0, .lut = 0x0011222222335777}, 671 }; 672 673 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 674 {.fl = 10, .lut = 0x344556677}, 675 {.fl = 11, .lut = 0x3344556677}, 676 {.fl = 12, .lut = 0x23344556677}, 677 {.fl = 13, .lut = 0x223344556677}, 678 {.fl = 14, .lut = 0x1223344556677}, 679 {.fl = 0, .lut = 0x112233344556677}, 680 }; 681 682 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 683 {.fl = 0, .lut = 0x0011223344556677}, 684 }; 685 686 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 687 {.fl = 10, .lut = 0x0000000344556677}, 688 }; 689 690 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 691 {.fl = 0, .lut = 0x0}, 692 }; 693 694 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 695 {.fl = 0, .lut = 0x0}, 696 }; 697 698 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 699 {.fl = 0, .lut = 0x0}, 700 }; 701 702 /************************************************************* 703 * Hardware catalog 704 *************************************************************/ 705 706 #include "catalog/dpu_3_0_msm8998.h" 707 708 #include "catalog/dpu_4_0_sdm845.h" 709 710 #include "catalog/dpu_5_0_sm8150.h" 711 #include "catalog/dpu_5_1_sc8180x.h" 712 #include "catalog/dpu_5_4_sm6125.h" 713 714 #include "catalog/dpu_6_0_sm8250.h" 715 #include "catalog/dpu_6_2_sc7180.h" 716 #include "catalog/dpu_6_3_sm6115.h" 717 #include "catalog/dpu_6_4_sm6350.h" 718 #include "catalog/dpu_6_5_qcm2290.h" 719 #include "catalog/dpu_6_9_sm6375.h" 720 721 #include "catalog/dpu_7_0_sm8350.h" 722 #include "catalog/dpu_7_2_sc7280.h" 723 724 #include "catalog/dpu_8_0_sc8280xp.h" 725 #include "catalog/dpu_8_1_sm8450.h" 726 727 #include "catalog/dpu_9_0_sm8550.h" 728