1 #ifndef DSI_PHY_28NM_XML
2 #define DSI_PHY_28NM_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
30 Copyright (C) 2013-2022 by the following authors:
31 - Rob Clark <robdclark@gmail.com> (robclark)
32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
34 Permission is hereby granted, free of charge, to any person obtaining
35 a copy of this software and associated documentation files (the
36 "Software"), to deal in the Software without restriction, including
37 without limitation the rights to use, copy, modify, merge, publish,
38 distribute, sublicense, and/or sell copies of the Software, and to
39 permit persons to whom the Software is furnished to do so, subject to
40 the following conditions:
41
42 The above copyright notice and this permission notice (including the
43 next paragraph) shall be included in all copies or substantial
44 portions of the Software.
45
46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53 */
54
55
REG_DSI_28nm_PHY_LN(uint32_t i0)56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
57
REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0)58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
59
REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0)60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
61
REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0)62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
63
REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0)64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
65
REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0)66 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
67
REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0)68 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
69
REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0)70 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
71
REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0)72 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
73
REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0)74 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
75
76 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
77
78 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
79
80 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
81
82 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
83
84 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
85
86 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
87
88 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
89
90 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
91
92 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
93
94 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
95 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
96 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)97 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
98 {
99 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
100 }
101
102 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
103 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
104 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)105 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
106 {
107 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
108 }
109
110 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
111 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
112 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)113 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
114 {
115 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
116 }
117
118 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
119 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
120
121 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
122 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
123 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)124 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
125 {
126 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
127 }
128
129 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
130 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
131 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)132 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
133 {
134 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
135 }
136
137 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
138 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
139 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)140 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
141 {
142 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
143 }
144
145 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
146 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
147 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)148 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
149 {
150 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
151 }
152
153 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
154 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
155 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)156 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
157 {
158 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
159 }
160
161 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
162 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
163 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)164 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
165 {
166 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
167 }
168 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
169 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)170 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
171 {
172 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
173 }
174
175 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
176 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
177 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)178 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
179 {
180 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
181 }
182
183 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
184 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
185 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)186 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
187 {
188 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
189 }
190
191 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170
192
193 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174
194
195 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178
196
197 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
198
199 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180
200
201 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
202
203 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
204
205 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
206
207 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
208
209 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
210
211 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
212
213 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
214
215 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
216
217 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
218 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
219
220 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
221
222 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
223
224 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
225
226 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
227
228 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
229
230 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
231
232 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
233
234 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
235
236 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
237 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
238
239 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
240
241 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
242
243 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
244
245 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
246 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
247
248 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
249
250 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
251
252 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
253
254 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
255 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
256 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
257 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
258 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
259
260 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
261
262 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
263
264 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
265
266 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
267
268 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
269
270 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
271 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
272 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)273 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
274 {
275 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
276 }
277 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
278
279 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
280 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
281 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)282 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
283 {
284 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
285 }
286 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
287 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)288 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
289 {
290 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
291 }
292
293 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
294 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
295 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)296 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
297 {
298 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
299 }
300
301 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
302 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
303 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)304 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
305 {
306 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
307 }
308
309 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
310
311 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
312
313 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
314
315 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
316
317 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
318
319 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
320
321 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
322
323 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
324
325 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
326 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
327
328 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
329
330 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
331
332 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
333
334 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
335
336 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
337
338 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
339
340 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
341
342 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
343
344 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
345
346 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
347
348 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
349
350 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
351
352 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
353
354 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
355
356 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
357
358 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
359
360 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
361
362 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
363
364 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
365
366 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
367
368 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
369
370 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
371 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
372
373 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
374
375 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
376
377 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
378
379 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
380
381 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
382
383
384 #endif /* DSI_PHY_28NM_XML */
385