1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #ifndef _DRM_HDCP_H_ 10 #define _DRM_HDCP_H_ 11 12 #include <linux/types.h> 13 14 /* Period of hdcp checks (to ensure we're still authenticated) */ 15 #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) 16 #define DRM_HDCP2_CHECK_PERIOD_MS 500 17 18 /* Shared lengths/masks between HDMI/DVI/DisplayPort */ 19 #define DRM_HDCP_AN_LEN 8 20 #define DRM_HDCP_BSTATUS_LEN 2 21 #define DRM_HDCP_KSV_LEN 5 22 #define DRM_HDCP_RI_LEN 2 23 #define DRM_HDCP_V_PRIME_PART_LEN 4 24 #define DRM_HDCP_V_PRIME_NUM_PARTS 5 25 #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) 26 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3)) 27 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7)) 28 29 /* Slave address for the HDCP registers in the receiver */ 30 #define DRM_HDCP_DDC_ADDR 0x3A 31 32 /* Value to use at the end of the SHA-1 bytestream used for repeaters */ 33 #define DRM_HDCP_SHA1_TERMINATOR 0x80 34 35 /* HDCP register offsets for HDMI/DVI devices */ 36 #define DRM_HDCP_DDC_BKSV 0x00 37 #define DRM_HDCP_DDC_RI_PRIME 0x08 38 #define DRM_HDCP_DDC_AKSV 0x10 39 #define DRM_HDCP_DDC_AN 0x18 40 #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4) 41 #define DRM_HDCP_DDC_BCAPS 0x40 42 #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) 43 #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) 44 #define DRM_HDCP_DDC_BSTATUS 0x41 45 #define DRM_HDCP_DDC_KSV_FIFO 0x43 46 47 #define DRM_HDCP_1_4_SRM_ID 0x8 48 #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 49 #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 50 51 /* Protocol message definition for HDCP2.2 specification */ 52 /* 53 * Protected content streams are classified into 2 types: 54 * - Type0: Can be transmitted with HDCP 1.4+ 55 * - Type1: Can be transmitted with HDCP 2.2+ 56 */ 57 #define HDCP_STREAM_TYPE0 0x00 58 #define HDCP_STREAM_TYPE1 0x01 59 60 /* HDCP2.2 Msg IDs */ 61 #define HDCP_2_2_NULL_MSG 1 62 #define HDCP_2_2_AKE_INIT 2 63 #define HDCP_2_2_AKE_SEND_CERT 3 64 #define HDCP_2_2_AKE_NO_STORED_KM 4 65 #define HDCP_2_2_AKE_STORED_KM 5 66 #define HDCP_2_2_AKE_SEND_HPRIME 7 67 #define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 68 #define HDCP_2_2_LC_INIT 9 69 #define HDCP_2_2_LC_SEND_LPRIME 10 70 #define HDCP_2_2_SKE_SEND_EKS 11 71 #define HDCP_2_2_REP_SEND_RECVID_LIST 12 72 #define HDCP_2_2_REP_SEND_ACK 15 73 #define HDCP_2_2_REP_STREAM_MANAGE 16 74 #define HDCP_2_2_REP_STREAM_READY 17 75 76 #define HDCP_2_2_RTX_LEN 8 77 #define HDCP_2_2_RRX_LEN 8 78 79 #define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 80 #define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 81 #define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ 82 HDCP_2_2_K_PUB_RX_EXP_E_LEN) 83 84 #define HDCP_2_2_DCP_LLC_SIG_LEN 384 85 86 #define HDCP_2_2_E_KPUB_KM_LEN 128 87 #define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) 88 #define HDCP_2_2_H_PRIME_LEN 32 89 #define HDCP_2_2_E_KH_KM_LEN 16 90 #define HDCP_2_2_RN_LEN 8 91 #define HDCP_2_2_L_PRIME_LEN 32 92 #define HDCP_2_2_E_DKEY_KS_LEN 16 93 #define HDCP_2_2_RIV_LEN 8 94 #define HDCP_2_2_SEQ_NUM_LEN 3 95 #define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) 96 #define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN 97 #define HDCP_2_2_MAX_DEVICE_COUNT 31 98 #define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ 99 HDCP_2_2_MAX_DEVICE_COUNT) 100 #define HDCP_2_2_MPRIME_LEN 32 101 102 /* Following Macros take a byte at a time for bit(s) masking */ 103 /* 104 * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual 105 * H/W MST streams capacity. 106 * This required to be moved out to platform specific header. 107 */ 108 #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 109 #define HDCP_2_2_TXCAP_MASK_LEN 2 110 #define HDCP_2_2_RXCAPS_LEN 3 111 #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) 112 #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) 113 #define HDCP_2_2_RXINFO_LEN 2 114 115 /* HDCP1.x compliant device in downstream */ 116 #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) 117 118 /* HDCP2.0 Compliant repeater in downstream */ 119 #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) 120 #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) 121 #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) 122 #define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) 123 #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) 124 #define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) 125 126 struct hdcp2_cert_rx { 127 u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; 128 u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; 129 u8 reserved[2]; 130 u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; 131 } __packed; 132 133 struct hdcp2_streamid_type { 134 u8 stream_id; 135 u8 stream_type; 136 } __packed; 137 138 /* 139 * The TxCaps field specified in the HDCP HDMI, DP specs 140 * This field is big endian as specified in the errata. 141 */ 142 struct hdcp2_tx_caps { 143 /* Transmitter must set this to 0x2 */ 144 u8 version; 145 146 /* Reserved for HDCP and DP Spec. Read as Zero */ 147 u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; 148 } __packed; 149 150 /* Main structures for HDCP2.2 protocol communication */ 151 struct hdcp2_ake_init { 152 u8 msg_id; 153 u8 r_tx[HDCP_2_2_RTX_LEN]; 154 struct hdcp2_tx_caps tx_caps; 155 } __packed; 156 157 struct hdcp2_ake_send_cert { 158 u8 msg_id; 159 struct hdcp2_cert_rx cert_rx; 160 u8 r_rx[HDCP_2_2_RRX_LEN]; 161 u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; 162 } __packed; 163 164 struct hdcp2_ake_no_stored_km { 165 u8 msg_id; 166 u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; 167 } __packed; 168 169 struct hdcp2_ake_stored_km { 170 u8 msg_id; 171 u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; 172 } __packed; 173 174 struct hdcp2_ake_send_hprime { 175 u8 msg_id; 176 u8 h_prime[HDCP_2_2_H_PRIME_LEN]; 177 } __packed; 178 179 struct hdcp2_ake_send_pairing_info { 180 u8 msg_id; 181 u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; 182 } __packed; 183 184 struct hdcp2_lc_init { 185 u8 msg_id; 186 u8 r_n[HDCP_2_2_RN_LEN]; 187 } __packed; 188 189 struct hdcp2_lc_send_lprime { 190 u8 msg_id; 191 u8 l_prime[HDCP_2_2_L_PRIME_LEN]; 192 } __packed; 193 194 struct hdcp2_ske_send_eks { 195 u8 msg_id; 196 u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; 197 u8 riv[HDCP_2_2_RIV_LEN]; 198 } __packed; 199 200 struct hdcp2_rep_send_receiverid_list { 201 u8 msg_id; 202 u8 rx_info[HDCP_2_2_RXINFO_LEN]; 203 u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; 204 u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; 205 u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; 206 } __packed; 207 208 struct hdcp2_rep_send_ack { 209 u8 msg_id; 210 u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; 211 } __packed; 212 213 struct hdcp2_rep_stream_manage { 214 u8 msg_id; 215 u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; 216 __be16 k; 217 struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; 218 } __packed; 219 220 struct hdcp2_rep_stream_ready { 221 u8 msg_id; 222 u8 m_prime[HDCP_2_2_MPRIME_LEN]; 223 } __packed; 224 225 /* HDCP2.2 TIMEOUTs in mSec */ 226 #define HDCP_2_2_CERT_TIMEOUT_MS 100 227 #define HDCP_2_2_DP_CERT_READ_TIMEOUT_MS 110 228 #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 229 #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 230 #define HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS 7 231 #define HDCP_2_2_PAIRING_TIMEOUT_MS 200 232 #define HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS 5 233 #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 234 #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 16 235 #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 236 #define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 237 238 /* HDMI HDCP2.2 Register Offsets */ 239 #define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 240 #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 241 #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 242 #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 243 #define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 244 245 #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) 246 #define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 247 #define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF 248 #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 249 250 /* Below macros take a byte at a time and mask the bit(s) */ 251 #define HDCP_2_2_HDMI_RXSTATUS_LEN 2 252 #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) 253 #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) 254 #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) 255 256 /* 257 * Helper functions to convert 24bit big endian hdcp sequence number to 258 * host format and back 259 */ 260 static inline drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])261u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN]) 262 { 263 return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16); 264 } 265 266 static inline drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN],u32 val)267void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val) 268 { 269 seq_num[0] = val >> 16; 270 seq_num[1] = val >> 8; 271 seq_num[2] = val; 272 } 273 274 #define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024) 275 #define DRM_HDCP_1_4_SRM_ID 0x8 276 #define DRM_HDCP_SRM_ID_MASK (0xF << 4) 277 #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 278 #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 279 #define DRM_HDCP_2_SRM_ID 0x9 280 #define DRM_HDCP_2_INDICATOR 0x1 281 #define DRM_HDCP_2_INDICATOR_MASK 0xF 282 #define DRM_HDCP_2_VRL_LENGTH_SIZE 3 283 #define DRM_HDCP_2_DCP_SIG_SIZE 384 284 #define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4 285 #define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6) 286 287 struct hdcp_srm_header { 288 u8 srm_id; 289 u8 reserved; 290 __be16 srm_version; 291 u8 srm_gen_no; 292 } __packed; 293 294 /* Content Type classification for HDCP2.2 vs others */ 295 #define DRM_MODE_HDCP_CONTENT_TYPE0 0 296 #define DRM_MODE_HDCP_CONTENT_TYPE1 1 297 298 #endif 299