1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2019-2022 MediaTek Inc.
4  * Copyright (c) 2022 BayLibre
5  */
6 #ifndef _MTK_DP_REG_H_
7 #define _MTK_DP_REG_H_
8 
9 #define SEC_OFFSET	0x4000
10 
11 #define MTK_DP_HPD_DISCONNECT		BIT(1)
12 #define MTK_DP_HPD_CONNECT		BIT(2)
13 #define MTK_DP_HPD_INTERRUPT		BIT(3)
14 
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00		0x0
17 #define RG_XTP_GLB_BIAS_INTR_CTRL		GENMASK(20, 16)
18 #define DP_PHY_GLB_DPAUX_TX		0x8
19 #define RG_CKM_PT0_CKTX_IMPSEL			GENMASK(23, 20)
20 #define MTK_DP_0034			0x34
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL		BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN		BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL		BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN		BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL		BIT(11)
26 #define DA_CKM_CKTX0_EN_FORCE_EN		BIT(10)
27 #define DA_CKM_XTAL_CK_FORCE_VAL		BIT(9)
28 #define DA_CKM_XTAL_CK_FORCE_EN			BIT(8)
29 #define DA_CKM_BIAS_LPF_EN_FORCE_VAL		BIT(7)
30 #define DA_CKM_BIAS_LPF_EN_FORCE_EN		BIT(6)
31 #define DA_CKM_BIAS_EN_FORCE_VAL		BIT(5)
32 #define DA_CKM_BIAS_EN_FORCE_EN			BIT(4)
33 #define DA_XTP_GLB_AVD10_ON_FORCE_VAL		BIT(3)
34 #define DA_XTP_GLB_AVD10_ON_FORCE		BIT(2)
35 #define DA_XTP_GLB_LDO_EN_FORCE_VAL		BIT(1)
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN		BIT(0)
37 #define DP_PHY_LANE_TX_0		0x104
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS		GENMASK(15, 12)
39 #define RG_XTP_LN0_TX_IMPSEL_NMOS		GENMASK(19, 16)
40 #define DP_PHY_LANE_TX_1		0x204
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS		GENMASK(15, 12)
42 #define RG_XTP_LN1_TX_IMPSEL_NMOS		GENMASK(19, 16)
43 #define DP_PHY_LANE_TX_2		0x304
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS		GENMASK(15, 12)
45 #define RG_XTP_LN2_TX_IMPSEL_NMOS		GENMASK(19, 16)
46 #define DP_PHY_LANE_TX_3		0x404
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS		GENMASK(15, 12)
48 #define RG_XTP_LN3_TX_IMPSEL_NMOS		GENMASK(19, 16)
49 #define MTK_DP_1040			0x1040
50 #define RG_DPAUX_RX_VALID_DEGLITCH_EN		BIT(2)
51 #define RG_XTP_GLB_CKDET_EN			BIT(1)
52 #define RG_DPAUX_RX_EN				BIT(0)
53 
54 /* offset: TOP_OFFSET (0x2000) */
55 #define MTK_DP_TOP_PWR_STATE		0x2000
56 #define DP_PWR_STATE_MASK			GENMASK(1, 0)
57 #define DP_PWR_STATE_BANDGAP			BIT(0)
58 #define DP_PWR_STATE_BANDGAP_TPLL		BIT(1)
59 #define DP_PWR_STATE_BANDGAP_TPLL_LANE		GENMASK(1, 0)
60 #define MTK_DP_TOP_SWING_EMP		0x2004
61 #define DP_TX0_VOLT_SWING_MASK			GENMASK(1, 0)
62 #define DP_TX0_VOLT_SWING_SHIFT			0
63 #define DP_TX0_PRE_EMPH_MASK			GENMASK(3, 2)
64 #define DP_TX0_PRE_EMPH_SHIFT			2
65 #define DP_TX1_VOLT_SWING_MASK			GENMASK(9, 8)
66 #define DP_TX1_VOLT_SWING_SHIFT			8
67 #define DP_TX1_PRE_EMPH_MASK			GENMASK(11, 10)
68 #define DP_TX2_VOLT_SWING_MASK			GENMASK(17, 16)
69 #define DP_TX2_PRE_EMPH_MASK			GENMASK(19, 18)
70 #define DP_TX3_VOLT_SWING_MASK			GENMASK(25, 24)
71 #define DP_TX3_PRE_EMPH_MASK			GENMASK(27, 26)
72 #define MTK_DP_TOP_RESET_AND_PROBE	0x2020
73 #define SW_RST_B_PHYD				BIT(4)
74 #define MTK_DP_TOP_IRQ_MASK		0x202c
75 #define IRQ_MASK_AUX_TOP_IRQ			BIT(2)
76 #define MTK_DP_TOP_MEM_PD		0x2038
77 #define MEM_ISO_EN				BIT(0)
78 #define FUSE_SEL				BIT(2)
79 
80 /* offset: ENC0_OFFSET (0x3000) */
81 #define MTK_DP_ENC0_P0_3000			0x3000
82 #define LANE_NUM_DP_ENC0_P0_MASK			GENMASK(1, 0)
83 #define VIDEO_MUTE_SW_DP_ENC0_P0			BIT(2)
84 #define VIDEO_MUTE_SEL_DP_ENC0_P0			BIT(3)
85 #define ENHANCED_FRAME_EN_DP_ENC0_P0			BIT(4)
86 #define MTK_DP_ENC0_P0_3004			0x3004
87 #define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK		BIT(8)
88 #define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)
89 #define MTK_DP_ENC0_P0_3010			0x3010
90 #define HTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
91 #define MTK_DP_ENC0_P0_3014			0x3014
92 #define VTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
93 #define MTK_DP_ENC0_P0_3018			0x3018
94 #define HSTART_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
95 #define MTK_DP_ENC0_P0_301C			0x301c
96 #define VSTART_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
97 #define MTK_DP_ENC0_P0_3020			0x3020
98 #define HWIDTH_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
99 #define MTK_DP_ENC0_P0_3024			0x3024
100 #define VHEIGHT_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
101 #define MTK_DP_ENC0_P0_3028			0x3028
102 #define HSW_SW_DP_ENC0_P0_MASK				GENMASK(14, 0)
103 #define HSP_SW_DP_ENC0_P0_MASK				BIT(15)
104 #define MTK_DP_ENC0_P0_302C			0x302c
105 #define VSW_SW_DP_ENC0_P0_MASK				GENMASK(14, 0)
106 #define VSP_SW_DP_ENC0_P0_MASK				BIT(15)
107 #define MTK_DP_ENC0_P0_3030			0x3030
108 #define HTOTAL_SEL_DP_ENC0_P0				BIT(0)
109 #define VTOTAL_SEL_DP_ENC0_P0				BIT(1)
110 #define HSTART_SEL_DP_ENC0_P0				BIT(2)
111 #define VSTART_SEL_DP_ENC0_P0				BIT(3)
112 #define HWIDTH_SEL_DP_ENC0_P0				BIT(4)
113 #define VHEIGHT_SEL_DP_ENC0_P0				BIT(5)
114 #define HSP_SEL_DP_ENC0_P0				BIT(6)
115 #define HSW_SEL_DP_ENC0_P0				BIT(7)
116 #define VSP_SEL_DP_ENC0_P0				BIT(8)
117 #define VSW_SEL_DP_ENC0_P0				BIT(9)
118 #define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0		BIT(11)
119 #define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0		BIT(12)
120 #define MTK_DP_ENC0_P0_3034			0x3034
121 #define MTK_DP_ENC0_P0_3038			0x3038
122 #define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK		BIT(11)
123 #define MTK_DP_ENC0_P0_303C			0x303c
124 #define SRAM_START_READ_THRD_DP_ENC0_P0_MASK		GENMASK(5, 0)
125 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK		GENMASK(10, 8)
126 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT		(0 << 8)
127 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT		(1 << 8)
128 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT		(2 << 8)
129 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT		(3 << 8)
130 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT		(4 << 8)
131 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK		GENMASK(14, 12)
132 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB		(0 << 12)
133 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422		(1 << 12)
134 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420		(2 << 12)
135 #define VIDEO_MN_GEN_EN_DP_ENC0_P0			BIT(15)
136 #define MTK_DP_ENC0_P0_3040			0x3040
137 #define SDP_DOWN_CNT_DP_ENC0_P0_VAL			0x20
138 #define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK		GENMASK(11, 0)
139 #define MTK_DP_ENC0_P0_304C			0x304c
140 #define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK			BIT(2)
141 #define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK		BIT(8)
142 #define MTK_DP_ENC0_P0_3064			0x3064
143 #define HDE_NUM_LAST_DP_ENC0_P0_MASK			GENMASK(15, 0)
144 #define MTK_DP_ENC0_P0_3088			0x3088
145 #define AU_EN_DP_ENC0_P0				BIT(6)
146 #define AUDIO_8CH_EN_DP_ENC0_P0_MASK			BIT(7)
147 #define AUDIO_8CH_SEL_DP_ENC0_P0_MASK			BIT(8)
148 #define AUDIO_2CH_EN_DP_ENC0_P0_MASK			BIT(14)
149 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK			BIT(15)
150 #define MTK_DP_ENC0_P0_308C			0x308c
151 #define CH_STATUS_0_DP_ENC0_P0_MASK			GENMASK(15, 0)
152 #define MTK_DP_ENC0_P0_3090			0x3090
153 #define CH_STATUS_1_DP_ENC0_P0_MASK			GENMASK(15, 0)
154 #define MTK_DP_ENC0_P0_3094			0x3094
155 #define CH_STATUS_2_DP_ENC0_P0_MASK			GENMASK(7, 0)
156 #define MTK_DP_ENC0_P0_30A4			0x30a4
157 #define AU_TS_CFG_DP_ENC0_P0_MASK			GENMASK(7, 0)
158 #define MTK_DP_ENC0_P0_30A8			0x30a8
159 #define MTK_DP_ENC0_P0_30BC			0x30bc
160 #define ISRC_CONT_DP_ENC0_P0				BIT(0)
161 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK	GENMASK(10, 8)
162 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2	(1 << 8)
163 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4	(2 << 8)
164 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8	(3 << 8)
165 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2	(5 << 8)
166 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4	(6 << 8)
167 #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8	(7 << 8)
168 #define MTK_DP_ENC0_P0_30D8			0x30d8
169 #define MTK_DP_ENC0_P0_312C			0x312c
170 #define ASP_HB2_DP_ENC0_P0_MASK				GENMASK(7, 0)
171 #define ASP_HB3_DP_ENC0_P0_MASK				GENMASK(15, 8)
172 #define MTK_DP_ENC0_P0_3154			0x3154
173 #define PGEN_HTOTAL_DP_ENC0_P0_MASK			GENMASK(13, 0)
174 #define MTK_DP_ENC0_P0_3158			0x3158
175 #define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK		GENMASK(13, 0)
176 #define MTK_DP_ENC0_P0_315C			0x315c
177 #define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK		GENMASK(13, 0)
178 #define MTK_DP_ENC0_P0_3160			0x3160
179 #define PGEN_HFDE_START_DP_ENC0_P0_MASK			GENMASK(13, 0)
180 #define MTK_DP_ENC0_P0_3164			0x3164
181 #define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK		GENMASK(13, 0)
182 #define MTK_DP_ENC0_P0_3168			0x3168
183 #define PGEN_VTOTAL_DP_ENC0_P0_MASK			GENMASK(12, 0)
184 #define MTK_DP_ENC0_P0_316C			0x316c
185 #define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK		GENMASK(12, 0)
186 #define MTK_DP_ENC0_P0_3170			0x3170
187 #define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK		GENMASK(12, 0)
188 #define MTK_DP_ENC0_P0_3174			0x3174
189 #define PGEN_VFDE_START_DP_ENC0_P0_MASK			GENMASK(12, 0)
190 #define MTK_DP_ENC0_P0_3178			0x3178
191 #define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK		GENMASK(12, 0)
192 #define MTK_DP_ENC0_P0_31B0			0x31b0
193 #define PGEN_PATTERN_SEL_VAL				4
194 #define PGEN_PATTERN_SEL_MASK				GENMASK(6, 4)
195 #define MTK_DP_ENC0_P0_31EC			0x31ec
196 #define AUDIO_CH_SRC_SEL_DP_ENC0_P0			BIT(4)
197 #define ISRC1_HB3_DP_ENC0_P0_MASK			GENMASK(15, 8)
198 
199 /* offset: ENC1_OFFSET (0x3200) */
200 #define MTK_DP_ENC1_P0_3200			0x3200
201 #define MTK_DP_ENC1_P0_3280			0x3280
202 #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK			GENMASK(4, 0)
203 #define SDP_PACKET_W_DP_ENC1_P0				BIT(5)
204 #define SDP_PACKET_W_DP_ENC1_P0_MASK			BIT(5)
205 #define MTK_DP_ENC1_P0_3300			0x3300
206 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL		2
207 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK		GENMASK(9, 8)
208 #define MTK_DP_ENC1_P0_3304			0x3304
209 #define AU_PRTY_REGEN_DP_ENC1_P0_MASK			BIT(8)
210 #define AU_CH_STS_REGEN_DP_ENC1_P0_MASK			BIT(9)
211 #define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK	BIT(12)
212 #define MTK_DP_ENC1_P0_3324			0x3324
213 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK		GENMASK(9, 8)
214 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX		0
215 #define MTK_DP_ENC1_P0_3364			0x3364
216 #define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL		0x20
217 #define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK	GENMASK(11, 0)
218 #define FIFO_READ_START_POINT_DP_ENC1_P0_VAL		4
219 #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK		GENMASK(15, 12)
220 #define MTK_DP_ENC1_P0_3368			0x3368
221 #define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0	BIT(0)
222 #define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0		BIT(4)
223 #define SDP_DP13_EN_DP_ENC1_P0				BIT(8)
224 #define BS2BS_MODE_DP_ENC1_P0				BIT(12)
225 #define BS2BS_MODE_DP_ENC1_P0_MASK			GENMASK(13, 12)
226 #define BS2BS_MODE_DP_ENC1_P0_VAL			1
227 #define DP_ENC1_P0_3368_VAL				(VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | \
228 							 VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \
229 							 SDP_DP13_EN_DP_ENC1_P0 | \
230 							 BS2BS_MODE_DP_ENC1_P0)
231 #define MTK_DP_ENC1_P0_33F4			0x33f4
232 #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN			BIT(0)
233 #define DP_ENC_DUMMY_RW_1				BIT(9)
234 
235 /* offset: TRANS_OFFSET (0x3400) */
236 #define MTK_DP_TRANS_P0_3400				0x3400
237 #define PATTERN1_EN_DP_TRANS_P0_MASK				BIT(12)
238 #define PATTERN2_EN_DP_TRANS_P0_MASK				BIT(13)
239 #define PATTERN3_EN_DP_TRANS_P0_MASK				BIT(14)
240 #define PATTERN4_EN_DP_TRANS_P0_MASK				BIT(15)
241 #define MTK_DP_TRANS_P0_3404				0x3404
242 #define DP_SCR_EN_DP_TRANS_P0_MASK				BIT(0)
243 #define MTK_DP_TRANS_P0_340C				0x340c
244 #define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0		BIT(13)
245 #define MTK_DP_TRANS_P0_3410				0x3410
246 #define HPD_DEB_THD_DP_TRANS_P0_MASK				GENMASK(3, 0)
247 #define HPD_INT_THD_DP_TRANS_P0_MASK				GENMASK(7, 4)
248 #define HPD_INT_THD_DP_TRANS_P0_LOWER_500US			(2 << 4)
249 #define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US			(2 << 6)
250 #define HPD_DISC_THD_DP_TRANS_P0_MASK				GENMASK(11, 8)
251 #define HPD_CONN_THD_DP_TRANS_P0_MASK				GENMASK(15, 12)
252 #define MTK_DP_TRANS_P0_3414				0x3414
253 #define HPD_DB_DP_TRANS_P0_MASK					BIT(2)
254 #define MTK_DP_TRANS_P0_3418				0x3418
255 #define IRQ_CLR_DP_TRANS_P0_MASK				GENMASK(3, 0)
256 #define IRQ_MASK_DP_TRANS_P0_MASK				GENMASK(7, 4)
257 #define IRQ_MASK_DP_TRANS_P0_DISC_IRQ				(BIT(1) << 4)
258 #define IRQ_MASK_DP_TRANS_P0_CONN_IRQ				(BIT(2) << 4)
259 #define IRQ_MASK_DP_TRANS_P0_INT_IRQ				(BIT(3) << 4)
260 #define IRQ_STATUS_DP_TRANS_P0_MASK				GENMASK(15, 12)
261 #define MTK_DP_TRANS_P0_342C				0x342c
262 #define XTAL_FREQ_DP_TRANS_P0_DEFAULT				(BIT(0) | BIT(3) | BIT(5) | BIT(6))
263 #define XTAL_FREQ_DP_TRANS_P0_MASK				GENMASK(7, 0)
264 #define MTK_DP_TRANS_P0_3430				0x3430
265 #define HPD_INT_THD_ECO_DP_TRANS_P0_MASK			GENMASK(1, 0)
266 #define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT		BIT(1)
267 #define MTK_DP_TRANS_P0_34A4				0x34a4
268 #define LANE_NUM_DP_TRANS_P0_MASK				GENMASK(3, 2)
269 #define MTK_DP_TRANS_P0_3540				0x3540
270 #define FEC_EN_DP_TRANS_P0_MASK					BIT(0)
271 #define FEC_CLOCK_EN_MODE_DP_TRANS_P0				BIT(3)
272 #define MTK_DP_TRANS_P0_3580				0x3580
273 #define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK		BIT(8)
274 #define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK		BIT(9)
275 #define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK		BIT(10)
276 #define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK		BIT(11)
277 #define MTK_DP_TRANS_P0_35C8				0x35c8
278 #define SW_IRQ_CLR_DP_TRANS_P0_MASK				GENMASK(15, 0)
279 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK				GENMASK(15, 0)
280 #define MTK_DP_TRANS_P0_35D0				0x35d0
281 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK			GENMASK(15, 0)
282 #define MTK_DP_TRANS_P0_35F0				0x35f0
283 #define DP_TRANS_DUMMY_RW_0					BIT(3)
284 #define DP_TRANS_DUMMY_RW_0_MASK				GENMASK(3, 2)
285 
286 /* offset: AUX_OFFSET (0x3600) */
287 #define MTK_DP_AUX_P0_360C			0x360c
288 #define AUX_TIMEOUT_THR_AUX_TX_P0_MASK			GENMASK(12, 0)
289 #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL			0x1595
290 #define MTK_DP_AUX_P0_3614			0x3614
291 #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK		GENMASK(6, 0)
292 #define AUX_RX_UI_CNT_THR_AUX_FOR_26M			13
293 #define MTK_DP_AUX_P0_3618			0x3618
294 #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK			BIT(9)
295 #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK	GENMASK(3, 0)
296 #define MTK_DP_AUX_P0_3620			0x3620
297 #define AUX_RD_MODE_AUX_TX_P0_MASK			BIT(9)
298 #define AUX_RX_FIFO_READ_PULSE_TX_P0			BIT(8)
299 #define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK		GENMASK(7, 0)
300 #define MTK_DP_AUX_P0_3624			0x3624
301 #define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK		GENMASK(3, 0)
302 #define MTK_DP_AUX_P0_3628			0x3628
303 #define AUX_RX_PHY_STATE_AUX_TX_P0_MASK			GENMASK(9, 0)
304 #define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE		BIT(0)
305 #define MTK_DP_AUX_P0_362C			0x362c
306 #define AUX_NO_LENGTH_AUX_TX_P0				BIT(0)
307 #define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK		BIT(1)
308 #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK		GENMASK(15, 2)
309 #define MTK_DP_AUX_P0_3630			0x3630
310 #define AUX_TX_REQUEST_READY_AUX_TX_P0			BIT(3)
311 #define MTK_DP_AUX_P0_3634			0x3634
312 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK		GENMASK(15, 8)
313 #define AUX_TX_OVER_SAMPLE_RATE_FOR_26M			25
314 #define MTK_DP_AUX_P0_3640			0x3640
315 #define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0		BIT(6)
316 #define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0		BIT(5)
317 #define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0		BIT(4)
318 #define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0			BIT(3)
319 #define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0			BIT(2)
320 #define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0			BIT(1)
321 #define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0			BIT(0)
322 #define DP_AUX_P0_3640_VAL				(AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 | \
323 							 AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 | \
324 							 AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0 | \
325 							 AUX_RX_CMD_RECV_IRQ_AUX_TX_P0 | \
326 							 AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 | \
327 							 AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 | \
328 							 AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0)
329 #define MTK_DP_AUX_P0_3644			0x3644
330 #define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK		GENMASK(3, 0)
331 #define MTK_DP_AUX_P0_3648			0x3648
332 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK		GENMASK(15, 0)
333 #define MTK_DP_AUX_P0_364C			0x364c
334 #define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK		GENMASK(3, 0)
335 #define MTK_DP_AUX_P0_3650			0x3650
336 #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK			GENMASK(15, 12)
337 #define PHY_FIFO_RST_AUX_TX_P0_MASK			BIT(9)
338 #define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0			BIT(8)
339 #define MTK_DP_AUX_P0_3658			0x3658
340 #define AUX_TX_OV_EN_AUX_TX_P0_MASK			BIT(0)
341 #define MTK_DP_AUX_P0_3690			0x3690
342 #define RX_REPLY_COMPLETE_MODE_AUX_TX_P0		BIT(8)
343 #define MTK_DP_AUX_P0_3704			0x3704
344 #define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK	BIT(1)
345 #define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0		BIT(2)
346 #define MTK_DP_AUX_P0_3708			0x3708
347 #define MTK_DP_AUX_P0_37C8			0x37c8
348 #define MTK_ATOP_EN_AUX_TX_P0				BIT(0)
349 
350 #endif /*_MTK_DP_REG_H_*/
351