1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DAL_DDC_SERVICE_TYPES_H__ 26 #define __DAL_DDC_SERVICE_TYPES_H__ 27 28 /* 0010FA dongles (ST Micro) external converter chip id */ 29 #define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA 30 /* 0022B9 external converter chip id */ 31 #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9 32 #define DP_BRANCH_DEVICE_ID_00001A 0x00001A 33 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1 34 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24 35 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C 36 #define DP_BRANCH_DEVICE_ID_006037 0x006037 37 #define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8 38 #define DP_BRANCH_DEVICE_ID_0060AD 0x0060AD 39 #define DP_BRANCH_HW_REV_10 0x10 40 #define DP_BRANCH_HW_REV_20 0x20 41 42 #define DP_DEVICE_ID_38EC11 0x38EC11 43 #define DP_DEVICE_ID_BA4159 0xBA4159 44 #define DP_FORCE_PSRSU_CAPABILITY 0x40F 45 46 #define DP_SINK_PSR_ACTIVE_VTOTAL 0x373 47 #define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375 48 #define DP_SOURCE_PSR_ACTIVE_VTOTAL 0x376 49 50 enum ddc_result { 51 DDC_RESULT_UNKNOWN = 0, 52 DDC_RESULT_SUCESSFULL, 53 DDC_RESULT_FAILED_CHANNEL_BUSY, 54 DDC_RESULT_FAILED_TIMEOUT, 55 DDC_RESULT_FAILED_PROTOCOL_ERROR, 56 DDC_RESULT_FAILED_NACK, 57 DDC_RESULT_FAILED_INCOMPLETE, 58 DDC_RESULT_FAILED_OPERATION, 59 DDC_RESULT_FAILED_INVALID_OPERATION, 60 DDC_RESULT_FAILED_BUFFER_OVERFLOW, 61 DDC_RESULT_FAILED_HPD_DISCON 62 }; 63 64 enum ddc_service_type { 65 DDC_SERVICE_TYPE_CONNECTOR, 66 DDC_SERVICE_TYPE_DISPLAY_PORT_MST, 67 }; 68 69 /** 70 * display sink capability 71 */ 72 struct display_sink_capability { 73 /* dongle type (DP converter, CV smart dongle) */ 74 enum display_dongle_type dongle_type; 75 bool is_dongle_type_one; 76 77 /********************************************************** 78 capabilities going INTO SINK DEVICE (stream capabilities) 79 **********************************************************/ 80 /* Dongle's downstream count. */ 81 uint32_t downstrm_sink_count; 82 /* Is dongle's downstream count info field (downstrm_sink_count) 83 * valid. */ 84 bool downstrm_sink_count_valid; 85 86 /* Maximum additional audio delay in microsecond (us) */ 87 uint32_t additional_audio_delay; 88 /* Audio latency value in microsecond (us) */ 89 uint32_t audio_latency; 90 /* Interlace video latency value in microsecond (us) */ 91 uint32_t video_latency_interlace; 92 /* Progressive video latency value in microsecond (us) */ 93 uint32_t video_latency_progressive; 94 /* Dongle caps: Maximum pixel clock supported over dongle for HDMI */ 95 uint32_t max_hdmi_pixel_clock; 96 /* Dongle caps: Maximum deep color supported over dongle for HDMI */ 97 enum dc_color_depth max_hdmi_deep_color; 98 99 /************************************************************ 100 capabilities going OUT OF SOURCE DEVICE (link capabilities) 101 ************************************************************/ 102 /* support for Spread Spectrum(SS) */ 103 bool ss_supported; 104 /* DP link settings (laneCount, linkRate, Spread) */ 105 uint32_t dp_link_lane_count; 106 uint32_t dp_link_rate; 107 uint32_t dp_link_spead; 108 109 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 110 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 111 bool is_dp_hdmi_s3d_converter; 112 /* to check if we have queried the display capability 113 * for eDP panel already. */ 114 bool is_edp_sink_cap_valid; 115 116 enum ddc_transaction_type transaction_type; 117 enum signal_type signal; 118 }; 119 120 struct av_sync_data { 121 uint8_t av_granularity;/* DPCD 00023h */ 122 uint8_t aud_dec_lat1;/* DPCD 00024h */ 123 uint8_t aud_dec_lat2;/* DPCD 00025h */ 124 uint8_t aud_pp_lat1;/* DPCD 00026h */ 125 uint8_t aud_pp_lat2;/* DPCD 00027h */ 126 uint8_t vid_inter_lat;/* DPCD 00028h */ 127 uint8_t vid_prog_lat;/* DPCD 00029h */ 128 uint8_t aud_del_ins1;/* DPCD 0002Bh */ 129 uint8_t aud_del_ins2;/* DPCD 0002Ch */ 130 uint8_t aud_del_ins3;/* DPCD 0002Dh */ 131 }; 132 133 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ 134