1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
6 #define _DPU_TRACE_H_
7 
8 #include <linux/stringify.h>
9 #include <linux/types.h>
10 #include <linux/tracepoint.h>
11 
12 #include <drm/drm_rect.h>
13 #include "dpu_crtc.h"
14 #include "dpu_encoder_phys.h"
15 #include "dpu_hw_mdss.h"
16 #include "dpu_hw_vbif.h"
17 #include "dpu_plane.h"
18 
19 #undef TRACE_SYSTEM
20 #define TRACE_SYSTEM dpu
21 #undef TRACE_INCLUDE_FILE
22 #define TRACE_INCLUDE_FILE dpu_trace
23 
24 TRACE_EVENT(dpu_perf_set_qos_luts,
25 	TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
26 		u32 lut, u32 lut_usage),
27 	TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
28 	TP_STRUCT__entry(
29 			__field(u32, pnum)
30 			__field(u32, fmt)
31 			__field(bool, rt)
32 			__field(u32, fl)
33 			__field(u64, lut)
34 			__field(u32, lut_usage)
35 	),
36 	TP_fast_assign(
37 			__entry->pnum = pnum;
38 			__entry->fmt = fmt;
39 			__entry->rt = rt;
40 			__entry->fl = fl;
41 			__entry->lut = lut;
42 			__entry->lut_usage = lut_usage;
43 	),
44 	TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
45 			__entry->pnum, __entry->fmt,
46 			__entry->rt, __entry->fl,
47 			__entry->lut, __entry->lut_usage)
48 );
49 
50 TRACE_EVENT(dpu_perf_set_danger_luts,
51 	TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
52 		u32 safe_lut),
53 	TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
54 	TP_STRUCT__entry(
55 			__field(u32, pnum)
56 			__field(u32, fmt)
57 			__field(u32, mode)
58 			__field(u32, danger_lut)
59 			__field(u32, safe_lut)
60 	),
61 	TP_fast_assign(
62 			__entry->pnum = pnum;
63 			__entry->fmt = fmt;
64 			__entry->mode = mode;
65 			__entry->danger_lut = danger_lut;
66 			__entry->safe_lut = safe_lut;
67 	),
68 	TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
69 			__entry->pnum, __entry->fmt,
70 			__entry->mode, __entry->danger_lut,
71 			__entry->safe_lut)
72 );
73 
74 TRACE_EVENT(dpu_perf_set_ot,
75 	TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
76 	TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
77 	TP_STRUCT__entry(
78 			__field(u32, pnum)
79 			__field(u32, xin_id)
80 			__field(u32, rd_lim)
81 			__field(u32, vbif_idx)
82 	),
83 	TP_fast_assign(
84 			__entry->pnum = pnum;
85 			__entry->xin_id = xin_id;
86 			__entry->rd_lim = rd_lim;
87 			__entry->vbif_idx = vbif_idx;
88 	),
89 	TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
90 			__entry->pnum, __entry->xin_id, __entry->rd_lim,
91 			__entry->vbif_idx)
92 )
93 
94 TRACE_EVENT(dpu_cmd_release_bw,
95 	TP_PROTO(u32 crtc_id),
96 	TP_ARGS(crtc_id),
97 	TP_STRUCT__entry(
98 			__field(u32, crtc_id)
99 	),
100 	TP_fast_assign(
101 			__entry->crtc_id = crtc_id;
102 	),
103 	TP_printk("crtc:%d", __entry->crtc_id)
104 );
105 
106 TRACE_EVENT(tracing_mark_write,
107 	TP_PROTO(int pid, const char *name, bool trace_begin),
108 	TP_ARGS(pid, name, trace_begin),
109 	TP_STRUCT__entry(
110 			__field(int, pid)
111 			__string(trace_name, name)
112 			__field(bool, trace_begin)
113 	),
114 	TP_fast_assign(
115 			__entry->pid = pid;
116 			__assign_str(trace_name, name);
117 			__entry->trace_begin = trace_begin;
118 	),
119 	TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
120 		__entry->pid, __get_str(trace_name))
121 )
122 
123 TRACE_EVENT(dpu_trace_counter,
124 	TP_PROTO(int pid, char *name, int value),
125 	TP_ARGS(pid, name, value),
126 	TP_STRUCT__entry(
127 			__field(int, pid)
128 			__string(counter_name, name)
129 			__field(int, value)
130 	),
131 	TP_fast_assign(
132 			__entry->pid = current->tgid;
133 			__assign_str(counter_name, name);
134 			__entry->value = value;
135 	),
136 	TP_printk("%d|%s|%d", __entry->pid,
137 			__get_str(counter_name), __entry->value)
138 )
139 
140 TRACE_EVENT(dpu_perf_crtc_update,
141 	TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate,
142 			bool stop_req, bool update_bus, bool update_clk),
143 	TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk),
144 	TP_STRUCT__entry(
145 			__field(u32, crtc)
146 			__field(u64, bw_ctl)
147 			__field(u32, core_clk_rate)
148 			__field(bool, stop_req)
149 			__field(u32, update_bus)
150 			__field(u32, update_clk)
151 	),
152 	TP_fast_assign(
153 			__entry->crtc = crtc;
154 			__entry->bw_ctl = bw_ctl;
155 			__entry->core_clk_rate = core_clk_rate;
156 			__entry->stop_req = stop_req;
157 			__entry->update_bus = update_bus;
158 			__entry->update_clk = update_clk;
159 	),
160 	 TP_printk(
161 		"crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
162 			__entry->crtc,
163 			__entry->bw_ctl,
164 			__entry->core_clk_rate,
165 			__entry->stop_req,
166 			__entry->update_bus,
167 			__entry->update_clk)
168 );
169 
170 DECLARE_EVENT_CLASS(dpu_irq_template,
171 	TP_PROTO(int irq_idx),
172 	TP_ARGS(irq_idx),
173 	TP_STRUCT__entry(
174 		__field(	int,			irq_idx		)
175 	),
176 	TP_fast_assign(
177 		__entry->irq_idx = irq_idx;
178 	),
179 	TP_printk("irq=%d", __entry->irq_idx)
180 );
181 DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success,
182 	TP_PROTO(int irq_idx),
183 	TP_ARGS(irq_idx)
184 );
185 DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success,
186 	TP_PROTO(int irq_idx),
187 	TP_ARGS(irq_idx)
188 );
189 
190 TRACE_EVENT(dpu_enc_irq_wait_success,
191 	TP_PROTO(uint32_t drm_id, void *func,
192 		 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
193 	TP_ARGS(drm_id, func, irq_idx, pp_idx, atomic_cnt),
194 	TP_STRUCT__entry(
195 		__field(	uint32_t,		drm_id		)
196 		__field(	void *,			func		)
197 		__field(	int,			irq_idx		)
198 		__field(	enum dpu_pingpong,	pp_idx		)
199 		__field(	int,			atomic_cnt	)
200 	),
201 	TP_fast_assign(
202 		__entry->drm_id = drm_id;
203 		__entry->func = func;
204 		__entry->irq_idx = irq_idx;
205 		__entry->pp_idx = pp_idx;
206 		__entry->atomic_cnt = atomic_cnt;
207 	),
208 	TP_printk("id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d",
209 		  __entry->drm_id, __entry->func,
210 		  __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
211 );
212 
213 DECLARE_EVENT_CLASS(dpu_drm_obj_template,
214 	TP_PROTO(uint32_t drm_id),
215 	TP_ARGS(drm_id),
216 	TP_STRUCT__entry(
217 		__field(	uint32_t,		drm_id		)
218 	),
219 	TP_fast_assign(
220 		__entry->drm_id = drm_id;
221 	),
222 	TP_printk("id=%u", __entry->drm_id)
223 );
224 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
225 	TP_PROTO(uint32_t drm_id),
226 	TP_ARGS(drm_id)
227 );
228 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
229 	TP_PROTO(uint32_t drm_id),
230 	TP_ARGS(drm_id)
231 );
232 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
233 	TP_PROTO(uint32_t drm_id),
234 	TP_ARGS(drm_id)
235 );
236 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
237 	TP_PROTO(uint32_t drm_id),
238 	TP_ARGS(drm_id)
239 );
240 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
241 	TP_PROTO(uint32_t drm_id),
242 	TP_ARGS(drm_id)
243 );
244 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
245 	TP_PROTO(uint32_t drm_id),
246 	TP_ARGS(drm_id)
247 );
248 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
249 	TP_PROTO(uint32_t drm_id),
250 	TP_ARGS(drm_id)
251 );
252 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
253 	TP_PROTO(uint32_t drm_id),
254 	TP_ARGS(drm_id)
255 );
256 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
257 	TP_PROTO(uint32_t drm_id),
258 	TP_ARGS(drm_id)
259 );
260 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
261 	TP_PROTO(uint32_t drm_id),
262 	TP_ARGS(drm_id)
263 );
264 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
265 	TP_PROTO(uint32_t drm_id),
266 	TP_ARGS(drm_id)
267 );
268 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
269 	TP_PROTO(uint32_t drm_id),
270 	TP_ARGS(drm_id)
271 );
272 
273 TRACE_EVENT(dpu_enc_enable,
274 	TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
275 	TP_ARGS(drm_id, hdisplay, vdisplay),
276 	TP_STRUCT__entry(
277 		__field(	uint32_t,		drm_id		)
278 		__field(	int,			hdisplay	)
279 		__field(	int,			vdisplay	)
280 	),
281 	TP_fast_assign(
282 		__entry->drm_id = drm_id;
283 		__entry->hdisplay = hdisplay;
284 		__entry->vdisplay = vdisplay;
285 	),
286 	TP_printk("id=%u, mode=%dx%d",
287 		  __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
288 );
289 
290 DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
291 	TP_PROTO(uint32_t drm_id, int val),
292 	TP_ARGS(drm_id, val),
293 	TP_STRUCT__entry(
294 		__field(	uint32_t,	drm_id	)
295 		__field(	int,		val	)
296 	),
297 	TP_fast_assign(
298 		__entry->drm_id = drm_id;
299 		__entry->val = val;
300 	),
301 	TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
302 );
303 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
304 	TP_PROTO(uint32_t drm_id, int count),
305 	TP_ARGS(drm_id, count)
306 );
307 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
308 	TP_PROTO(uint32_t drm_id, int ctl_idx),
309 	TP_ARGS(drm_id, ctl_idx)
310 );
311 
312 TRACE_EVENT(dpu_enc_atomic_check_flags,
313 	TP_PROTO(uint32_t drm_id, unsigned int flags),
314 	TP_ARGS(drm_id, flags),
315 	TP_STRUCT__entry(
316 		__field(	uint32_t,		drm_id		)
317 		__field(	unsigned int,		flags		)
318 	),
319 	TP_fast_assign(
320 		__entry->drm_id = drm_id;
321 		__entry->flags = flags;
322 	),
323 	TP_printk("id=%u, flags=%u",
324 		  __entry->drm_id, __entry->flags)
325 );
326 
327 DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
328 	TP_PROTO(uint32_t drm_id, bool enable),
329 	TP_ARGS(drm_id, enable),
330 	TP_STRUCT__entry(
331 		__field(	uint32_t,		drm_id		)
332 		__field(	bool,			enable		)
333 	),
334 	TP_fast_assign(
335 		__entry->drm_id = drm_id;
336 		__entry->enable = enable;
337 	),
338 	TP_printk("id=%u, enable=%s",
339 		  __entry->drm_id, __entry->enable ? "true" : "false")
340 );
341 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
342 	TP_PROTO(uint32_t drm_id, bool enable),
343 	TP_ARGS(drm_id, enable)
344 );
345 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
346 	TP_PROTO(uint32_t drm_id, bool enable),
347 	TP_ARGS(drm_id, enable)
348 );
349 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
350 	TP_PROTO(uint32_t drm_id, bool enable),
351 	TP_ARGS(drm_id, enable)
352 );
353 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
354 	TP_PROTO(uint32_t drm_id, bool enable),
355 	TP_ARGS(drm_id, enable)
356 );
357 
358 TRACE_EVENT(dpu_enc_rc,
359 	TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
360 		 int rc_state, const char *stage),
361 	TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
362 	TP_STRUCT__entry(
363 		__field(	uint32_t,	drm_id			)
364 		__field(	u32,		sw_event		)
365 		__field(	bool,		idle_pc_supported	)
366 		__field(	int,		rc_state		)
367 		__string(	stage_str,	stage			)
368 	),
369 	TP_fast_assign(
370 		__entry->drm_id = drm_id;
371 		__entry->sw_event = sw_event;
372 		__entry->idle_pc_supported = idle_pc_supported;
373 		__entry->rc_state = rc_state;
374 		__assign_str(stage_str, stage);
375 	),
376 	TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d",
377 		  __get_str(stage_str), __entry->drm_id, __entry->sw_event,
378 		  __entry->idle_pc_supported ? "true" : "false",
379 		  __entry->rc_state)
380 );
381 
382 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
383 	TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf intf_idx,
384 			enum dpu_wb wb_idx),
385 	TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
386 	TP_STRUCT__entry(
387 		__field(	uint32_t,	drm_id		)
388 		__field(	u32,		event		)
389 		__string(	intf_mode_str,	intf_mode	)
390 		__field(	enum dpu_intf,	intf_idx	)
391 		__field(	enum dpu_wb,	wb_idx		)
392 	),
393 	TP_fast_assign(
394 		__entry->drm_id = drm_id;
395 		__entry->event = event;
396 		__assign_str(intf_mode_str, intf_mode);
397 		__entry->intf_idx = intf_idx;
398 		__entry->wb_idx = wb_idx;
399 	),
400 	TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", __entry->drm_id,
401 			__entry->event, __get_str(intf_mode_str),
402 			__entry->intf_idx, __entry->wb_idx)
403 );
404 
405 TRACE_EVENT(dpu_enc_frame_done_cb,
406 	TP_PROTO(uint32_t drm_id, unsigned int idx,
407 		 unsigned long frame_busy_mask),
408 	TP_ARGS(drm_id, idx, frame_busy_mask),
409 	TP_STRUCT__entry(
410 		__field(	uint32_t,		drm_id		)
411 		__field(	unsigned int,		idx		)
412 		__field(	unsigned long,		frame_busy_mask	)
413 	),
414 	TP_fast_assign(
415 		__entry->drm_id = drm_id;
416 		__entry->idx = idx;
417 		__entry->frame_busy_mask = frame_busy_mask;
418 	),
419 	TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
420 		  __entry->idx, __entry->frame_busy_mask)
421 );
422 
423 TRACE_EVENT(dpu_enc_trigger_flush,
424 	TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum dpu_wb wb_idx,
425 		 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
426 		 u32 pending_flush_ret),
427 	TP_ARGS(drm_id, intf_mode, intf_idx, wb_idx, pending_kickoff_cnt, ctl_idx,
428 		extra_flush_bits, pending_flush_ret),
429 	TP_STRUCT__entry(
430 		__field(	uint32_t,	drm_id			)
431 		__string(	intf_mode_str,	intf_mode		)
432 		__field(	enum dpu_intf,	intf_idx		)
433 		__field(	enum dpu_wb,	wb_idx			)
434 		__field(	int,		pending_kickoff_cnt	)
435 		__field(	int,		ctl_idx			)
436 		__field(	u32,		extra_flush_bits	)
437 		__field(	u32,		pending_flush_ret	)
438 	),
439 	TP_fast_assign(
440 		__entry->drm_id = drm_id;
441 		__assign_str(intf_mode_str, intf_mode);
442 		__entry->intf_idx = intf_idx;
443 		__entry->wb_idx = wb_idx;
444 		__entry->pending_kickoff_cnt = pending_kickoff_cnt;
445 		__entry->ctl_idx = ctl_idx;
446 		__entry->extra_flush_bits = extra_flush_bits;
447 		__entry->pending_flush_ret = pending_flush_ret;
448 	),
449 	TP_printk("id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
450 		  "extra_flush_bits=0x%x pending_flush_ret=0x%x",
451 		  __entry->drm_id, __get_str(intf_mode_str), __entry->intf_idx, __entry->wb_idx,
452 		  __entry->pending_kickoff_cnt, __entry->ctl_idx,
453 		  __entry->extra_flush_bits, __entry->pending_flush_ret)
454 );
455 
456 DECLARE_EVENT_CLASS(dpu_id_event_template,
457 	TP_PROTO(uint32_t drm_id, u32 event),
458 	TP_ARGS(drm_id, event),
459 	TP_STRUCT__entry(
460 		__field(	uint32_t,	drm_id	)
461 		__field(	u32,		event	)
462 	),
463 	TP_fast_assign(
464 		__entry->drm_id = drm_id;
465 		__entry->event = event;
466 	),
467 	TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
468 );
469 DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
470 	TP_PROTO(uint32_t drm_id, u32 event),
471 	TP_ARGS(drm_id, event)
472 );
473 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
474 	TP_PROTO(uint32_t drm_id, u32 event),
475 	TP_ARGS(drm_id, event)
476 );
477 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
478 	TP_PROTO(uint32_t drm_id, u32 event),
479 	TP_ARGS(drm_id, event)
480 );
481 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
482 	TP_PROTO(uint32_t drm_id, u32 event),
483 	TP_ARGS(drm_id, event)
484 );
485 
486 TRACE_EVENT(dpu_enc_wait_event_timeout,
487 	TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
488 		 s64 expected_time, int atomic_cnt),
489 	TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
490 	TP_STRUCT__entry(
491 		__field(	uint32_t,	drm_id		)
492 		__field(	int,		irq_idx		)
493 		__field(	int,		rc		)
494 		__field(	s64,		time		)
495 		__field(	s64,		expected_time	)
496 		__field(	int,		atomic_cnt	)
497 	),
498 	TP_fast_assign(
499 		__entry->drm_id = drm_id;
500 		__entry->irq_idx = irq_idx;
501 		__entry->rc = rc;
502 		__entry->time = time;
503 		__entry->expected_time = expected_time;
504 		__entry->atomic_cnt = atomic_cnt;
505 	),
506 	TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
507 		  __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
508 		  __entry->expected_time, __entry->atomic_cnt)
509 );
510 
511 TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
512 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
513 		 int refcnt),
514 	TP_ARGS(drm_id, pp, enable, refcnt),
515 	TP_STRUCT__entry(
516 		__field(	uint32_t,		drm_id	)
517 		__field(	enum dpu_pingpong,	pp	)
518 		__field(	bool,			enable	)
519 		__field(	int,			refcnt	)
520 	),
521 	TP_fast_assign(
522 		__entry->drm_id = drm_id;
523 		__entry->pp = pp;
524 		__entry->enable = enable;
525 		__entry->refcnt = refcnt;
526 	),
527 	TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
528 		  __entry->pp, __entry->enable ? "true" : "false",
529 		  __entry->refcnt)
530 );
531 
532 TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
533 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
534 		 u32 event),
535 	TP_ARGS(drm_id, pp, new_count, event),
536 	TP_STRUCT__entry(
537 		__field(	uint32_t,		drm_id		)
538 		__field(	enum dpu_pingpong,	pp		)
539 		__field(	int,			new_count	)
540 		__field(	u32,			event		)
541 	),
542 	TP_fast_assign(
543 		__entry->drm_id = drm_id;
544 		__entry->pp = pp;
545 		__entry->new_count = new_count;
546 		__entry->event = event;
547 	),
548 	TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
549 		  __entry->pp, __entry->new_count, __entry->event)
550 );
551 
552 TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
553 	TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
554 		 int kickoff_count, u32 event),
555 	TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
556 	TP_STRUCT__entry(
557 		__field(	uint32_t,		drm_id		)
558 		__field(	enum dpu_pingpong,	pp		)
559 		__field(	int,			timeout_count	)
560 		__field(	int,			kickoff_count	)
561 		__field(	u32,			event		)
562 	),
563 	TP_fast_assign(
564 		__entry->drm_id = drm_id;
565 		__entry->pp = pp;
566 		__entry->timeout_count = timeout_count;
567 		__entry->kickoff_count = kickoff_count;
568 		__entry->event = event;
569 	),
570 	TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
571 		  __entry->drm_id, __entry->pp, __entry->timeout_count,
572 		  __entry->kickoff_count, __entry->event)
573 );
574 
575 TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
576 	TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
577 	TP_ARGS(drm_id, intf_idx),
578 	TP_STRUCT__entry(
579 		__field(	uint32_t,	drm_id			)
580 		__field(	enum dpu_intf,	intf_idx		)
581 	),
582 	TP_fast_assign(
583 		__entry->drm_id = drm_id;
584 		__entry->intf_idx = intf_idx;
585 	),
586 	TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
587 );
588 
589 TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
590 	TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
591 		 int refcnt),
592 	TP_ARGS(drm_id, intf_idx, enable, refcnt),
593 	TP_STRUCT__entry(
594 		__field(	uint32_t,	drm_id		)
595 		__field(	enum dpu_intf,	intf_idx	)
596 		__field(	bool,		enable		)
597 		__field(	int,		refcnt		)
598 	),
599 	TP_fast_assign(
600 		__entry->drm_id = drm_id;
601 		__entry->intf_idx = intf_idx;
602 		__entry->enable = enable;
603 		__entry->refcnt = refcnt;
604 	),
605 	TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
606 		  __entry->intf_idx, __entry->enable ? "true" : "false",
607 		  __entry->drm_id)
608 );
609 
610 TRACE_EVENT(dpu_crtc_setup_mixer,
611 	TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
612 		 struct drm_plane_state *state, struct dpu_plane_state *pstate,
613 		 uint32_t stage_idx, uint32_t pixel_format,
614 		 uint64_t modifier),
615 	TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
616 		pixel_format, modifier),
617 	TP_STRUCT__entry(
618 		__field(	uint32_t,		crtc_id		)
619 		__field(	uint32_t,		plane_id	)
620 		__field(	uint32_t,		fb_id		)
621 		__field_struct(	struct drm_rect,	src_rect	)
622 		__field_struct(	struct drm_rect,	dst_rect	)
623 		__field(	uint32_t,		stage_idx	)
624 		__field(	enum dpu_stage,		stage		)
625 		__field(	enum dpu_sspp,		sspp		)
626 		__field(	uint32_t,		multirect_idx	)
627 		__field(	uint32_t,		multirect_mode	)
628 		__field(	uint32_t,		pixel_format	)
629 		__field(	uint64_t,		modifier	)
630 	),
631 	TP_fast_assign(
632 		__entry->crtc_id = crtc_id;
633 		__entry->plane_id = plane_id;
634 		__entry->fb_id = state ? state->fb->base.id : 0;
635 		__entry->src_rect = drm_plane_state_src(state);
636 		__entry->dst_rect = drm_plane_state_dest(state);
637 		__entry->stage_idx = stage_idx;
638 		__entry->stage = pstate->stage;
639 		__entry->sspp = pstate->pipe.sspp->idx;
640 		__entry->multirect_idx = pstate->pipe.multirect_index;
641 		__entry->multirect_mode = pstate->pipe.multirect_mode;
642 		__entry->pixel_format = pixel_format;
643 		__entry->modifier = modifier;
644 	),
645 	TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
646 		  " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
647 		  "multirect_index:%d multirect_mode:%u pix_format:%u "
648 		  "modifier:%llu",
649 		  __entry->crtc_id, __entry->plane_id, __entry->fb_id,
650 		  DRM_RECT_FP_ARG(&__entry->src_rect),
651 		  DRM_RECT_ARG(&__entry->dst_rect),
652 		  __entry->stage_idx, __entry->stage, __entry->sspp,
653 		  __entry->multirect_idx, __entry->multirect_mode,
654 		  __entry->pixel_format, __entry->modifier)
655 );
656 
657 TRACE_EVENT(dpu_crtc_setup_lm_bounds,
658 	TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
659 	TP_ARGS(drm_id, mixer, bounds),
660 	TP_STRUCT__entry(
661 		__field(	uint32_t,		drm_id	)
662 		__field(	int,			mixer	)
663 		__field_struct(	struct drm_rect,	bounds	)
664 	),
665 	TP_fast_assign(
666 		__entry->drm_id = drm_id;
667 		__entry->mixer = mixer;
668 		__entry->bounds = *bounds;
669 	),
670 	TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
671 		  __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
672 );
673 
674 TRACE_EVENT(dpu_crtc_vblank_enable,
675 	TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
676 		 struct dpu_crtc *crtc),
677 	TP_ARGS(drm_id, enc_id, enable, crtc),
678 	TP_STRUCT__entry(
679 		__field(	uint32_t,		drm_id	)
680 		__field(	uint32_t,		enc_id	)
681 		__field(	bool,			enable	)
682 		__field(	bool,			enabled )
683 	),
684 	TP_fast_assign(
685 		__entry->drm_id = drm_id;
686 		__entry->enc_id = enc_id;
687 		__entry->enable = enable;
688 		__entry->enabled = crtc->enabled;
689 	),
690 	TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
691 		  __entry->drm_id, __entry->enc_id,
692 		  __entry->enable ? "true" : "false",
693 		  __entry->enabled ? "true" : "false")
694 );
695 
696 DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
697 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
698 	TP_ARGS(drm_id, enable, crtc),
699 	TP_STRUCT__entry(
700 		__field(	uint32_t,		drm_id	)
701 		__field(	bool,			enable	)
702 		__field(	bool,			enabled )
703 	),
704 	TP_fast_assign(
705 		__entry->drm_id = drm_id;
706 		__entry->enable = enable;
707 		__entry->enabled = crtc->enabled;
708 	),
709 	TP_printk("id:%u enable:%s state{enabled:%s}",
710 		  __entry->drm_id, __entry->enable ? "true" : "false",
711 		  __entry->enabled ? "true" : "false")
712 );
713 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
714 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
715 	TP_ARGS(drm_id, enable, crtc)
716 );
717 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
718 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
719 	TP_ARGS(drm_id, enable, crtc)
720 );
721 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
722 	TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
723 	TP_ARGS(drm_id, enable, crtc)
724 );
725 
726 TRACE_EVENT(dpu_crtc_disable_frame_pending,
727 	TP_PROTO(uint32_t drm_id, int frame_pending),
728 	TP_ARGS(drm_id, frame_pending),
729 	TP_STRUCT__entry(
730 		__field(	uint32_t,		drm_id		)
731 		__field(	int,			frame_pending	)
732 	),
733 	TP_fast_assign(
734 		__entry->drm_id = drm_id;
735 		__entry->frame_pending = frame_pending;
736 	),
737 	TP_printk("id:%u frame_pending:%d", __entry->drm_id,
738 		  __entry->frame_pending)
739 );
740 
741 TRACE_EVENT(dpu_plane_set_scanout,
742 	TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout),
743 	TP_ARGS(pipe, layout),
744 	TP_STRUCT__entry(
745 		__field(	enum dpu_sspp,			index	)
746 		__field_struct(	struct dpu_hw_fmt_layout,	layout	)
747 		__field(	enum dpu_sspp_multirect_index,	multirect_index)
748 	),
749 	TP_fast_assign(
750 		__entry->index = pipe->sspp->idx;
751 		__entry->layout = *layout;
752 		__entry->multirect_index = pipe->multirect_index;
753 	),
754 	TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
755 		  "multirect_index:%d", __entry->index, __entry->layout.width,
756 		  __entry->layout.height, __entry->layout.plane_addr[0],
757 		  __entry->layout.plane_size[0],
758 		  __entry->layout.plane_addr[1],
759 		  __entry->layout.plane_size[1],
760 		  __entry->layout.plane_addr[2],
761 		  __entry->layout.plane_size[2],
762 		  __entry->layout.plane_addr[3],
763 		  __entry->layout.plane_size[3], __entry->multirect_index)
764 );
765 
766 TRACE_EVENT(dpu_plane_disable,
767 	TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
768 	TP_ARGS(drm_id, is_virtual, multirect_mode),
769 	TP_STRUCT__entry(
770 		__field(	uint32_t,		drm_id		)
771 		__field(	bool,			is_virtual	)
772 		__field(	uint32_t,		multirect_mode	)
773 	),
774 	TP_fast_assign(
775 		__entry->drm_id = drm_id;
776 		__entry->is_virtual = is_virtual;
777 		__entry->multirect_mode = multirect_mode;
778 	),
779 	TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
780 		  __entry->is_virtual ? "true" : "false",
781 		  __entry->multirect_mode)
782 );
783 
784 DECLARE_EVENT_CLASS(dpu_rm_iter_template,
785 	TP_PROTO(uint32_t id, uint32_t enc_id),
786 	TP_ARGS(id, enc_id),
787 	TP_STRUCT__entry(
788 		__field(	uint32_t,		id	)
789 		__field(	uint32_t,		enc_id	)
790 	),
791 	TP_fast_assign(
792 		__entry->id = id;
793 		__entry->enc_id = enc_id;
794 	),
795 	TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
796 );
797 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
798 	TP_PROTO(uint32_t id, uint32_t enc_id),
799 	TP_ARGS(id, enc_id)
800 );
801 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
802 	TP_PROTO(uint32_t id, uint32_t enc_id),
803 	TP_ARGS(id, enc_id)
804 );
805 
806 TRACE_EVENT(dpu_rm_reserve_lms,
807 	TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
808 	TP_ARGS(id, enc_id, pp_id),
809 	TP_STRUCT__entry(
810 		__field(	uint32_t,		id	)
811 		__field(	uint32_t,		enc_id	)
812 		__field(	uint32_t,		pp_id	)
813 	),
814 	TP_fast_assign(
815 		__entry->id = id;
816 		__entry->enc_id = enc_id;
817 		__entry->pp_id = pp_id;
818 	),
819 	TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
820 		  __entry->enc_id, __entry->pp_id)
821 );
822 
823 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
824 	TP_PROTO(enum dpu_vbif index, u32 xin_id),
825 	TP_ARGS(index, xin_id),
826 	TP_STRUCT__entry(
827 		__field(	enum dpu_vbif,	index	)
828 		__field(	u32,		xin_id	)
829 	),
830 	TP_fast_assign(
831 		__entry->index = index;
832 		__entry->xin_id = xin_id;
833 	),
834 	TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
835 );
836 
837 TRACE_EVENT(dpu_pp_connect_ext_te,
838 	TP_PROTO(enum dpu_pingpong pp, u32 cfg),
839 	TP_ARGS(pp, cfg),
840 	TP_STRUCT__entry(
841 		__field(	enum dpu_pingpong,	pp	)
842 		__field(	u32,			cfg	)
843 	),
844 	TP_fast_assign(
845 		__entry->pp = pp;
846 		__entry->cfg = cfg;
847 	),
848 	TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
849 );
850 
851 TRACE_EVENT(dpu_intf_connect_ext_te,
852 	TP_PROTO(enum dpu_intf intf, u32 cfg),
853 	TP_ARGS(intf, cfg),
854 	TP_STRUCT__entry(
855 		__field(	enum dpu_intf,	intf	)
856 		__field(	u32,			cfg	)
857 	),
858 	TP_fast_assign(
859 		__entry->intf = intf;
860 		__entry->cfg = cfg;
861 	),
862 	TP_printk("intf:%d cfg:%u", __entry->intf, __entry->cfg)
863 );
864 
865 TRACE_EVENT(dpu_core_irq_register_callback,
866 	TP_PROTO(int irq_idx, void *callback),
867 	TP_ARGS(irq_idx, callback),
868 	TP_STRUCT__entry(
869 		__field(	int,				irq_idx	)
870 		__field(	void *,				callback)
871 	),
872 	TP_fast_assign(
873 		__entry->irq_idx = irq_idx;
874 		__entry->callback = callback;
875 	),
876 	TP_printk("irq_idx:%d callback:%ps", __entry->irq_idx,
877 		  __entry->callback)
878 );
879 
880 TRACE_EVENT(dpu_core_irq_unregister_callback,
881 	TP_PROTO(int irq_idx),
882 	TP_ARGS(irq_idx),
883 	TP_STRUCT__entry(
884 		__field(	int,				irq_idx	)
885 	),
886 	TP_fast_assign(
887 		__entry->irq_idx = irq_idx;
888 	),
889 	TP_printk("irq_idx:%d", __entry->irq_idx)
890 );
891 
892 TRACE_EVENT(dpu_core_perf_update_clk,
893 	TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
894 	TP_ARGS(dev, stop_req, clk_rate),
895 	TP_STRUCT__entry(
896 		__string(	dev_name,		dev->unique	)
897 		__field(	bool,			stop_req	)
898 		__field(	u64,			clk_rate	)
899 	),
900 	TP_fast_assign(
901 		__assign_str(dev_name, dev->unique);
902 		__entry->stop_req = stop_req;
903 		__entry->clk_rate = clk_rate;
904 	),
905 	TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
906 		  __entry->stop_req ? "true" : "false", __entry->clk_rate)
907 );
908 
909 TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
910 	TP_PROTO(u32 new_bits, u32 pending_mask),
911 	TP_ARGS(new_bits, pending_mask),
912 	TP_STRUCT__entry(
913 		__field(	u32,			new_bits	)
914 		__field(	u32,			pending_mask	)
915 	),
916 	TP_fast_assign(
917 		__entry->new_bits = new_bits;
918 		__entry->pending_mask = pending_mask;
919 	),
920 	TP_printk("new=%x existing=%x", __entry->new_bits,
921 		  __entry->pending_mask)
922 );
923 
924 DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
925 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
926 	TP_ARGS(pending_mask, ctl_flush),
927 	TP_STRUCT__entry(
928 		__field(	u32,			pending_mask	)
929 		__field(	u32,			ctl_flush	)
930 	),
931 	TP_fast_assign(
932 		__entry->pending_mask = pending_mask;
933 		__entry->ctl_flush = ctl_flush;
934 	),
935 	TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
936 		  __entry->ctl_flush)
937 );
938 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
939 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
940 	TP_ARGS(pending_mask, ctl_flush)
941 );
942 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
943 	     dpu_hw_ctl_trigger_pending_flush,
944 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
945 	TP_ARGS(pending_mask, ctl_flush)
946 );
947 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
948 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
949 	TP_ARGS(pending_mask, ctl_flush)
950 );
951 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
952 	TP_PROTO(u32 pending_mask, u32 ctl_flush),
953 	TP_ARGS(pending_mask, ctl_flush)
954 );
955 
956 #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
957 #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
958 #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
959 
960 #define DPU_ATRACE_INT(name, value) \
961 	trace_dpu_trace_counter(current->tgid, name, value)
962 
963 #endif /* _DPU_TRACE_H_ */
964 
965 /* This part must be outside protection */
966 #undef TRACE_INCLUDE_PATH
967 #define TRACE_INCLUDE_PATH .
968 #include <trace/define_trace.h>
969