1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * DWMAC4 DMA Header file.
4 *
5 * Copyright (C) 2007-2015 STMicroelectronics Ltd
6 *
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 */
9
10 #ifndef __DWMAC4_DMA_H__
11 #define __DWMAC4_DMA_H__
12
13 /* Define the max channel number used for tx (also rx).
14 * dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
15 */
16 #define DMA_CHANNEL_NB_MAX 1
17
18 #define DMA_BUS_MODE 0x00001000
19 #define DMA_SYS_BUS_MODE 0x00001004
20 #define DMA_STATUS 0x00001008
21 #define DMA_DEBUG_STATUS_0 0x0000100c
22 #define DMA_DEBUG_STATUS_1 0x00001010
23 #define DMA_DEBUG_STATUS_2 0x00001014
24 #define DMA_AXI_BUS_MODE 0x00001028
25 #define DMA_TBS_CTRL 0x00001050
26
27 /* DMA Bus Mode bitmap */
28 #define DMA_BUS_MODE_DCHE BIT(19)
29 #define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
30 #define DMA_BUS_MODE_INTM_SHIFT 16
31 #define DMA_BUS_MODE_INTM_MODE1 0x1
32 #define DMA_BUS_MODE_SFT_RESET BIT(0)
33
34 /* DMA SYS Bus Mode bitmap */
35 #define DMA_BUS_MODE_SPH BIT(24)
36 #define DMA_BUS_MODE_PBL BIT(16)
37 #define DMA_BUS_MODE_PBL_SHIFT 16
38 #define DMA_BUS_MODE_RPBL_SHIFT 16
39 #define DMA_BUS_MODE_MB BIT(14)
40 #define DMA_BUS_MODE_FB BIT(0)
41
42 /* DMA Interrupt top status */
43 #define DMA_STATUS_MAC BIT(17)
44 #define DMA_STATUS_MTL BIT(16)
45 #define DMA_STATUS_CHAN7 BIT(7)
46 #define DMA_STATUS_CHAN6 BIT(6)
47 #define DMA_STATUS_CHAN5 BIT(5)
48 #define DMA_STATUS_CHAN4 BIT(4)
49 #define DMA_STATUS_CHAN3 BIT(3)
50 #define DMA_STATUS_CHAN2 BIT(2)
51 #define DMA_STATUS_CHAN1 BIT(1)
52 #define DMA_STATUS_CHAN0 BIT(0)
53
54 /* DMA debug status bitmap */
55 #define DMA_DEBUG_STATUS_TS_MASK 0xf
56 #define DMA_DEBUG_STATUS_RS_MASK 0xf
57
58 /* DMA AXI bitmap */
59 #define DMA_AXI_EN_LPI BIT(31)
60 #define DMA_AXI_LPI_XIT_FRM BIT(30)
61 #define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
62 #define DMA_AXI_WR_OSR_LMT_SHIFT 24
63 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
64 #define DMA_AXI_RD_OSR_LMT_SHIFT 16
65
66 #define DMA_AXI_OSR_MAX 0xf
67 #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
68 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
69
70 #define DMA_SYS_BUS_MB BIT(14)
71 #define DMA_AXI_1KBBE BIT(13)
72 #define DMA_SYS_BUS_AAL BIT(12)
73 #define DMA_SYS_BUS_EAME BIT(11)
74 #define DMA_AXI_BLEN256 BIT(7)
75 #define DMA_AXI_BLEN128 BIT(6)
76 #define DMA_AXI_BLEN64 BIT(5)
77 #define DMA_AXI_BLEN32 BIT(4)
78 #define DMA_AXI_BLEN16 BIT(3)
79 #define DMA_AXI_BLEN8 BIT(2)
80 #define DMA_AXI_BLEN4 BIT(1)
81 #define DMA_SYS_BUS_FB BIT(0)
82
83 #define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
84 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
85 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
86 DMA_AXI_BLEN4)
87
88 #define DMA_AXI_BURST_LEN_MASK 0x000000FE
89
90 /* DMA TBS Control */
91 #define DMA_TBS_FTOS GENMASK(31, 8)
92 #define DMA_TBS_FTOV BIT(0)
93 #define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
94
95 /* Following DMA defines are chanels oriented */
96 #define DMA_CHAN_BASE_ADDR 0x00001100
97 #define DMA_CHAN_BASE_OFFSET 0x80
98
dma_chanx_base_addr(const struct dwmac4_addrs * addrs,const u32 x)99 static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
100 const u32 x)
101 {
102 u32 addr;
103
104 if (addrs)
105 addr = addrs->dma_chan + (x * addrs->dma_chan_offset);
106 else
107 addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET);
108
109 return addr;
110 }
111
112 #define DMA_CHAN_REG_NUMBER 17
113
114 #define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
115 #define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
116 #define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8)
117 #define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10)
118 #define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14)
119 #define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18)
120 #define DMA_CHAN_RX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x1c)
121 #define DMA_CHAN_TX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x20)
122 #define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28)
123 #define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c)
124 #define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30)
125 #define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34)
126 #define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
127 #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
128 #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
129 #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c)
130 #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54)
131 #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c)
132 #define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60)
133
134 /* DMA Control X */
135 #define DMA_CONTROL_SPH BIT(24)
136 #define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
137
138 /* DMA Tx Channel X Control register defines */
139 #define DMA_CONTROL_EDSE BIT(28)
140 #define DMA_CONTROL_TSE BIT(12)
141 #define DMA_CONTROL_OSP BIT(4)
142 #define DMA_CONTROL_ST BIT(0)
143
144 /* DMA Rx Channel X Control register defines */
145 #define DMA_CONTROL_SR BIT(0)
146 #define DMA_RBSZ_MASK GENMASK(14, 1)
147 #define DMA_RBSZ_SHIFT 1
148
149 /* Interrupt status per channel */
150 #define DMA_CHAN_STATUS_REB GENMASK(21, 19)
151 #define DMA_CHAN_STATUS_REB_SHIFT 19
152 #define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
153 #define DMA_CHAN_STATUS_TEB_SHIFT 16
154 #define DMA_CHAN_STATUS_NIS BIT(15)
155 #define DMA_CHAN_STATUS_AIS BIT(14)
156 #define DMA_CHAN_STATUS_CDE BIT(13)
157 #define DMA_CHAN_STATUS_FBE BIT(12)
158 #define DMA_CHAN_STATUS_ERI BIT(11)
159 #define DMA_CHAN_STATUS_ETI BIT(10)
160 #define DMA_CHAN_STATUS_RWT BIT(9)
161 #define DMA_CHAN_STATUS_RPS BIT(8)
162 #define DMA_CHAN_STATUS_RBU BIT(7)
163 #define DMA_CHAN_STATUS_RI BIT(6)
164 #define DMA_CHAN_STATUS_TBU BIT(2)
165 #define DMA_CHAN_STATUS_TPS BIT(1)
166 #define DMA_CHAN_STATUS_TI BIT(0)
167
168 #define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \
169 DMA_CHAN_STATUS_AIS | \
170 DMA_CHAN_STATUS_CDE | \
171 DMA_CHAN_STATUS_FBE)
172
173 #define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \
174 DMA_CHAN_STATUS_ERI | \
175 DMA_CHAN_STATUS_RWT | \
176 DMA_CHAN_STATUS_RPS | \
177 DMA_CHAN_STATUS_RBU | \
178 DMA_CHAN_STATUS_RI | \
179 DMA_CHAN_STATUS_MSK_COMMON)
180
181 #define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \
182 DMA_CHAN_STATUS_TBU | \
183 DMA_CHAN_STATUS_TPS | \
184 DMA_CHAN_STATUS_TI | \
185 DMA_CHAN_STATUS_MSK_COMMON)
186
187 /* Interrupt enable bits per channel */
188 #define DMA_CHAN_INTR_ENA_NIE BIT(16)
189 #define DMA_CHAN_INTR_ENA_AIE BIT(15)
190 #define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
191 #define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
192 #define DMA_CHAN_INTR_ENA_CDE BIT(13)
193 #define DMA_CHAN_INTR_ENA_FBE BIT(12)
194 #define DMA_CHAN_INTR_ENA_ERE BIT(11)
195 #define DMA_CHAN_INTR_ENA_ETE BIT(10)
196 #define DMA_CHAN_INTR_ENA_RWE BIT(9)
197 #define DMA_CHAN_INTR_ENA_RSE BIT(8)
198 #define DMA_CHAN_INTR_ENA_RBUE BIT(7)
199 #define DMA_CHAN_INTR_ENA_RIE BIT(6)
200 #define DMA_CHAN_INTR_ENA_TBUE BIT(2)
201 #define DMA_CHAN_INTR_ENA_TSE BIT(1)
202 #define DMA_CHAN_INTR_ENA_TIE BIT(0)
203
204 #define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
205 DMA_CHAN_INTR_ENA_RIE | \
206 DMA_CHAN_INTR_ENA_TIE)
207
208 #define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
209 DMA_CHAN_INTR_ENA_FBE)
210 /* DMA default interrupt mask for 4.00 */
211 #define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
212 DMA_CHAN_INTR_ABNORMAL)
213 #define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
214 #define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
215
216 #define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
217 DMA_CHAN_INTR_ENA_RIE | \
218 DMA_CHAN_INTR_ENA_TIE)
219
220 #define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
221 DMA_CHAN_INTR_ENA_FBE)
222 /* DMA default interrupt mask for 4.10a */
223 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
224 DMA_CHAN_INTR_ABNORMAL_4_10)
225 #define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
226 #define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
227
228 /* channel 0 specific fields */
229 #define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
230 #define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
231 #define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
232 #define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
233
234 int dwmac4_dma_reset(void __iomem *ioaddr);
235 void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
236 u32 chan, bool rx, bool tx);
237 void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
238 u32 chan, bool rx, bool tx);
239 void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
240 u32 chan, bool rx, bool tx);
241 void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
242 u32 chan, bool rx, bool tx);
243 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
244 u32 chan);
245 void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
246 u32 chan);
247 void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
248 u32 chan);
249 void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
250 u32 chan);
251 int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
252 struct stmmac_extra_stats *x, u32 chan, u32 dir);
253 void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
254 u32 len, u32 chan);
255 void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
256 u32 len, u32 chan);
257 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
258 u32 tail_ptr, u32 chan);
259 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
260 u32 tail_ptr, u32 chan);
261
262 #endif /* __DWMAC4_DMA_H__ */
263