1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_HW_TYPES_H
27 #define DC_HW_TYPES_H
28 
29 #include "os_types.h"
30 #include "fixed31_32.h"
31 #include "signal_types.h"
32 
33 /******************************************************************************
34  * Data types for Virtual HW Layer of DAL3.
35  * (see DAL3 design documents for HW Layer definition)
36  *
37  * The intended uses are:
38  * 1. Generation pseudocode sequences for HW programming.
39  * 2. Implementation of real HW programming by HW Sequencer of DAL3.
40  *
41  * Note: do *not* add any types which are *not* used for HW programming - this
42  * will ensure separation of Logic layer from HW layer.
43  ******************************************************************************/
44 
45 union large_integer {
46 	struct {
47 		uint32_t low_part;
48 		int32_t high_part;
49 	};
50 
51 	struct {
52 		uint32_t low_part;
53 		int32_t high_part;
54 	} u;
55 
56 	int64_t quad_part;
57 };
58 
59 #define PHYSICAL_ADDRESS_LOC union large_integer
60 
61 enum dc_plane_addr_type {
62 	PLN_ADDR_TYPE_GRAPHICS = 0,
63 	PLN_ADDR_TYPE_GRPH_STEREO,
64 	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
65 	PLN_ADDR_TYPE_RGBEA
66 };
67 
68 struct dc_plane_address {
69 	enum dc_plane_addr_type type;
70 	bool tmz_surface;
71 	union {
72 		struct{
73 			PHYSICAL_ADDRESS_LOC addr;
74 			PHYSICAL_ADDRESS_LOC cursor_cache_addr;
75 			PHYSICAL_ADDRESS_LOC meta_addr;
76 			union large_integer dcc_const_color;
77 		} grph;
78 
79 		/*stereo*/
80 		struct {
81 			PHYSICAL_ADDRESS_LOC left_addr;
82 			PHYSICAL_ADDRESS_LOC left_meta_addr;
83 			union large_integer left_dcc_const_color;
84 
85 			PHYSICAL_ADDRESS_LOC right_addr;
86 			PHYSICAL_ADDRESS_LOC right_meta_addr;
87 			union large_integer right_dcc_const_color;
88 
89 			PHYSICAL_ADDRESS_LOC left_alpha_addr;
90 			PHYSICAL_ADDRESS_LOC left_alpha_meta_addr;
91 			union large_integer left_alpha_dcc_const_color;
92 
93 			PHYSICAL_ADDRESS_LOC right_alpha_addr;
94 			PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;
95 			union large_integer right_alpha_dcc_const_color;
96 
97 		} grph_stereo;
98 
99 		/*video  progressive*/
100 		struct {
101 			PHYSICAL_ADDRESS_LOC luma_addr;
102 			PHYSICAL_ADDRESS_LOC luma_meta_addr;
103 			union large_integer luma_dcc_const_color;
104 
105 			PHYSICAL_ADDRESS_LOC chroma_addr;
106 			PHYSICAL_ADDRESS_LOC chroma_meta_addr;
107 			union large_integer chroma_dcc_const_color;
108 		} video_progressive;
109 
110 		struct {
111 			PHYSICAL_ADDRESS_LOC addr;
112 			PHYSICAL_ADDRESS_LOC meta_addr;
113 			union large_integer dcc_const_color;
114 
115 			PHYSICAL_ADDRESS_LOC alpha_addr;
116 			PHYSICAL_ADDRESS_LOC alpha_meta_addr;
117 			union large_integer alpha_dcc_const_color;
118 		} rgbea;
119 	};
120 
121 	union large_integer page_table_base;
122 
123 	uint8_t vmid;
124 };
125 
126 struct dc_size {
127 	int width;
128 	int height;
129 };
130 
131 struct rect {
132 	int x;
133 	int y;
134 	int width;
135 	int height;
136 };
137 
138 struct plane_size {
139 	/* Graphic surface pitch in pixels.
140 	 * In LINEAR_GENERAL mode, pitch
141 	 * is 32 pixel aligned.
142 	 */
143 	int surface_pitch;
144 	int chroma_pitch;
145 	struct rect surface_size;
146 	struct rect chroma_size;
147 };
148 
149 struct dc_plane_dcc_param {
150 	bool enable;
151 
152 	int meta_pitch;
153 	bool independent_64b_blks;
154 	uint8_t dcc_ind_blk;
155 
156 	int meta_pitch_c;
157 	bool independent_64b_blks_c;
158 	uint8_t dcc_ind_blk_c;
159 };
160 
161 /*Displayable pixel format in fb*/
162 enum surface_pixel_format {
163 	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
164 	/*TOBE REMOVED paletta 256 colors*/
165 	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
166 		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
167 	/*16 bpp*/
168 	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
169 	/*16 bpp*/
170 	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
171 	/*32 bpp*/
172 	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
173 	/*32 bpp swaped*/
174 	SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
175 
176 	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
177 	/*swaped*/
178 	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
179 	/*TOBE REMOVED swaped, XR_BIAS has no differance
180 	 * for pixel layout than previous and we can
181 	 * delete this after discusion*/
182 	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
183 	/*64 bpp */
184 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
185 	/*swapped*/
186 	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616,
187 	/*float*/
188 	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
189 	/*swaped & float*/
190 	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
191 	/*grow graphics here if necessary */
192 	SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
193 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
194 	SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
195 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
196 	SURFACE_PIXEL_FORMAT_GRPH_RGBE,
197 	SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA,
198 	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
199 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
200 		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
201 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
202 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
203 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
204 	SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
205 	SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 =
206 		SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
207 	SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
208 	SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
209 	SURFACE_PIXEL_FORMAT_INVALID
210 
211 	/*grow 444 video here if necessary */
212 };
213 
214 
215 
216 /* Pixel format */
217 enum pixel_format {
218 	/*graph*/
219 	PIXEL_FORMAT_UNINITIALIZED,
220 	PIXEL_FORMAT_INDEX8,
221 	PIXEL_FORMAT_RGB565,
222 	PIXEL_FORMAT_ARGB8888,
223 	PIXEL_FORMAT_ARGB2101010,
224 	PIXEL_FORMAT_ARGB2101010_XRBIAS,
225 	PIXEL_FORMAT_FP16,
226 	/*video*/
227 	PIXEL_FORMAT_420BPP8,
228 	PIXEL_FORMAT_420BPP10,
229 	/*end of pixel format definition*/
230 	PIXEL_FORMAT_INVALID,
231 
232 	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
233 	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
234 	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
235 	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
236 	PIXEL_FORMAT_UNKNOWN
237 };
238 
239 /*
240  * This structure holds a surface address.  There could be multiple addresses
241  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
242  * as frame durations and DCC format can also be set.
243  */
244 #define DC_MAX_DIRTY_RECTS 3
245 struct dc_flip_addrs {
246 	struct dc_plane_address address;
247 	unsigned long long flip_timestamp_in_us;
248 	bool flip_immediate;
249 	/* TODO: add flip duration for FreeSync */
250 	bool triplebuffer_flips;
251 	unsigned int dirty_rect_count;
252 	struct rect dirty_rects[DC_MAX_DIRTY_RECTS];
253 };
254 
255 enum tile_split_values {
256 	DC_DISPLAY_MICRO_TILING = 0x0,
257 	DC_THIN_MICRO_TILING = 0x1,
258 	DC_DEPTH_MICRO_TILING = 0x2,
259 	DC_ROTATED_MICRO_TILING = 0x3,
260 };
261 
262 enum tripleBuffer_enable {
263 	DC_TRIPLEBUFFER_DISABLE = 0x0,
264 	DC_TRIPLEBUFFER_ENABLE = 0x1,
265 };
266 
267 /* TODO: These values come from hardware spec. We need to readdress this
268  * if they ever change.
269  */
270 enum array_mode_values {
271 	DC_ARRAY_LINEAR_GENERAL = 0,
272 	DC_ARRAY_LINEAR_ALLIGNED,
273 	DC_ARRAY_1D_TILED_THIN1,
274 	DC_ARRAY_1D_TILED_THICK,
275 	DC_ARRAY_2D_TILED_THIN1,
276 	DC_ARRAY_PRT_TILED_THIN1,
277 	DC_ARRAY_PRT_2D_TILED_THIN1,
278 	DC_ARRAY_2D_TILED_THICK,
279 	DC_ARRAY_2D_TILED_X_THICK,
280 	DC_ARRAY_PRT_TILED_THICK,
281 	DC_ARRAY_PRT_2D_TILED_THICK,
282 	DC_ARRAY_PRT_3D_TILED_THIN1,
283 	DC_ARRAY_3D_TILED_THIN1,
284 	DC_ARRAY_3D_TILED_THICK,
285 	DC_ARRAY_3D_TILED_X_THICK,
286 	DC_ARRAY_PRT_3D_TILED_THICK,
287 };
288 
289 enum tile_mode_values {
290 	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
291 	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
292 };
293 
294 enum swizzle_mode_values {
295 	DC_SW_LINEAR = 0,
296 	DC_SW_256B_S = 1,
297 	DC_SW_256_D = 2,
298 	DC_SW_256_R = 3,
299 	DC_SW_4KB_S = 5,
300 	DC_SW_4KB_D = 6,
301 	DC_SW_4KB_R = 7,
302 	DC_SW_64KB_S = 9,
303 	DC_SW_64KB_D = 10,
304 	DC_SW_64KB_R = 11,
305 	DC_SW_VAR_S = 13,
306 	DC_SW_VAR_D = 14,
307 	DC_SW_VAR_R = 15,
308 	DC_SW_64KB_S_T = 17,
309 	DC_SW_64KB_D_T = 18,
310 	DC_SW_4KB_S_X = 21,
311 	DC_SW_4KB_D_X = 22,
312 	DC_SW_4KB_R_X = 23,
313 	DC_SW_64KB_S_X = 25,
314 	DC_SW_64KB_D_X = 26,
315 	DC_SW_64KB_R_X = 27,
316 	DC_SW_VAR_S_X = 29,
317 	DC_SW_VAR_D_X = 30,
318 	DC_SW_VAR_R_X = 31,
319 	DC_SW_MAX = 32,
320 	DC_SW_UNKNOWN = DC_SW_MAX
321 };
322 
323 union dc_tiling_info {
324 
325 	struct {
326 		/* Specifies the number of memory banks for tiling
327 		 *	purposes.
328 		 * Only applies to 2D and 3D tiling modes.
329 		 *	POSSIBLE VALUES: 2,4,8,16
330 		 */
331 		unsigned int num_banks;
332 		/* Specifies the number of tiles in the x direction
333 		 *	to be incorporated into the same bank.
334 		 * Only applies to 2D and 3D tiling modes.
335 		 *	POSSIBLE VALUES: 1,2,4,8
336 		 */
337 		unsigned int bank_width;
338 		unsigned int bank_width_c;
339 		/* Specifies the number of tiles in the y direction to
340 		 *	be incorporated into the same bank.
341 		 * Only applies to 2D and 3D tiling modes.
342 		 *	POSSIBLE VALUES: 1,2,4,8
343 		 */
344 		unsigned int bank_height;
345 		unsigned int bank_height_c;
346 		/* Specifies the macro tile aspect ratio. Only applies
347 		 * to 2D and 3D tiling modes.
348 		 */
349 		unsigned int tile_aspect;
350 		unsigned int tile_aspect_c;
351 		/* Specifies the number of bytes that will be stored
352 		 *	contiguously for each tile.
353 		 * If the tile data requires more storage than this
354 		 *	amount, it is split into multiple slices.
355 		 * This field must not be larger than
356 		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
357 		 * Only applies to 2D and 3D tiling modes.
358 		 * For color render targets, TILE_SPLIT >= 256B.
359 		 */
360 		enum tile_split_values tile_split;
361 		enum tile_split_values tile_split_c;
362 		/* Specifies the addressing within a tile.
363 		 *	0x0 - DISPLAY_MICRO_TILING
364 		 *	0x1 - THIN_MICRO_TILING
365 		 *	0x2 - DEPTH_MICRO_TILING
366 		 *	0x3 - ROTATED_MICRO_TILING
367 		 */
368 		enum tile_mode_values tile_mode;
369 		enum tile_mode_values tile_mode_c;
370 		/* Specifies the number of pipes and how they are
371 		 *	interleaved in the surface.
372 		 * Refer to memory addressing document for complete
373 		 *	details and constraints.
374 		 */
375 		unsigned int pipe_config;
376 		/* Specifies the tiling mode of the surface.
377 		 * THIN tiles use an 8x8x1 tile size.
378 		 * THICK tiles use an 8x8x4 tile size.
379 		 * 2D tiling modes rotate banks for successive Z slices
380 		 * 3D tiling modes rotate pipes and banks for Z slices
381 		 * Refer to memory addressing document for complete
382 		 *	details and constraints.
383 		 */
384 		enum array_mode_values array_mode;
385 	} gfx8;
386 
387 	struct {
388 		enum swizzle_mode_values swizzle;
389 		unsigned int num_pipes;
390 		unsigned int max_compressed_frags;
391 		unsigned int pipe_interleave;
392 
393 		unsigned int num_banks;
394 		unsigned int num_shader_engines;
395 		unsigned int num_rb_per_se;
396 		bool shaderEnable;
397 
398 		bool meta_linear;
399 		bool rb_aligned;
400 		bool pipe_aligned;
401 		unsigned int num_pkrs;
402 	} gfx9;
403 };
404 
405 /* Rotation angle */
406 enum dc_rotation_angle {
407 	ROTATION_ANGLE_0 = 0,
408 	ROTATION_ANGLE_90,
409 	ROTATION_ANGLE_180,
410 	ROTATION_ANGLE_270,
411 	ROTATION_ANGLE_COUNT
412 };
413 
414 enum dc_scan_direction {
415 	SCAN_DIRECTION_UNKNOWN = 0,
416 	SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
417 	SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
418 };
419 
420 /**
421  * struct dc_cursor_position: Hardware cursor data.
422  *
423  * This struct keeps the action information related to the cursor that will be
424  * sent and received from our DC core.
425  */
426 struct dc_cursor_position {
427 	/**
428 	 * @x: It represents the top left abscissa coordinate of the cursor.
429 	 */
430 	uint32_t x;
431 
432 	/**
433 	 * @y: It is the top ordinate of the cursor coordinate.
434 	 */
435 	uint32_t y;
436 
437 	/**
438 	 * @x_hotspot: Define the abscissa point where mouse click happens.
439 	 */
440 	uint32_t x_hotspot;
441 
442 	/**
443 	 * @y_hotspot: Define the ordinate point where mouse click happens.
444 	 */
445 	uint32_t y_hotspot;
446 
447 	/**
448 	 * @enable: This parameter indicates whether hardware cursor should be
449 	 * enabled.
450 	 */
451 	bool enable;
452 
453 	/**
454 	 * @translate_by_source: Translate cursor x/y by the source rectangle
455 	 * for each plane.
456 	 */
457 	bool translate_by_source;
458 };
459 
460 struct dc_cursor_mi_param {
461 	unsigned int pixel_clk_khz;
462 	unsigned int ref_clk_khz;
463 	struct rect viewport;
464 	struct fixed31_32 h_scale_ratio;
465 	struct fixed31_32 v_scale_ratio;
466 	enum dc_rotation_angle rotation;
467 	bool mirror;
468 	struct dc_stream_state *stream;
469 };
470 
471 /* IPP related types */
472 
473 enum {
474 	GAMMA_RGB_256_ENTRIES = 256,
475 	GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
476 	GAMMA_CS_TFM_1D_ENTRIES = 4096,
477 	GAMMA_CUSTOM_ENTRIES = 4096,
478 	GAMMA_MAX_ENTRIES = 4096
479 };
480 
481 enum dc_gamma_type {
482 	GAMMA_RGB_256 = 1,
483 	GAMMA_RGB_FLOAT_1024 = 2,
484 	GAMMA_CS_TFM_1D = 3,
485 	GAMMA_CUSTOM = 4,
486 };
487 
488 struct dc_csc_transform {
489 	uint16_t matrix[12];
490 	bool enable_adjustment;
491 };
492 
493 struct dc_rgb_fixed {
494 	struct fixed31_32 red;
495 	struct fixed31_32 green;
496 	struct fixed31_32 blue;
497 };
498 
499 struct dc_gamma {
500 	struct kref refcount;
501 	enum dc_gamma_type type;
502 	unsigned int num_entries;
503 
504 	struct dc_gamma_entries {
505 		struct fixed31_32 red[GAMMA_MAX_ENTRIES];
506 		struct fixed31_32 green[GAMMA_MAX_ENTRIES];
507 		struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
508 	} entries;
509 
510 	/* private to DC core */
511 	struct dc_context *ctx;
512 
513 	/* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT.
514 	 * is_logical_identity indicates the given gamma ramp regardless of type is identity.
515 	 */
516 	bool is_identity;
517 };
518 
519 /* Used by both ipp amd opp functions*/
520 /* TODO: to be consolidated with enum color_space */
521 
522 /**
523  * enum dc_cursor_color_format - DC cursor programming mode
524  *
525  * This enum is for programming CURSOR_MODE register field. What this register
526  * should be programmed to depends on OS requested cursor shape flags and what
527  * we stored in the cursor surface.
528  */
529 enum dc_cursor_color_format {
530 	CURSOR_MODE_MONO,
531 	CURSOR_MODE_COLOR_1BIT_AND,
532 	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
533 	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
534 	CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
535 	CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
536 };
537 
538 /*
539  * This is all the parameters required by DAL in order to update the cursor
540  * attributes, including the new cursor image surface address, size, hotspot
541  * location, color format, etc.
542  */
543 
544 union dc_cursor_attribute_flags {
545 	struct {
546 		uint32_t ENABLE_MAGNIFICATION:1;
547 		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
548 		uint32_t HORIZONTAL_MIRROR:1;
549 		uint32_t VERTICAL_MIRROR:1;
550 		uint32_t INVERT_PIXEL_DATA:1;
551 		uint32_t ZERO_EXPANSION:1;
552 		uint32_t MIN_MAX_INVERT:1;
553 		uint32_t ENABLE_CURSOR_DEGAMMA:1;
554 		uint32_t RESERVED:24;
555 	} bits;
556 	uint32_t value;
557 };
558 
559 struct dc_cursor_attributes {
560 	/**
561 	 * @address: This field represents the framebuffer address associated
562 	 * with the cursor. It is important to highlight that this address is
563 	 * divided into a high and low parts.
564 	 */
565 	PHYSICAL_ADDRESS_LOC address;
566 
567 	/**
568 	 * @pitch: Cursor line stride.
569 	 */
570 	uint32_t pitch;
571 
572 	/**
573 	 * @width: Width should correspond to cursor surface width.
574 	 */
575 	uint32_t width;
576 	/**
577 	 * @heigh: Height should correspond to cursor surface heigh.
578 	 */
579 	uint32_t height;
580 
581 	/**
582 	 * @color_format: DC cursor programming mode.
583 	 */
584 	enum dc_cursor_color_format color_format;
585 	/**
586 	 * @sdr_white_level: Boosting (SDR) cursor in HDR mode.
587 	 */
588 	uint32_t sdr_white_level;
589 
590 	/**
591 	 * @rotation_angle: In case we support HW Cursor rotation in the future
592 	 */
593 	enum dc_rotation_angle rotation_angle;
594 
595 	union dc_cursor_attribute_flags attribute_flags;
596 };
597 
598 struct dpp_cursor_attributes {
599 	int bias;
600 	int scale;
601 };
602 
603 /* OPP */
604 
605 enum dc_color_space {
606 	COLOR_SPACE_UNKNOWN,
607 	COLOR_SPACE_SRGB,
608 	COLOR_SPACE_XR_RGB,
609 	COLOR_SPACE_SRGB_LIMITED,
610 	COLOR_SPACE_MSREF_SCRGB,
611 	COLOR_SPACE_YCBCR601,
612 	COLOR_SPACE_YCBCR709,
613 	COLOR_SPACE_XV_YCC_709,
614 	COLOR_SPACE_XV_YCC_601,
615 	COLOR_SPACE_YCBCR601_LIMITED,
616 	COLOR_SPACE_YCBCR709_LIMITED,
617 	COLOR_SPACE_2020_RGB_FULLRANGE,
618 	COLOR_SPACE_2020_RGB_LIMITEDRANGE,
619 	COLOR_SPACE_2020_YCBCR,
620 	COLOR_SPACE_ADOBERGB,
621 	COLOR_SPACE_DCIP3,
622 	COLOR_SPACE_DISPLAYNATIVE,
623 	COLOR_SPACE_DOLBYVISION,
624 	COLOR_SPACE_APPCTRL,
625 	COLOR_SPACE_CUSTOMPOINTS,
626 	COLOR_SPACE_YCBCR709_BLACK,
627 };
628 
629 enum dc_dither_option {
630 	DITHER_OPTION_DEFAULT,
631 	DITHER_OPTION_DISABLE,
632 	DITHER_OPTION_FM6,
633 	DITHER_OPTION_FM8,
634 	DITHER_OPTION_FM10,
635 	DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
636 	DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
637 	DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
638 	DITHER_OPTION_SPATIAL6,
639 	DITHER_OPTION_SPATIAL8,
640 	DITHER_OPTION_SPATIAL10,
641 	DITHER_OPTION_TRUN6,
642 	DITHER_OPTION_TRUN8,
643 	DITHER_OPTION_TRUN10,
644 	DITHER_OPTION_TRUN10_SPATIAL8,
645 	DITHER_OPTION_TRUN10_SPATIAL6,
646 	DITHER_OPTION_TRUN10_FM8,
647 	DITHER_OPTION_TRUN10_FM6,
648 	DITHER_OPTION_TRUN10_SPATIAL8_FM6,
649 	DITHER_OPTION_SPATIAL10_FM8,
650 	DITHER_OPTION_SPATIAL10_FM6,
651 	DITHER_OPTION_TRUN8_SPATIAL6,
652 	DITHER_OPTION_TRUN8_FM6,
653 	DITHER_OPTION_SPATIAL8_FM6,
654 	DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
655 	DITHER_OPTION_INVALID
656 };
657 
658 enum dc_quantization_range {
659 	QUANTIZATION_RANGE_UNKNOWN,
660 	QUANTIZATION_RANGE_FULL,
661 	QUANTIZATION_RANGE_LIMITED
662 };
663 
664 enum dc_dynamic_expansion {
665 	DYN_EXPANSION_AUTO,
666 	DYN_EXPANSION_DISABLE
667 };
668 
669 /* XFM */
670 
671 /* used in  struct dc_plane_state */
672 struct scaling_taps {
673 	uint32_t v_taps;
674 	uint32_t h_taps;
675 	uint32_t v_taps_c;
676 	uint32_t h_taps_c;
677 	bool integer_scaling;
678 };
679 
680 enum dc_timing_standard {
681 	DC_TIMING_STANDARD_UNDEFINED,
682 	DC_TIMING_STANDARD_DMT,
683 	DC_TIMING_STANDARD_GTF,
684 	DC_TIMING_STANDARD_CVT,
685 	DC_TIMING_STANDARD_CVT_RB,
686 	DC_TIMING_STANDARD_CEA770,
687 	DC_TIMING_STANDARD_CEA861,
688 	DC_TIMING_STANDARD_HDMI,
689 	DC_TIMING_STANDARD_TV_NTSC,
690 	DC_TIMING_STANDARD_TV_NTSC_J,
691 	DC_TIMING_STANDARD_TV_PAL,
692 	DC_TIMING_STANDARD_TV_PAL_M,
693 	DC_TIMING_STANDARD_TV_PAL_CN,
694 	DC_TIMING_STANDARD_TV_SECAM,
695 	DC_TIMING_STANDARD_EXPLICIT,
696 	/*!< For explicit timings from EDID, VBIOS, etc.*/
697 	DC_TIMING_STANDARD_USER_OVERRIDE,
698 	/*!< For mode timing override by user*/
699 	DC_TIMING_STANDARD_MAX
700 };
701 
702 enum dc_color_depth {
703 	COLOR_DEPTH_UNDEFINED,
704 	COLOR_DEPTH_666,
705 	COLOR_DEPTH_888,
706 	COLOR_DEPTH_101010,
707 	COLOR_DEPTH_121212,
708 	COLOR_DEPTH_141414,
709 	COLOR_DEPTH_161616,
710 	COLOR_DEPTH_999,
711 	COLOR_DEPTH_111111,
712 	COLOR_DEPTH_COUNT
713 };
714 
715 enum dc_pixel_encoding {
716 	PIXEL_ENCODING_UNDEFINED,
717 	PIXEL_ENCODING_RGB,
718 	PIXEL_ENCODING_YCBCR422,
719 	PIXEL_ENCODING_YCBCR444,
720 	PIXEL_ENCODING_YCBCR420,
721 	PIXEL_ENCODING_COUNT
722 };
723 
724 enum dc_aspect_ratio {
725 	ASPECT_RATIO_NO_DATA,
726 	ASPECT_RATIO_4_3,
727 	ASPECT_RATIO_16_9,
728 	ASPECT_RATIO_64_27,
729 	ASPECT_RATIO_256_135,
730 	ASPECT_RATIO_FUTURE
731 };
732 
733 enum scanning_type {
734 	SCANNING_TYPE_NODATA = 0,
735 	SCANNING_TYPE_OVERSCAN,
736 	SCANNING_TYPE_UNDERSCAN,
737 	SCANNING_TYPE_FUTURE,
738 	SCANNING_TYPE_UNDEFINED
739 };
740 
741 struct dc_crtc_timing_flags {
742 	uint32_t INTERLACE :1;
743 	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
744 	 it is positive polarity --reversed with dal1 or video bios define*/
745 	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
746 	 it is positive polarity --reversed with dal1 or video bios define*/
747 
748 	uint32_t HORZ_COUNT_BY_TWO:1;
749 
750 	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
751 	 timing can be driven in 3D format only
752 	 and there is no corresponding 2D timing*/
753 	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
754 	 (right eye = '1', left eye = '0') */
755 	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
756 	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
757 	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
758 	 because corresponding 2D timing also present in the list*/
759 	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
760 	 and we want to match priority of corresponding 3D timing*/
761 	uint32_t Y_ONLY :1;
762 
763 	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
764 	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
765 
766 	uint32_t FORCE_HDR :1;
767 
768 	/* HDMI 2.0 - Support scrambling for TMDS character
769 	 * rates less than or equal to 340Mcsc */
770 	uint32_t LTE_340MCSC_SCRAMBLE:1;
771 
772 	uint32_t DSC : 1; /* Use DSC with this timing */
773 #ifndef TRIM_FSFT
774 	uint32_t FAST_TRANSPORT: 1;
775 #endif
776 	uint32_t VBLANK_SYNCHRONIZABLE: 1;
777 };
778 
779 enum dc_timing_3d_format {
780 	TIMING_3D_FORMAT_NONE,
781 	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
782 	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
783 	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
784 	/* for active DP-HDMI dongle*/
785 	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
786 	TIMING_3D_FORMAT_HW_FRAME_PACKING,
787 	TIMING_3D_FORMAT_SW_FRAME_PACKING,
788 	TIMING_3D_FORMAT_ROW_INTERLEAVE,
789 	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
790 	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
791 	TIMING_3D_FORMAT_SIDE_BY_SIDE,
792 	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
793 	TIMING_3D_FORMAT_SBS_SW_PACKED,
794 	/* Side-by-side, packed by application/driver into 2D frame*/
795 	TIMING_3D_FORMAT_TB_SW_PACKED,
796 	/* Top-and-bottom, packed by application/driver into 2D frame*/
797 
798 	TIMING_3D_FORMAT_MAX,
799 };
800 
801 #define DC_DSC_QP_SET_SIZE 15
802 #define DC_DSC_RC_BUF_THRESH_SIZE 14
803 struct dc_dsc_rc_params_override {
804 	int32_t rc_model_size;
805 	int32_t rc_buf_thresh[DC_DSC_RC_BUF_THRESH_SIZE];
806 	int32_t rc_minqp[DC_DSC_QP_SET_SIZE];
807 	int32_t rc_maxqp[DC_DSC_QP_SET_SIZE];
808 	int32_t rc_offset[DC_DSC_QP_SET_SIZE];
809 
810 	int32_t rc_tgt_offset_hi;
811 	int32_t rc_tgt_offset_lo;
812 	int32_t rc_edge_factor;
813 	int32_t rc_quant_incr_limit0;
814 	int32_t rc_quant_incr_limit1;
815 
816 	int32_t initial_fullness_offset;
817 	int32_t initial_delay;
818 
819 	int32_t flatness_min_qp;
820 	int32_t flatness_max_qp;
821 	int32_t flatness_det_thresh;
822 };
823 
824 struct dc_dsc_config {
825 	uint32_t num_slices_h; /* Number of DSC slices - horizontal */
826 	uint32_t num_slices_v; /* Number of DSC slices - vertical */
827 	uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
828 	bool block_pred_enable; /* DSC block prediction enable */
829 	uint32_t linebuf_depth; /* DSC line buffer depth */
830 	uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
831 	bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
832 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
833 #if defined(CONFIG_DRM_AMD_DC_FP)
834 	bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
835 #endif
836 	bool is_dp; /* indicate if DSC is applied based on DP's capability */
837 	uint32_t mst_pbn; /* pbn of display on dsc mst hub */
838 	const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */
839 };
840 
841 /**
842  * struct dc_crtc_timing - Timing parameters used to configure DCN blocks
843  *
844  * DCN provides multiple signals and parameters that can be used to adjust
845  * timing parameters, this struct aggregate multiple of these values for easy
846  * access. In this struct, fields prefixed with h_* are related to horizontal
847  * timing, and v_* to vertical timing. Keep in mind that when we talk about
848  * vertical timings, the values, in general, are described in the number of
849  * lines; on the other hand, the horizontal values are in pixels.
850  */
851 struct dc_crtc_timing {
852 	/**
853 	 * @h_total: The total number of pixels from the rising edge of HSync
854 	 * until the rising edge of the current HSync.
855 	 */
856 	uint32_t h_total;
857 
858 	/**
859 	 * @h_border_left: The black pixels related to the left border
860 	 */
861 	uint32_t h_border_left;
862 
863 	/**
864 	 * @h_addressable: It is the range of pixels displayed horizontally.
865 	 * For example, if the display resolution is 3840@2160, the horizontal
866 	 * addressable area is 3840.
867 	 */
868 	uint32_t h_addressable;
869 
870 	/**
871 	 * @h_border_right: The black pixels related to the right border
872 	 */
873 	uint32_t h_border_right;
874 
875 	/**
876 	 * @h_front_porch: Period (in pixels) between HBlank start and the
877 	 * rising edge of HSync.
878 	 */
879 	uint32_t h_front_porch;
880 
881 	/**
882 	 * @h_sync_width: HSync duration in pixels.
883 	 */
884 	uint32_t h_sync_width;
885 
886 	/**
887 	 * @v_total: It is the total number of lines from the rising edge of
888 	 * the previous VSync until the rising edge of the current VSync.
889 	 *
890 	 *          |--------------------------|
891 	 *          +-+        V_TOTAL         +-+
892 	 *          | |                        | |
893 	 * VSync ---+ +--------- // -----------+ +---
894 	 */
895 	uint32_t v_total;
896 
897 	/**
898 	 * @v_border_top: The black border on the top.
899 	 */
900 	uint32_t v_border_top;
901 
902 	/**
903 	 * @v_addressable: It is the range of the scanout at which the
904 	 * framebuffer is displayed. For example, if the display resolution is
905 	 * 3840@2160, the addressable area is 2160 lines, or if the resolution
906 	 * is 1920x1080, the addressable area is 1080 lines.
907 	 */
908 	uint32_t v_addressable;
909 
910 	/**
911 	 * @v_border_bottom: The black border on the bottom.
912 	 */
913 	uint32_t v_border_bottom;
914 
915 	/**
916 	 * @v_front_porch: Period (in lines) between VBlank start and rising
917 	 * edge of VSync.
918 	 *                  +-+
919 	 * VSync            | |
920 	 *        ----------+ +--------...
921 	 *          +------------------...
922 	 * VBlank   |
923 	 *        --+
924 	 *          |-------|
925 	 *        v_front_porch
926 	 */
927 	uint32_t v_front_porch;
928 
929 	/**
930 	 * @v_sync_width: VSync signal width in lines.
931 	 */
932 	uint32_t v_sync_width;
933 
934 	/**
935 	 * @pix_clk_100hz: Pipe pixel precision
936 	 *
937 	 * This field is used to communicate pixel clocks with 100 Hz accuracy
938 	 * from dc_crtc_timing to BIOS command table.
939 	 */
940 	uint32_t pix_clk_100hz;
941 
942 	uint32_t min_refresh_in_uhz;
943 
944 	uint32_t vic;
945 	uint32_t hdmi_vic;
946 	uint32_t rid;
947 	uint32_t fr_index;
948 	enum dc_timing_3d_format timing_3d_format;
949 	enum dc_color_depth display_color_depth;
950 	enum dc_pixel_encoding pixel_encoding;
951 	enum dc_aspect_ratio aspect_ratio;
952 	enum scanning_type scan_type;
953 
954 #ifndef TRIM_FSFT
955 	uint32_t fast_transport_output_rate_100hz;
956 #endif
957 
958 	struct dc_crtc_timing_flags flags;
959 	uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
960 	struct dc_dsc_config dsc_cfg;
961 };
962 
963 enum trigger_delay {
964 	TRIGGER_DELAY_NEXT_PIXEL = 0,
965 	TRIGGER_DELAY_NEXT_LINE,
966 };
967 
968 enum crtc_event {
969 	CRTC_EVENT_VSYNC_RISING = 0,
970 	CRTC_EVENT_VSYNC_FALLING
971 };
972 
973 struct crtc_trigger_info {
974 	bool enabled;
975 	struct dc_stream_state *event_source;
976 	enum crtc_event event;
977 	enum trigger_delay delay;
978 };
979 
980 struct dc_crtc_timing_adjust {
981 	uint32_t v_total_min;
982 	uint32_t v_total_max;
983 	uint32_t v_total_mid;
984 	uint32_t v_total_mid_frame_num;
985 };
986 
987 
988 /* Passed on init */
989 enum vram_type {
990 	VIDEO_MEMORY_TYPE_GDDR5  = 2,
991 	VIDEO_MEMORY_TYPE_DDR3   = 3,
992 	VIDEO_MEMORY_TYPE_DDR4   = 4,
993 	VIDEO_MEMORY_TYPE_HBM    = 5,
994 	VIDEO_MEMORY_TYPE_GDDR6  = 6,
995 };
996 
997 enum dwb_cnv_out_bpc {
998 	DWB_CNV_OUT_BPC_8BPC  = 0,
999 	DWB_CNV_OUT_BPC_10BPC = 1,
1000 };
1001 
1002 enum dwb_output_depth {
1003 	DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
1004 	DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
1005 };
1006 
1007 enum dwb_capture_rate {
1008 	dwb_capture_rate_0 = 0,	/* Every frame is captured. */
1009 	dwb_capture_rate_1 = 1,	/* Every other frame is captured. */
1010 	dwb_capture_rate_2 = 2,	/* Every 3rd frame is captured. */
1011 	dwb_capture_rate_3 = 3,	/* Every 4th frame is captured. */
1012 };
1013 
1014 enum dwb_scaler_mode {
1015 	dwb_scaler_mode_bypass444 = 0,
1016 	dwb_scaler_mode_rgb444 = 1,
1017 	dwb_scaler_mode_yuv444 = 2,
1018 	dwb_scaler_mode_yuv420 = 3
1019 };
1020 
1021 enum dwb_subsample_position {
1022 	DWB_INTERSTITIAL_SUBSAMPLING = 0,
1023 	DWB_COSITED_SUBSAMPLING      = 1
1024 };
1025 
1026 enum dwb_stereo_eye_select {
1027 	DWB_STEREO_EYE_LEFT  = 1,		/* Capture left eye only */
1028 	DWB_STEREO_EYE_RIGHT = 2,		/* Capture right eye only */
1029 };
1030 
1031 enum dwb_stereo_type {
1032 	DWB_STEREO_TYPE_FRAME_PACKING = 0,		/* Frame packing */
1033 	DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3,	/* Frame sequential */
1034 };
1035 
1036 enum dwb_out_format {
1037 	DWB_OUT_FORMAT_32BPP_ARGB = 0,
1038 	DWB_OUT_FORMAT_32BPP_RGBA = 1,
1039 	DWB_OUT_FORMAT_64BPP_ARGB = 2,
1040 	DWB_OUT_FORMAT_64BPP_RGBA = 3
1041 };
1042 
1043 enum dwb_out_denorm {
1044 	DWB_OUT_DENORM_10BPC = 0,
1045 	DWB_OUT_DENORM_8BPC = 1,
1046 	DWB_OUT_DENORM_BYPASS = 2
1047 };
1048 
1049 enum cm_gamut_remap_select {
1050 	CM_GAMUT_REMAP_MODE_BYPASS = 0,
1051 	CM_GAMUT_REMAP_MODE_RAMA_COEFF,
1052 	CM_GAMUT_REMAP_MODE_RAMB_COEFF,
1053 	CM_GAMUT_REMAP_MODE_RESERVED
1054 };
1055 
1056 enum cm_gamut_coef_format {
1057 	CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0,
1058 	CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1
1059 };
1060 
1061 struct mcif_warmup_params {
1062 	union large_integer	start_address;
1063 	unsigned int		address_increment;
1064 	unsigned int		region_size;
1065 	unsigned int		p_vmid;
1066 };
1067 
1068 #define MCIF_BUF_COUNT	4
1069 
1070 struct mcif_buf_params {
1071 	unsigned long long	luma_address[MCIF_BUF_COUNT];
1072 	unsigned long long	chroma_address[MCIF_BUF_COUNT];
1073 	unsigned int		luma_pitch;
1074 	unsigned int		chroma_pitch;
1075 	unsigned int		warmup_pitch;
1076 	unsigned int		swlock;
1077 	unsigned int		p_vmid;
1078 };
1079 
1080 
1081 #define MAX_TG_COLOR_VALUE 0x3FF
1082 struct tg_color {
1083 	/* Maximum 10 bits color value */
1084 	uint16_t color_r_cr;
1085 	uint16_t color_g_y;
1086 	uint16_t color_b_cb;
1087 };
1088 
1089 enum symclk_state {
1090 	SYMCLK_OFF_TX_OFF,
1091 	SYMCLK_ON_TX_ON,
1092 	SYMCLK_ON_TX_OFF,
1093 };
1094 
1095 struct phy_state {
1096 	struct {
1097 		uint8_t otg		: 1;
1098 		uint8_t reserved	: 7;
1099 	} symclk_ref_cnts;
1100 	enum symclk_state symclk_state;
1101 };
1102 
1103 #endif /* DC_HW_TYPES_H */
1104 
1105