1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/mach-imx/spi.h>
13 #include <linux/errno.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/mxc_i2c.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/video.h>
19 #include <mmc.h>
20 #include <fsl_esdhc.h>
21 #include <miiphy.h>
22 #include <netdev.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h>
26 #include <asm/arch/sys_proto.h>
27 #include <i2c.h>
28 #include <input.h>
29 #include <power/pmic.h>
30 #include <power/pfuze100_pmic.h>
31 #include "../common/pfuze.h"
32 #include <usb.h>
33 #include <usb/ehci-ci.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
50
51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54
55 #define I2C_PMIC 1
56
57 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
58
59 #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
60
61 #define KEY_VOL_UP IMX_GPIO_NR(1, 4)
62
dram_init(void)63 int dram_init(void)
64 {
65 gd->ram_size = imx_ddr_size();
66 return 0;
67 }
68
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
72 };
73
74 static iomux_v3_cfg_t const enet_pads[] = {
75 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 /* AR8031 PHY Reset */
91 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 };
93
setup_iomux_enet(void)94 static void setup_iomux_enet(void)
95 {
96 SETUP_IOMUX_PADS(enet_pads);
97 }
98
99 static iomux_v3_cfg_t const usdhc2_pads[] = {
100 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
101 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
102 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
104 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
107 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
110 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
111 };
112
113 static iomux_v3_cfg_t const usdhc3_pads[] = {
114 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
115 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
116 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
117 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
118 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
119 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
120 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
121 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
122 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
123 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
125 };
126
127 static iomux_v3_cfg_t const usdhc4_pads[] = {
128 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
129 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
130 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
131 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
132 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
134 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 };
139
140 static iomux_v3_cfg_t const ecspi1_pads[] = {
141 IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
142 IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
143 IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
144 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
145 };
146
147 static iomux_v3_cfg_t const rgb_pads[] = {
148 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
149 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
150 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
151 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
152 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
153 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
154 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
155 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
156 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
157 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
158 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
159 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
160 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
161 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
162 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
163 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
164 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
165 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
166 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
167 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
168 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
170 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
171 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
173 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
174 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
175 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
177 };
178
179 static iomux_v3_cfg_t const bl_pads[] = {
180 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
181 };
182
enable_backlight(void)183 static void enable_backlight(void)
184 {
185 SETUP_IOMUX_PADS(bl_pads);
186 gpio_request(DISP0_PWR_EN, "Display Power Enable");
187 gpio_direction_output(DISP0_PWR_EN, 1);
188 }
189
enable_rgb(struct display_info_t const * dev)190 static void enable_rgb(struct display_info_t const *dev)
191 {
192 SETUP_IOMUX_PADS(rgb_pads);
193 enable_backlight();
194 }
195
enable_lvds(struct display_info_t const * dev)196 static void enable_lvds(struct display_info_t const *dev)
197 {
198 enable_backlight();
199 }
200
201 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
202 .scl = {
203 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
204 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
205 .gp = IMX_GPIO_NR(4, 12)
206 },
207 .sda = {
208 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
209 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
210 .gp = IMX_GPIO_NR(4, 13)
211 }
212 };
213
214 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
215 .scl = {
216 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
217 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
218 .gp = IMX_GPIO_NR(4, 12)
219 },
220 .sda = {
221 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
222 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
223 .gp = IMX_GPIO_NR(4, 13)
224 }
225 };
226
setup_spi(void)227 static void setup_spi(void)
228 {
229 SETUP_IOMUX_PADS(ecspi1_pads);
230 }
231
232 iomux_v3_cfg_t const pcie_pads[] = {
233 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
234 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
235 };
236
setup_pcie(void)237 static void setup_pcie(void)
238 {
239 SETUP_IOMUX_PADS(pcie_pads);
240 }
241
242 iomux_v3_cfg_t const di0_pads[] = {
243 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
244 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
245 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
246 };
247
setup_iomux_uart(void)248 static void setup_iomux_uart(void)
249 {
250 SETUP_IOMUX_PADS(uart1_pads);
251 }
252
253 #ifdef CONFIG_FSL_ESDHC
254 struct fsl_esdhc_cfg usdhc_cfg[3] = {
255 {USDHC2_BASE_ADDR},
256 {USDHC3_BASE_ADDR},
257 {USDHC4_BASE_ADDR},
258 };
259
260 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
261 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
262
board_mmc_get_env_dev(int devno)263 int board_mmc_get_env_dev(int devno)
264 {
265 return devno - 1;
266 }
267
board_mmc_getcd(struct mmc * mmc)268 int board_mmc_getcd(struct mmc *mmc)
269 {
270 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
271 int ret = 0;
272
273 switch (cfg->esdhc_base) {
274 case USDHC2_BASE_ADDR:
275 ret = !gpio_get_value(USDHC2_CD_GPIO);
276 break;
277 case USDHC3_BASE_ADDR:
278 ret = !gpio_get_value(USDHC3_CD_GPIO);
279 break;
280 case USDHC4_BASE_ADDR:
281 ret = 1; /* eMMC/uSDHC4 is always present */
282 break;
283 }
284
285 return ret;
286 }
287
board_mmc_init(bd_t * bis)288 int board_mmc_init(bd_t *bis)
289 {
290 #ifndef CONFIG_SPL_BUILD
291 int ret;
292 int i;
293
294 /*
295 * According to the board_mmc_init() the following map is done:
296 * (U-Boot device node) (Physical Port)
297 * mmc0 SD2
298 * mmc1 SD3
299 * mmc2 eMMC
300 */
301 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
302 switch (i) {
303 case 0:
304 SETUP_IOMUX_PADS(usdhc2_pads);
305 gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
306 gpio_direction_input(USDHC2_CD_GPIO);
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
308 break;
309 case 1:
310 SETUP_IOMUX_PADS(usdhc3_pads);
311 gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
312 gpio_direction_input(USDHC3_CD_GPIO);
313 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
314 break;
315 case 2:
316 SETUP_IOMUX_PADS(usdhc4_pads);
317 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
318 break;
319 default:
320 printf("Warning: you configured more USDHC controllers"
321 "(%d) then supported by the board (%d)\n",
322 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
323 return -EINVAL;
324 }
325
326 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
327 if (ret)
328 return ret;
329 }
330
331 return 0;
332 #else
333 struct src *psrc = (struct src *)SRC_BASE_ADDR;
334 unsigned reg = readl(&psrc->sbmr1) >> 11;
335 /*
336 * Upon reading BOOT_CFG register the following map is done:
337 * Bit 11 and 12 of BOOT_CFG register can determine the current
338 * mmc port
339 * 0x1 SD1
340 * 0x2 SD2
341 * 0x3 SD4
342 */
343
344 switch (reg & 0x3) {
345 case 0x1:
346 SETUP_IOMUX_PADS(usdhc2_pads);
347 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
348 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
349 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
350 break;
351 case 0x2:
352 SETUP_IOMUX_PADS(usdhc3_pads);
353 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
354 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
355 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
356 break;
357 case 0x3:
358 SETUP_IOMUX_PADS(usdhc4_pads);
359 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
360 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
361 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
362 break;
363 }
364
365 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
366 #endif
367 }
368 #endif
369
ar8031_phy_fixup(struct phy_device * phydev)370 static int ar8031_phy_fixup(struct phy_device *phydev)
371 {
372 unsigned short val;
373
374 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
375 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
376 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
378
379 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
380 val &= 0xffe3;
381 val |= 0x18;
382 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
383
384 /* introduce tx clock delay */
385 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
386 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
387 val |= 0x0100;
388 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
389
390 return 0;
391 }
392
board_phy_config(struct phy_device * phydev)393 int board_phy_config(struct phy_device *phydev)
394 {
395 ar8031_phy_fixup(phydev);
396
397 if (phydev->drv->config)
398 phydev->drv->config(phydev);
399
400 return 0;
401 }
402
403 #if defined(CONFIG_VIDEO_IPUV3)
disable_lvds(struct display_info_t const * dev)404 static void disable_lvds(struct display_info_t const *dev)
405 {
406 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
407
408 int reg = readl(&iomux->gpr[2]);
409
410 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
411 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
412
413 writel(reg, &iomux->gpr[2]);
414 }
415
do_enable_hdmi(struct display_info_t const * dev)416 static void do_enable_hdmi(struct display_info_t const *dev)
417 {
418 disable_lvds(dev);
419 imx_enable_hdmi_phy();
420 }
421
422 struct display_info_t const displays[] = {{
423 .bus = -1,
424 .addr = 0,
425 .pixfmt = IPU_PIX_FMT_RGB666,
426 .detect = NULL,
427 .enable = enable_lvds,
428 .mode = {
429 .name = "Hannstar-XGA",
430 .refresh = 60,
431 .xres = 1024,
432 .yres = 768,
433 .pixclock = 15384,
434 .left_margin = 160,
435 .right_margin = 24,
436 .upper_margin = 29,
437 .lower_margin = 3,
438 .hsync_len = 136,
439 .vsync_len = 6,
440 .sync = FB_SYNC_EXT,
441 .vmode = FB_VMODE_NONINTERLACED
442 } }, {
443 .bus = -1,
444 .addr = 0,
445 .pixfmt = IPU_PIX_FMT_RGB24,
446 .detect = detect_hdmi,
447 .enable = do_enable_hdmi,
448 .mode = {
449 .name = "HDMI",
450 .refresh = 60,
451 .xres = 1024,
452 .yres = 768,
453 .pixclock = 15384,
454 .left_margin = 160,
455 .right_margin = 24,
456 .upper_margin = 29,
457 .lower_margin = 3,
458 .hsync_len = 136,
459 .vsync_len = 6,
460 .sync = FB_SYNC_EXT,
461 .vmode = FB_VMODE_NONINTERLACED
462 } }, {
463 .bus = 0,
464 .addr = 0,
465 .pixfmt = IPU_PIX_FMT_RGB24,
466 .detect = NULL,
467 .enable = enable_rgb,
468 .mode = {
469 .name = "SEIKO-WVGA",
470 .refresh = 60,
471 .xres = 800,
472 .yres = 480,
473 .pixclock = 29850,
474 .left_margin = 89,
475 .right_margin = 164,
476 .upper_margin = 23,
477 .lower_margin = 10,
478 .hsync_len = 10,
479 .vsync_len = 10,
480 .sync = 0,
481 .vmode = FB_VMODE_NONINTERLACED
482 } } };
483 size_t display_count = ARRAY_SIZE(displays);
484
setup_display(void)485 static void setup_display(void)
486 {
487 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
488 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
489 int reg;
490
491 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
492 SETUP_IOMUX_PADS(di0_pads);
493
494 enable_ipu_clock();
495 imx_setup_hdmi();
496
497 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
498 reg = readl(&mxc_ccm->CCGR3);
499 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
500 writel(reg, &mxc_ccm->CCGR3);
501
502 /* set LDB0, LDB1 clk select to 011/011 */
503 reg = readl(&mxc_ccm->cs2cdr);
504 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
505 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
506 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
507 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
508 writel(reg, &mxc_ccm->cs2cdr);
509
510 reg = readl(&mxc_ccm->cscmr2);
511 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
512 writel(reg, &mxc_ccm->cscmr2);
513
514 reg = readl(&mxc_ccm->chsccdr);
515 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
516 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
517 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
518 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
519 writel(reg, &mxc_ccm->chsccdr);
520
521 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
522 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
523 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
524 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
525 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
526 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
527 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
528 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
529 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
530 writel(reg, &iomux->gpr[2]);
531
532 reg = readl(&iomux->gpr[3]);
533 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
534 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
535 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
536 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
537 writel(reg, &iomux->gpr[3]);
538 }
539 #endif /* CONFIG_VIDEO_IPUV3 */
540
541 /*
542 * Do not overwrite the console
543 * Use always serial for U-Boot console
544 */
overwrite_console(void)545 int overwrite_console(void)
546 {
547 return 1;
548 }
549
board_eth_init(bd_t * bis)550 int board_eth_init(bd_t *bis)
551 {
552 setup_iomux_enet();
553 setup_pcie();
554
555 return cpu_eth_init(bis);
556 }
557
558 #ifdef CONFIG_USB_EHCI_MX6
setup_usb(void)559 static void setup_usb(void)
560 {
561 /*
562 * set daisy chain for otg_pin_id on 6q.
563 * for 6dl, this bit is reserved
564 */
565 imx_iomux_set_gpr_register(1, 13, 1, 0);
566 }
567 #endif
568
board_early_init_f(void)569 int board_early_init_f(void)
570 {
571 setup_iomux_uart();
572
573 return 0;
574 }
575
board_init(void)576 int board_init(void)
577 {
578 /* address of boot parameters */
579 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
580
581 #ifdef CONFIG_MXC_SPI
582 setup_spi();
583 #endif
584 if (is_mx6dq() || is_mx6dqp())
585 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
586 else
587 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
588 #if defined(CONFIG_VIDEO_IPUV3)
589 setup_display();
590 #endif
591 #ifdef CONFIG_USB_EHCI_MX6
592 setup_usb();
593 #endif
594
595 return 0;
596 }
597
power_init_board(void)598 int power_init_board(void)
599 {
600 struct pmic *p;
601 unsigned int reg;
602 int ret;
603
604 p = pfuze_common_init(I2C_PMIC);
605 if (!p)
606 return -ENODEV;
607
608 ret = pfuze_mode_init(p, APS_PFM);
609 if (ret < 0)
610 return ret;
611
612 /* Increase VGEN3 from 2.5 to 2.8V */
613 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
614 reg &= ~LDO_VOL_MASK;
615 reg |= LDOB_2_80V;
616 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
617
618 /* Increase VGEN5 from 2.8 to 3V */
619 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
620 reg &= ~LDO_VOL_MASK;
621 reg |= LDOB_3_00V;
622 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
623
624 return 0;
625 }
626
627 #ifdef CONFIG_MXC_SPI
board_spi_cs_gpio(unsigned bus,unsigned cs)628 int board_spi_cs_gpio(unsigned bus, unsigned cs)
629 {
630 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
631 }
632 #endif
633
634 #ifdef CONFIG_CMD_BMODE
635 static const struct boot_mode board_boot_modes[] = {
636 /* 4 bit bus width */
637 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
638 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
639 /* 8 bit bus width */
640 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
641 {NULL, 0},
642 };
643 #endif
644
board_late_init(void)645 int board_late_init(void)
646 {
647 #ifdef CONFIG_CMD_BMODE
648 add_board_boot_modes(board_boot_modes);
649 #endif
650
651 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
652 env_set("board_name", "SABRESD");
653
654 if (is_mx6dqp())
655 env_set("board_rev", "MX6QP");
656 else if (is_mx6dq())
657 env_set("board_rev", "MX6Q");
658 else if (is_mx6sdl())
659 env_set("board_rev", "MX6DL");
660 #endif
661
662 return 0;
663 }
664
checkboard(void)665 int checkboard(void)
666 {
667 puts("Board: MX6-SabreSD\n");
668 return 0;
669 }
670
671 #ifdef CONFIG_SPL_BUILD
672 #include <asm/arch/mx6-ddr.h>
673 #include <spl.h>
674 #include <linux/libfdt.h>
675
676 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)677 int spl_start_uboot(void)
678 {
679 gpio_request(KEY_VOL_UP, "KEY Volume UP");
680 gpio_direction_input(KEY_VOL_UP);
681
682 /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
683 return gpio_get_value(KEY_VOL_UP);
684 }
685 #endif
686
ccgr_init(void)687 static void ccgr_init(void)
688 {
689 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
690
691 writel(0x00C03F3F, &ccm->CCGR0);
692 writel(0x0030FC03, &ccm->CCGR1);
693 writel(0x0FFFC000, &ccm->CCGR2);
694 writel(0x3FF00000, &ccm->CCGR3);
695 writel(0x00FFF300, &ccm->CCGR4);
696 writel(0x0F0000C3, &ccm->CCGR5);
697 writel(0x000003FF, &ccm->CCGR6);
698 }
699
700 static int mx6q_dcd_table[] = {
701 0x020e0798, 0x000C0000,
702 0x020e0758, 0x00000000,
703 0x020e0588, 0x00000030,
704 0x020e0594, 0x00000030,
705 0x020e056c, 0x00000030,
706 0x020e0578, 0x00000030,
707 0x020e074c, 0x00000030,
708 0x020e057c, 0x00000030,
709 0x020e058c, 0x00000000,
710 0x020e059c, 0x00000030,
711 0x020e05a0, 0x00000030,
712 0x020e078c, 0x00000030,
713 0x020e0750, 0x00020000,
714 0x020e05a8, 0x00000030,
715 0x020e05b0, 0x00000030,
716 0x020e0524, 0x00000030,
717 0x020e051c, 0x00000030,
718 0x020e0518, 0x00000030,
719 0x020e050c, 0x00000030,
720 0x020e05b8, 0x00000030,
721 0x020e05c0, 0x00000030,
722 0x020e0774, 0x00020000,
723 0x020e0784, 0x00000030,
724 0x020e0788, 0x00000030,
725 0x020e0794, 0x00000030,
726 0x020e079c, 0x00000030,
727 0x020e07a0, 0x00000030,
728 0x020e07a4, 0x00000030,
729 0x020e07a8, 0x00000030,
730 0x020e0748, 0x00000030,
731 0x020e05ac, 0x00000030,
732 0x020e05b4, 0x00000030,
733 0x020e0528, 0x00000030,
734 0x020e0520, 0x00000030,
735 0x020e0514, 0x00000030,
736 0x020e0510, 0x00000030,
737 0x020e05bc, 0x00000030,
738 0x020e05c4, 0x00000030,
739 0x021b0800, 0xa1390003,
740 0x021b080c, 0x001F001F,
741 0x021b0810, 0x001F001F,
742 0x021b480c, 0x001F001F,
743 0x021b4810, 0x001F001F,
744 0x021b083c, 0x43270338,
745 0x021b0840, 0x03200314,
746 0x021b483c, 0x431A032F,
747 0x021b4840, 0x03200263,
748 0x021b0848, 0x4B434748,
749 0x021b4848, 0x4445404C,
750 0x021b0850, 0x38444542,
751 0x021b4850, 0x4935493A,
752 0x021b081c, 0x33333333,
753 0x021b0820, 0x33333333,
754 0x021b0824, 0x33333333,
755 0x021b0828, 0x33333333,
756 0x021b481c, 0x33333333,
757 0x021b4820, 0x33333333,
758 0x021b4824, 0x33333333,
759 0x021b4828, 0x33333333,
760 0x021b08b8, 0x00000800,
761 0x021b48b8, 0x00000800,
762 0x021b0004, 0x00020036,
763 0x021b0008, 0x09444040,
764 0x021b000c, 0x555A7975,
765 0x021b0010, 0xFF538F64,
766 0x021b0014, 0x01FF00DB,
767 0x021b0018, 0x00001740,
768 0x021b001c, 0x00008000,
769 0x021b002c, 0x000026d2,
770 0x021b0030, 0x005A1023,
771 0x021b0040, 0x00000027,
772 0x021b0000, 0x831A0000,
773 0x021b001c, 0x04088032,
774 0x021b001c, 0x00008033,
775 0x021b001c, 0x00048031,
776 0x021b001c, 0x09408030,
777 0x021b001c, 0x04008040,
778 0x021b0020, 0x00005800,
779 0x021b0818, 0x00011117,
780 0x021b4818, 0x00011117,
781 0x021b0004, 0x00025576,
782 0x021b0404, 0x00011006,
783 0x021b001c, 0x00000000,
784 };
785
786 static int mx6qp_dcd_table[] = {
787 0x020e0798, 0x000c0000,
788 0x020e0758, 0x00000000,
789 0x020e0588, 0x00000030,
790 0x020e0594, 0x00000030,
791 0x020e056c, 0x00000030,
792 0x020e0578, 0x00000030,
793 0x020e074c, 0x00000030,
794 0x020e057c, 0x00000030,
795 0x020e058c, 0x00000000,
796 0x020e059c, 0x00000030,
797 0x020e05a0, 0x00000030,
798 0x020e078c, 0x00000030,
799 0x020e0750, 0x00020000,
800 0x020e05a8, 0x00000030,
801 0x020e05b0, 0x00000030,
802 0x020e0524, 0x00000030,
803 0x020e051c, 0x00000030,
804 0x020e0518, 0x00000030,
805 0x020e050c, 0x00000030,
806 0x020e05b8, 0x00000030,
807 0x020e05c0, 0x00000030,
808 0x020e0774, 0x00020000,
809 0x020e0784, 0x00000030,
810 0x020e0788, 0x00000030,
811 0x020e0794, 0x00000030,
812 0x020e079c, 0x00000030,
813 0x020e07a0, 0x00000030,
814 0x020e07a4, 0x00000030,
815 0x020e07a8, 0x00000030,
816 0x020e0748, 0x00000030,
817 0x020e05ac, 0x00000030,
818 0x020e05b4, 0x00000030,
819 0x020e0528, 0x00000030,
820 0x020e0520, 0x00000030,
821 0x020e0514, 0x00000030,
822 0x020e0510, 0x00000030,
823 0x020e05bc, 0x00000030,
824 0x020e05c4, 0x00000030,
825 0x021b0800, 0xa1390003,
826 0x021b080c, 0x001b001e,
827 0x021b0810, 0x002e0029,
828 0x021b480c, 0x001b002a,
829 0x021b4810, 0x0019002c,
830 0x021b083c, 0x43240334,
831 0x021b0840, 0x0324031a,
832 0x021b483c, 0x43340344,
833 0x021b4840, 0x03280276,
834 0x021b0848, 0x44383A3E,
835 0x021b4848, 0x3C3C3846,
836 0x021b0850, 0x2e303230,
837 0x021b4850, 0x38283E34,
838 0x021b081c, 0x33333333,
839 0x021b0820, 0x33333333,
840 0x021b0824, 0x33333333,
841 0x021b0828, 0x33333333,
842 0x021b481c, 0x33333333,
843 0x021b4820, 0x33333333,
844 0x021b4824, 0x33333333,
845 0x021b4828, 0x33333333,
846 0x021b08c0, 0x24912249,
847 0x021b48c0, 0x24914289,
848 0x021b08b8, 0x00000800,
849 0x021b48b8, 0x00000800,
850 0x021b0004, 0x00020036,
851 0x021b0008, 0x24444040,
852 0x021b000c, 0x555A7955,
853 0x021b0010, 0xFF320F64,
854 0x021b0014, 0x01ff00db,
855 0x021b0018, 0x00001740,
856 0x021b001c, 0x00008000,
857 0x021b002c, 0x000026d2,
858 0x021b0030, 0x005A1023,
859 0x021b0040, 0x00000027,
860 0x021b0400, 0x14420000,
861 0x021b0000, 0x831A0000,
862 0x021b0890, 0x00400C58,
863 0x00bb0008, 0x00000000,
864 0x00bb000c, 0x2891E41A,
865 0x00bb0038, 0x00000564,
866 0x00bb0014, 0x00000040,
867 0x00bb0028, 0x00000020,
868 0x00bb002c, 0x00000020,
869 0x021b001c, 0x04088032,
870 0x021b001c, 0x00008033,
871 0x021b001c, 0x00048031,
872 0x021b001c, 0x09408030,
873 0x021b001c, 0x04008040,
874 0x021b0020, 0x00005800,
875 0x021b0818, 0x00011117,
876 0x021b4818, 0x00011117,
877 0x021b0004, 0x00025576,
878 0x021b0404, 0x00011006,
879 0x021b001c, 0x00000000,
880 };
881
882 static int mx6dl_dcd_table[] = {
883 0x020e0774, 0x000C0000,
884 0x020e0754, 0x00000000,
885 0x020e04ac, 0x00000030,
886 0x020e04b0, 0x00000030,
887 0x020e0464, 0x00000030,
888 0x020e0490, 0x00000030,
889 0x020e074c, 0x00000030,
890 0x020e0494, 0x00000030,
891 0x020e04a0, 0x00000000,
892 0x020e04b4, 0x00000030,
893 0x020e04b8, 0x00000030,
894 0x020e076c, 0x00000030,
895 0x020e0750, 0x00020000,
896 0x020e04bc, 0x00000030,
897 0x020e04c0, 0x00000030,
898 0x020e04c4, 0x00000030,
899 0x020e04c8, 0x00000030,
900 0x020e04cc, 0x00000030,
901 0x020e04d0, 0x00000030,
902 0x020e04d4, 0x00000030,
903 0x020e04d8, 0x00000030,
904 0x020e0760, 0x00020000,
905 0x020e0764, 0x00000030,
906 0x020e0770, 0x00000030,
907 0x020e0778, 0x00000030,
908 0x020e077c, 0x00000030,
909 0x020e0780, 0x00000030,
910 0x020e0784, 0x00000030,
911 0x020e078c, 0x00000030,
912 0x020e0748, 0x00000030,
913 0x020e0470, 0x00000030,
914 0x020e0474, 0x00000030,
915 0x020e0478, 0x00000030,
916 0x020e047c, 0x00000030,
917 0x020e0480, 0x00000030,
918 0x020e0484, 0x00000030,
919 0x020e0488, 0x00000030,
920 0x020e048c, 0x00000030,
921 0x021b0800, 0xa1390003,
922 0x021b080c, 0x001F001F,
923 0x021b0810, 0x001F001F,
924 0x021b480c, 0x001F001F,
925 0x021b4810, 0x001F001F,
926 0x021b083c, 0x4220021F,
927 0x021b0840, 0x0207017E,
928 0x021b483c, 0x4201020C,
929 0x021b4840, 0x01660172,
930 0x021b0848, 0x4A4D4E4D,
931 0x021b4848, 0x4A4F5049,
932 0x021b0850, 0x3F3C3D31,
933 0x021b4850, 0x3238372B,
934 0x021b081c, 0x33333333,
935 0x021b0820, 0x33333333,
936 0x021b0824, 0x33333333,
937 0x021b0828, 0x33333333,
938 0x021b481c, 0x33333333,
939 0x021b4820, 0x33333333,
940 0x021b4824, 0x33333333,
941 0x021b4828, 0x33333333,
942 0x021b08b8, 0x00000800,
943 0x021b48b8, 0x00000800,
944 0x021b0004, 0x0002002D,
945 0x021b0008, 0x00333030,
946 0x021b000c, 0x3F435313,
947 0x021b0010, 0xB66E8B63,
948 0x021b0014, 0x01FF00DB,
949 0x021b0018, 0x00001740,
950 0x021b001c, 0x00008000,
951 0x021b002c, 0x000026d2,
952 0x021b0030, 0x00431023,
953 0x021b0040, 0x00000027,
954 0x021b0000, 0x831A0000,
955 0x021b001c, 0x04008032,
956 0x021b001c, 0x00008033,
957 0x021b001c, 0x00048031,
958 0x021b001c, 0x05208030,
959 0x021b001c, 0x04008040,
960 0x021b0020, 0x00005800,
961 0x021b0818, 0x00011117,
962 0x021b4818, 0x00011117,
963 0x021b0004, 0x0002556D,
964 0x021b0404, 0x00011006,
965 0x021b001c, 0x00000000,
966 };
967
ddr_init(int * table,int size)968 static void ddr_init(int *table, int size)
969 {
970 int i;
971
972 for (i = 0; i < size / 2 ; i++)
973 writel(table[2 * i + 1], table[2 * i]);
974 }
975
spl_dram_init(void)976 static void spl_dram_init(void)
977 {
978 if (is_mx6dq())
979 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
980 else if (is_mx6dqp())
981 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
982 else if (is_mx6sdl())
983 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
984 }
985
board_init_f(ulong dummy)986 void board_init_f(ulong dummy)
987 {
988 /* DDR initialization */
989 spl_dram_init();
990
991 /* setup AIPS and disable watchdog */
992 arch_cpu_init();
993
994 ccgr_init();
995 gpr_init();
996
997 /* iomux and setup of i2c */
998 board_early_init_f();
999
1000 /* setup GP timer */
1001 timer_init();
1002
1003 /* UART clocks enabled and gd valid - init serial console */
1004 preloader_console_init();
1005
1006 /* Clear the BSS. */
1007 memset(__bss_start, 0, __bss_end - __bss_start);
1008
1009 /* load/boot image from boot device */
1010 board_init_r(NULL, 0);
1011 }
1012 #endif
1013
1014 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)1015 int board_fit_config_name_match(const char *name)
1016 {
1017 if (is_mx6dq()) {
1018 if (!strcmp(name, "imx6q-sabresd"))
1019 return 0;
1020 } else if (is_mx6dqp()) {
1021 if (!strcmp(name, "imx6qp-sabresd"))
1022 return 0;
1023 } else if (is_mx6dl()) {
1024 if (!strcmp(name, "imx6dl-sabresd"))
1025 return 0;
1026 }
1027
1028 return -1;
1029 }
1030 #endif
1031