xref: /openbmc/qemu/hw/pci-host/designware.c (revision 8a731520)
1 /*
2  * Copyright (c) 2018, Impinj, Inc.
3  *
4  * Designware PCIe IP block emulation
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "qemu/log.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_host.h"
28 #include "hw/pci/pcie_port.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "hw/irq.h"
32 #include "hw/pci-host/designware.h"
33 
34 #define DESIGNWARE_PCIE_PORT_LINK_CONTROL          0x710
35 #define DESIGNWARE_PCIE_PHY_DEBUG_R1               0x72C
36 #define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
37 #define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
38 #define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE    BIT(17)
39 #define DESIGNWARE_PCIE_MSI_ADDR_LO                0x820
40 #define DESIGNWARE_PCIE_MSI_ADDR_HI                0x824
41 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
42 #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
43 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
44 #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
45 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
46 #define DESIGNWARE_PCIE_ATU_CR1                    0x904
47 #define DESIGNWARE_PCIE_ATU_TYPE_MEM               (0x0 << 0)
48 #define DESIGNWARE_PCIE_ATU_CR2                    0x908
49 #define DESIGNWARE_PCIE_ATU_ENABLE                 BIT(31)
50 #define DESIGNWARE_PCIE_ATU_LOWER_BASE             0x90C
51 #define DESIGNWARE_PCIE_ATU_UPPER_BASE             0x910
52 #define DESIGNWARE_PCIE_ATU_LIMIT                  0x914
53 #define DESIGNWARE_PCIE_ATU_LOWER_TARGET           0x918
54 #define DESIGNWARE_PCIE_ATU_BUS(x)                 (((x) >> 24) & 0xff)
55 #define DESIGNWARE_PCIE_ATU_DEVFN(x)               (((x) >> 16) & 0xff)
56 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET           0x91C
57 
58 #define DESIGNWARE_PCIE_IRQ_MSI                    3
59 
60 static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot * root)61 designware_pcie_root_to_host(DesignwarePCIERoot *root)
62 {
63     BusState *bus = qdev_get_parent_bus(DEVICE(root));
64     return DESIGNWARE_PCIE_HOST(bus->parent);
65 }
66 
designware_pcie_root_msi_read(void * opaque,hwaddr addr,unsigned size)67 static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr,
68                                               unsigned size)
69 {
70     /*
71      * Attempts to read from the MSI address are undefined in
72      * the PCI specifications. For this hardware, the datasheet
73      * specifies that a read from the magic address is simply not
74      * intercepted by the MSI controller, and will go out to the
75      * AHB/AXI bus like any other PCI-device-initiated DMA read.
76      * This is not trivial to implement in QEMU, so since
77      * well-behaved guests won't ever ask a PCI device to DMA from
78      * this address we just log the missing functionality.
79      */
80     qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
81     return 0;
82 }
83 
designware_pcie_root_msi_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)84 static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
85                                            uint64_t val, unsigned len)
86 {
87     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
88     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
89 
90     root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
91 
92     if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
93         qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
94     }
95 }
96 
97 static const MemoryRegionOps designware_pci_host_msi_ops = {
98     .read = designware_pcie_root_msi_read,
99     .write = designware_pcie_root_msi_write,
100     .endianness = DEVICE_LITTLE_ENDIAN,
101     .valid = {
102         .min_access_size = 4,
103         .max_access_size = 4,
104     },
105 };
106 
designware_pcie_root_update_msi_mapping(DesignwarePCIERoot * root)107 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)
108 
109 {
110     MemoryRegion *mem   = &root->msi.iomem;
111     const uint64_t base = root->msi.base;
112     const bool enable   = root->msi.intr[0].enable;
113 
114     memory_region_set_address(mem, base);
115     memory_region_set_enabled(mem, enable);
116 }
117 
118 static DesignwarePCIEViewport *
designware_pcie_root_get_current_viewport(DesignwarePCIERoot * root)119 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)
120 {
121     const unsigned int idx = root->atu_viewport & 0xF;
122     const unsigned int dir =
123         !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);
124     return &root->viewports[dir][idx];
125 }
126 
127 static uint32_t
designware_pcie_root_config_read(PCIDevice * d,uint32_t address,int len)128 designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
129 {
130     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
131     DesignwarePCIEViewport *viewport =
132         designware_pcie_root_get_current_viewport(root);
133 
134     uint32_t val;
135 
136     switch (address) {
137     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
138         /*
139          * Linux guest uses this register only to configure number of
140          * PCIE lane (which in our case is irrelevant) and doesn't
141          * really care about the value it reads from this register
142          */
143         val = 0xDEADBEEF;
144         break;
145 
146     case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
147         /*
148          * To make sure that any code in guest waiting for speed
149          * change does not time out we always report
150          * PORT_LOGIC_SPEED_CHANGE as set
151          */
152         val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE;
153         break;
154 
155     case DESIGNWARE_PCIE_MSI_ADDR_LO:
156         val = root->msi.base;
157         break;
158 
159     case DESIGNWARE_PCIE_MSI_ADDR_HI:
160         val = root->msi.base >> 32;
161         break;
162 
163     case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
164         val = root->msi.intr[0].enable;
165         break;
166 
167     case DESIGNWARE_PCIE_MSI_INTR0_MASK:
168         val = root->msi.intr[0].mask;
169         break;
170 
171     case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
172         val = root->msi.intr[0].status;
173         break;
174 
175     case DESIGNWARE_PCIE_PHY_DEBUG_R1:
176         val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
177         break;
178 
179     case DESIGNWARE_PCIE_ATU_VIEWPORT:
180         val = root->atu_viewport;
181         break;
182 
183     case DESIGNWARE_PCIE_ATU_LOWER_BASE:
184         val = viewport->base;
185         break;
186 
187     case DESIGNWARE_PCIE_ATU_UPPER_BASE:
188         val = viewport->base >> 32;
189         break;
190 
191     case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
192         val = viewport->target;
193         break;
194 
195     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
196         val = viewport->target >> 32;
197         break;
198 
199     case DESIGNWARE_PCIE_ATU_LIMIT:
200         val = viewport->limit;
201         break;
202 
203     case DESIGNWARE_PCIE_ATU_CR1:
204     case DESIGNWARE_PCIE_ATU_CR2:
205         val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /
206                            sizeof(uint32_t)];
207         break;
208 
209     default:
210         val = pci_default_read_config(d, address, len);
211         break;
212     }
213 
214     return val;
215 }
216 
designware_pcie_root_data_access(void * opaque,hwaddr addr,uint64_t * val,unsigned len)217 static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr,
218                                                  uint64_t *val, unsigned len)
219 {
220     DesignwarePCIEViewport *viewport = opaque;
221     DesignwarePCIERoot *root = viewport->root;
222 
223     const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
224     const uint8_t devfn  = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
225     PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));
226     PCIDevice *pcidev    = pci_find_device(pcibus, busnum, devfn);
227 
228     if (pcidev) {
229         addr &= pci_config_size(pcidev) - 1;
230 
231         if (val) {
232             pci_host_config_write_common(pcidev, addr,
233                                          pci_config_size(pcidev),
234                                          *val, len);
235         } else {
236             return pci_host_config_read_common(pcidev, addr,
237                                                pci_config_size(pcidev),
238                                                len);
239         }
240     }
241 
242     return UINT64_MAX;
243 }
244 
designware_pcie_root_data_read(void * opaque,hwaddr addr,unsigned len)245 static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr,
246                                                unsigned len)
247 {
248     return designware_pcie_root_data_access(opaque, addr, NULL, len);
249 }
250 
designware_pcie_root_data_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)251 static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
252                                             uint64_t val, unsigned len)
253 {
254     designware_pcie_root_data_access(opaque, addr, &val, len);
255 }
256 
257 static const MemoryRegionOps designware_pci_host_conf_ops = {
258     .read = designware_pcie_root_data_read,
259     .write = designware_pcie_root_data_write,
260     .endianness = DEVICE_LITTLE_ENDIAN,
261     .valid = {
262         .min_access_size = 1,
263         .max_access_size = 4,
264     },
265 };
266 
designware_pcie_update_viewport(DesignwarePCIERoot * root,DesignwarePCIEViewport * viewport)267 static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
268                                             DesignwarePCIEViewport *viewport)
269 {
270     const uint64_t target = viewport->target;
271     const uint64_t base   = viewport->base;
272     const uint64_t size   = (uint64_t)viewport->limit - base + 1;
273     const bool enabled    = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
274 
275     MemoryRegion *current, *other;
276 
277     if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
278         current = &viewport->mem;
279         other   = &viewport->cfg;
280         memory_region_set_alias_offset(current, target);
281     } else {
282         current = &viewport->cfg;
283         other   = &viewport->mem;
284     }
285 
286     /*
287      * An outbound viewport can be reconfigure from being MEM to CFG,
288      * to account for that we disable the "other" memory region that
289      * becomes unused due to that fact.
290      */
291     memory_region_set_enabled(other, false);
292     if (enabled) {
293         memory_region_set_size(current, size);
294         memory_region_set_address(current, base);
295     }
296     memory_region_set_enabled(current, enabled);
297 }
298 
designware_pcie_root_config_write(PCIDevice * d,uint32_t address,uint32_t val,int len)299 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
300                                               uint32_t val, int len)
301 {
302     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
303     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
304     DesignwarePCIEViewport *viewport =
305         designware_pcie_root_get_current_viewport(root);
306 
307     switch (address) {
308     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
309     case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
310     case DESIGNWARE_PCIE_PHY_DEBUG_R1:
311         /* No-op */
312         break;
313 
314     case DESIGNWARE_PCIE_MSI_ADDR_LO:
315         root->msi.base &= 0xFFFFFFFF00000000ULL;
316         root->msi.base |= val;
317         designware_pcie_root_update_msi_mapping(root);
318         break;
319 
320     case DESIGNWARE_PCIE_MSI_ADDR_HI:
321         root->msi.base &= 0x00000000FFFFFFFFULL;
322         root->msi.base |= (uint64_t)val << 32;
323         designware_pcie_root_update_msi_mapping(root);
324         break;
325 
326     case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
327         root->msi.intr[0].enable = val;
328         designware_pcie_root_update_msi_mapping(root);
329         break;
330 
331     case DESIGNWARE_PCIE_MSI_INTR0_MASK:
332         root->msi.intr[0].mask = val;
333         break;
334 
335     case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
336         root->msi.intr[0].status ^= val;
337         if (!root->msi.intr[0].status) {
338             qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
339         }
340         break;
341 
342     case DESIGNWARE_PCIE_ATU_VIEWPORT:
343         val &= DESIGNWARE_PCIE_ATU_REGION_INBOUND |
344                 (DESIGNWARE_PCIE_NUM_VIEWPORTS - 1);
345         root->atu_viewport = val;
346         break;
347 
348     case DESIGNWARE_PCIE_ATU_LOWER_BASE:
349         viewport->base &= 0xFFFFFFFF00000000ULL;
350         viewport->base |= val;
351         break;
352 
353     case DESIGNWARE_PCIE_ATU_UPPER_BASE:
354         viewport->base &= 0x00000000FFFFFFFFULL;
355         viewport->base |= (uint64_t)val << 32;
356         break;
357 
358     case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
359         viewport->target &= 0xFFFFFFFF00000000ULL;
360         viewport->target |= val;
361         break;
362 
363     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
364         viewport->target &= 0x00000000FFFFFFFFULL;
365         viewport->target |= val;
366         break;
367 
368     case DESIGNWARE_PCIE_ATU_LIMIT:
369         viewport->limit = val;
370         break;
371 
372     case DESIGNWARE_PCIE_ATU_CR1:
373         viewport->cr[0] = val;
374         break;
375     case DESIGNWARE_PCIE_ATU_CR2:
376         viewport->cr[1] = val;
377         designware_pcie_update_viewport(root, viewport);
378         break;
379 
380     default:
381         pci_bridge_write_config(d, address, val, len);
382         break;
383     }
384 }
385 
designware_pcie_viewport_name(const char * direction,unsigned int i,const char * type)386 static char *designware_pcie_viewport_name(const char *direction,
387                                            unsigned int i,
388                                            const char *type)
389 {
390     return g_strdup_printf("PCI %s Viewport %u [%s]",
391                            direction, i, type);
392 }
393 
designware_pcie_root_realize(PCIDevice * dev,Error ** errp)394 static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
395 {
396     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
397     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
398     MemoryRegion *address_space = &host->pci.memory;
399     PCIBridge *br = PCI_BRIDGE(dev);
400     DesignwarePCIEViewport *viewport;
401     /*
402      * Dummy values used for initial configuration of MemoryRegions
403      * that belong to a given viewport
404      */
405     const hwaddr dummy_offset = 0;
406     const uint64_t dummy_size = 4;
407     size_t i;
408 
409     br->bus_name  = "dw-pcie";
410 
411     pci_set_word(dev->config + PCI_COMMAND,
412                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
413 
414     pci_config_set_interrupt_pin(dev->config, 1);
415     pci_bridge_initfn(dev, TYPE_PCIE_BUS);
416 
417     pcie_port_init_reg(dev);
418 
419     pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT,
420                   0, &error_fatal);
421 
422     msi_nonbroken = true;
423     msi_init(dev, 0x50, 32, true, true, &error_fatal);
424 
425     for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
426         MemoryRegion *source, *destination, *mem;
427         const char *direction;
428         char *name;
429 
430         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
431         viewport->inbound = true;
432         viewport->base    = 0x0000000000000000ULL;
433         viewport->target  = 0x0000000000000000ULL;
434         viewport->limit   = UINT32_MAX;
435         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
436 
437         source      = &host->pci.address_space_root;
438         destination = get_system_memory();
439         direction   = "Inbound";
440 
441         /*
442          * Configure MemoryRegion implementing PCI -> CPU memory
443          * access
444          */
445         mem  = &viewport->mem;
446         name = designware_pcie_viewport_name(direction, i, "MEM");
447         memory_region_init_alias(mem, OBJECT(root), name, destination,
448                                  dummy_offset, dummy_size);
449         memory_region_add_subregion_overlap(source, dummy_offset, mem, -1);
450         memory_region_set_enabled(mem, false);
451         g_free(name);
452 
453         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
454         viewport->root    = root;
455         viewport->inbound = false;
456         viewport->base    = 0x0000000000000000ULL;
457         viewport->target  = 0x0000000000000000ULL;
458         viewport->limit   = UINT32_MAX;
459         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
460 
461         destination = &host->pci.memory;
462         direction   = "Outbound";
463         source      = get_system_memory();
464 
465         /*
466          * Configure MemoryRegion implementing CPU -> PCI memory
467          * access
468          */
469         mem  = &viewport->mem;
470         name = designware_pcie_viewport_name(direction, i, "MEM");
471         memory_region_init_alias(mem, OBJECT(root), name, destination,
472                                  dummy_offset, dummy_size);
473         memory_region_add_subregion(source, dummy_offset, mem);
474         memory_region_set_enabled(mem, false);
475         g_free(name);
476 
477         /*
478          * Configure MemoryRegion implementing access to configuration
479          * space
480          */
481         mem  = &viewport->cfg;
482         name = designware_pcie_viewport_name(direction, i, "CFG");
483         memory_region_init_io(&viewport->cfg, OBJECT(root),
484                               &designware_pci_host_conf_ops,
485                               viewport, name, dummy_size);
486         memory_region_add_subregion(source, dummy_offset, mem);
487         memory_region_set_enabled(mem, false);
488         g_free(name);
489     }
490 
491     /*
492      * If no inbound iATU windows are configured, HW defaults to
493      * letting inbound TLPs to pass in. We emulate that by explicitly
494      * configuring first inbound window to cover all of target's
495      * address space.
496      *
497      * NOTE: This will not work correctly for the case when first
498      * configured inbound window is window 0
499      */
500     viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
501     viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;
502     designware_pcie_update_viewport(root, viewport);
503 
504     memory_region_init_io(&root->msi.iomem, OBJECT(root),
505                           &designware_pci_host_msi_ops,
506                           root, "pcie-msi", 0x4);
507     /*
508      * We initially place MSI interrupt I/O region at address 0 and
509      * disable it. It'll be later moved to correct offset and enabled
510      * in designware_pcie_root_update_msi_mapping() as a part of
511      * initialization done by guest OS
512      */
513     memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);
514     memory_region_set_enabled(&root->msi.iomem, false);
515 }
516 
designware_pcie_set_irq(void * opaque,int irq_num,int level)517 static void designware_pcie_set_irq(void *opaque, int irq_num, int level)
518 {
519     DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque);
520 
521     qemu_set_irq(host->pci.irqs[irq_num], level);
522 }
523 
524 static const char *
designware_pcie_host_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)525 designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus)
526 {
527     return "0000:00";
528 }
529 
530 static const VMStateDescription vmstate_designware_pcie_msi_bank = {
531     .name = "designware-pcie-msi-bank",
532     .version_id = 1,
533     .minimum_version_id = 1,
534     .fields = (const VMStateField[]) {
535         VMSTATE_UINT32(enable, DesignwarePCIEMSIBank),
536         VMSTATE_UINT32(mask, DesignwarePCIEMSIBank),
537         VMSTATE_UINT32(status, DesignwarePCIEMSIBank),
538         VMSTATE_END_OF_LIST()
539     }
540 };
541 
542 static const VMStateDescription vmstate_designware_pcie_msi = {
543     .name = "designware-pcie-msi",
544     .version_id = 1,
545     .minimum_version_id = 1,
546     .fields = (const VMStateField[]) {
547         VMSTATE_UINT64(base, DesignwarePCIEMSI),
548         VMSTATE_STRUCT_ARRAY(intr,
549                              DesignwarePCIEMSI,
550                              DESIGNWARE_PCIE_NUM_MSI_BANKS,
551                              1,
552                              vmstate_designware_pcie_msi_bank,
553                              DesignwarePCIEMSIBank),
554         VMSTATE_END_OF_LIST()
555     }
556 };
557 
558 static const VMStateDescription vmstate_designware_pcie_viewport = {
559     .name = "designware-pcie-viewport",
560     .version_id = 1,
561     .minimum_version_id = 1,
562     .fields = (const VMStateField[]) {
563         VMSTATE_UINT64(base, DesignwarePCIEViewport),
564         VMSTATE_UINT64(target, DesignwarePCIEViewport),
565         VMSTATE_UINT32(limit, DesignwarePCIEViewport),
566         VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
567         VMSTATE_END_OF_LIST()
568     }
569 };
570 
571 static const VMStateDescription vmstate_designware_pcie_root = {
572     .name = "designware-pcie-root",
573     .version_id = 1,
574     .minimum_version_id = 1,
575     .fields = (const VMStateField[]) {
576         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
577         VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot),
578         VMSTATE_STRUCT_2DARRAY(viewports,
579                                DesignwarePCIERoot,
580                                2,
581                                DESIGNWARE_PCIE_NUM_VIEWPORTS,
582                                1,
583                                vmstate_designware_pcie_viewport,
584                                DesignwarePCIEViewport),
585         VMSTATE_STRUCT(msi,
586                        DesignwarePCIERoot,
587                        1,
588                        vmstate_designware_pcie_msi,
589                        DesignwarePCIEMSI),
590         VMSTATE_END_OF_LIST()
591     }
592 };
593 
designware_pcie_root_class_init(ObjectClass * klass,void * data)594 static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
595 {
596     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
597     DeviceClass *dc = DEVICE_CLASS(klass);
598 
599     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
600 
601     k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
602     k->device_id = 0xABCD;
603     k->revision = 0;
604     k->class_id = PCI_CLASS_BRIDGE_PCI;
605     k->exit = pci_bridge_exitfn;
606     k->realize = designware_pcie_root_realize;
607     k->config_read = designware_pcie_root_config_read;
608     k->config_write = designware_pcie_root_config_write;
609 
610     dc->reset = pci_bridge_reset;
611     /*
612      * PCI-facing part of the host bridge, not usable without the
613      * host-facing part, which can't be device_add'ed, yet.
614      */
615     dc->user_creatable = false;
616     dc->vmsd = &vmstate_designware_pcie_root;
617 }
618 
designware_pcie_host_mmio_read(void * opaque,hwaddr addr,unsigned int size)619 static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
620                                                unsigned int size)
621 {
622     PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
623     PCIDevice *device = pci_find_device(pci->bus, 0, 0);
624 
625     return pci_host_config_read_common(device,
626                                        addr,
627                                        pci_config_size(device),
628                                        size);
629 }
630 
designware_pcie_host_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)631 static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
632                                             uint64_t val, unsigned int size)
633 {
634     PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
635     PCIDevice *device = pci_find_device(pci->bus, 0, 0);
636 
637     return pci_host_config_write_common(device,
638                                         addr,
639                                         pci_config_size(device),
640                                         val, size);
641 }
642 
643 static const MemoryRegionOps designware_pci_mmio_ops = {
644     .read       = designware_pcie_host_mmio_read,
645     .write      = designware_pcie_host_mmio_write,
646     .endianness = DEVICE_LITTLE_ENDIAN,
647     .impl = {
648         /*
649          * Our device would not work correctly if the guest was doing
650          * unaligned access. This might not be a limitation on the real
651          * device but in practice there is no reason for a guest to access
652          * this device unaligned.
653          */
654         .min_access_size = 4,
655         .max_access_size = 4,
656         .unaligned = false,
657     },
658 };
659 
designware_pcie_host_set_iommu(PCIBus * bus,void * opaque,int devfn)660 static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
661                                                     int devfn)
662 {
663     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);
664 
665     return &s->pci.address_space;
666 }
667 
668 static const PCIIOMMUOps designware_iommu_ops = {
669     .get_address_space = designware_pcie_host_set_iommu,
670 };
671 
designware_pcie_host_realize(DeviceState * dev,Error ** errp)672 static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
673 {
674     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
675     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
676     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
677     size_t i;
678 
679     for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
680         sysbus_init_irq(sbd, &s->pci.irqs[i]);
681     }
682 
683     memory_region_init_io(&s->mmio,
684                           OBJECT(s),
685                           &designware_pci_mmio_ops,
686                           s,
687                           "pcie.reg", 4 * 1024);
688     sysbus_init_mmio(sbd, &s->mmio);
689 
690     memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
691     memory_region_init(&s->pci.memory, OBJECT(s),
692                        "pcie-bus-memory",
693                        UINT64_MAX);
694 
695     pci->bus = pci_register_root_bus(dev, "pcie",
696                                      designware_pcie_set_irq,
697                                      pci_swizzle_map_irq_fn,
698                                      s,
699                                      &s->pci.memory,
700                                      &s->pci.io,
701                                      0, 4,
702                                      TYPE_PCIE_BUS);
703     pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
704 
705     memory_region_init(&s->pci.address_space_root,
706                        OBJECT(s),
707                        "pcie-bus-address-space-root",
708                        UINT64_MAX);
709     memory_region_add_subregion(&s->pci.address_space_root,
710                                 0x0, &s->pci.memory);
711     address_space_init(&s->pci.address_space,
712                        &s->pci.address_space_root,
713                        "pcie-bus-address-space");
714     pci_setup_iommu(pci->bus, &designware_iommu_ops, s);
715 
716     qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
717 }
718 
719 static const VMStateDescription vmstate_designware_pcie_host = {
720     .name = "designware-pcie-host",
721     .version_id = 1,
722     .minimum_version_id = 1,
723     .fields = (const VMStateField[]) {
724         VMSTATE_STRUCT(root,
725                        DesignwarePCIEHost,
726                        1,
727                        vmstate_designware_pcie_root,
728                        DesignwarePCIERoot),
729         VMSTATE_END_OF_LIST()
730     }
731 };
732 
designware_pcie_host_class_init(ObjectClass * klass,void * data)733 static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
734 {
735     DeviceClass *dc = DEVICE_CLASS(klass);
736     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
737 
738     hc->root_bus_path = designware_pcie_host_root_bus_path;
739     dc->realize = designware_pcie_host_realize;
740     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
741     dc->fw_name = "pci";
742     dc->vmsd = &vmstate_designware_pcie_host;
743 }
744 
designware_pcie_host_init(Object * obj)745 static void designware_pcie_host_init(Object *obj)
746 {
747     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
748     DesignwarePCIERoot *root = &s->root;
749 
750     object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT);
751     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
752     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
753 }
754 
755 static const TypeInfo designware_pcie_root_info = {
756     .name = TYPE_DESIGNWARE_PCIE_ROOT,
757     .parent = TYPE_PCI_BRIDGE,
758     .instance_size = sizeof(DesignwarePCIERoot),
759     .class_init = designware_pcie_root_class_init,
760     .interfaces = (InterfaceInfo[]) {
761         { INTERFACE_PCIE_DEVICE },
762         { }
763     },
764 };
765 
766 static const TypeInfo designware_pcie_host_info = {
767     .name       = TYPE_DESIGNWARE_PCIE_HOST,
768     .parent     = TYPE_PCI_HOST_BRIDGE,
769     .instance_size = sizeof(DesignwarePCIEHost),
770     .instance_init = designware_pcie_host_init,
771     .class_init = designware_pcie_host_class_init,
772 };
773 
designware_pcie_register(void)774 static void designware_pcie_register(void)
775 {
776     type_register_static(&designware_pcie_root_info);
777     type_register_static(&designware_pcie_host_info);
778 }
779 type_init(designware_pcie_register)
780