1 /*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/qemu-print.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "fpu/softfloat-helpers.h"
26 #include "tcg/tcg.h"
27
openrisc_cpu_set_pc(CPUState * cs,vaddr value)28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
29 {
30 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
31
32 cpu->env.pc = value;
33 cpu->env.dflag = 0;
34 }
35
openrisc_cpu_get_pc(CPUState * cs)36 static vaddr openrisc_cpu_get_pc(CPUState *cs)
37 {
38 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
39
40 return cpu->env.pc;
41 }
42
openrisc_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
44 const TranslationBlock *tb)
45 {
46 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
47
48 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
49 cpu->env.pc = tb->pc;
50 }
51
openrisc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)52 static void openrisc_restore_state_to_opc(CPUState *cs,
53 const TranslationBlock *tb,
54 const uint64_t *data)
55 {
56 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
57
58 cpu->env.pc = data[0];
59 cpu->env.dflag = data[1] & 1;
60 if (data[1] & 2) {
61 cpu->env.ppc = cpu->env.pc - 4;
62 }
63 }
64
openrisc_cpu_has_work(CPUState * cs)65 static bool openrisc_cpu_has_work(CPUState *cs)
66 {
67 return cs->interrupt_request & (CPU_INTERRUPT_HARD |
68 CPU_INTERRUPT_TIMER);
69 }
70
openrisc_cpu_mmu_index(CPUState * cs,bool ifetch)71 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
72 {
73 CPUOpenRISCState *env = cpu_env(cs);
74
75 if (env->sr & (ifetch ? SR_IME : SR_DME)) {
76 /* The mmu is enabled; test supervisor state. */
77 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
78 }
79
80 return MMU_NOMMU_IDX; /* mmu is disabled */
81 }
82
openrisc_disas_set_info(CPUState * cpu,disassemble_info * info)83 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
84 {
85 info->print_insn = print_insn_or1k;
86 }
87
openrisc_cpu_reset_hold(Object * obj,ResetType type)88 static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
89 {
90 CPUState *cs = CPU(obj);
91 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
92 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj);
93
94 if (occ->parent_phases.hold) {
95 occ->parent_phases.hold(obj, type);
96 }
97
98 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
99
100 cpu->env.pc = 0x100;
101 cpu->env.sr = SR_FO | SR_SM;
102 cpu->env.lock_addr = -1;
103 cs->exception_index = -1;
104 cpu_set_fpcsr(&cpu->env, 0);
105
106 set_float_detect_tininess(float_tininess_before_rounding,
107 &cpu->env.fp_status);
108
109 #ifndef CONFIG_USER_ONLY
110 cpu->env.picmr = 0x00000000;
111 cpu->env.picsr = 0x00000000;
112
113 cpu->env.ttmr = 0x00000000;
114 #endif
115 }
116
117 #ifndef CONFIG_USER_ONLY
openrisc_cpu_set_irq(void * opaque,int irq,int level)118 static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
119 {
120 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
121 CPUState *cs = CPU(cpu);
122 uint32_t irq_bit;
123
124 if (irq > 31 || irq < 0) {
125 return;
126 }
127
128 irq_bit = 1U << irq;
129
130 if (level) {
131 cpu->env.picsr |= irq_bit;
132 } else {
133 cpu->env.picsr &= ~irq_bit;
134 }
135
136 if (cpu->env.picsr & cpu->env.picmr) {
137 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
138 } else {
139 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
140 }
141 }
142 #endif
143
openrisc_cpu_realizefn(DeviceState * dev,Error ** errp)144 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
145 {
146 CPUState *cs = CPU(dev);
147 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
148 Error *local_err = NULL;
149
150 cpu_exec_realizefn(cs, &local_err);
151 if (local_err != NULL) {
152 error_propagate(errp, local_err);
153 return;
154 }
155
156 qemu_init_vcpu(cs);
157 cpu_reset(cs);
158
159 occ->parent_realize(dev, errp);
160 }
161
openrisc_cpu_initfn(Object * obj)162 static void openrisc_cpu_initfn(Object *obj)
163 {
164 #ifndef CONFIG_USER_ONLY
165 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS);
166 #endif
167 }
168
169 /* CPU models */
170
openrisc_cpu_class_by_name(const char * cpu_model)171 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
172 {
173 ObjectClass *oc;
174 char *typename;
175
176 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
177 oc = object_class_by_name(typename);
178 g_free(typename);
179
180 return oc;
181 }
182
or1200_initfn(Object * obj)183 static void or1200_initfn(Object *obj)
184 {
185 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
186
187 cpu->env.vr = 0x13000008;
188 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
189 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
190 CPUCFGR_EVBARP;
191
192 /* 1Way, TLB_SIZE entries. */
193 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
194 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
195 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
196 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
197 }
198
openrisc_any_initfn(Object * obj)199 static void openrisc_any_initfn(Object *obj)
200 {
201 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
202
203 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */
204 cpu->env.vr2 = 0; /* No version specific id */
205 cpu->env.avr = 0x01030000; /* Architecture v1.3 */
206
207 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
208 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
209 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
210
211 /* 1Way, TLB_SIZE entries. */
212 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
213 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
214 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
215 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
216 }
217
218 #ifndef CONFIG_USER_ONLY
219 #include "hw/core/sysemu-cpu-ops.h"
220
221 static const struct SysemuCPUOps openrisc_sysemu_ops = {
222 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
223 };
224 #endif
225
226 #include "hw/core/tcg-cpu-ops.h"
227
228 static const TCGCPUOps openrisc_tcg_ops = {
229 .initialize = openrisc_translate_init,
230 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
231 .restore_state_to_opc = openrisc_restore_state_to_opc,
232
233 #ifndef CONFIG_USER_ONLY
234 .tlb_fill = openrisc_cpu_tlb_fill,
235 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
236 .cpu_exec_halt = openrisc_cpu_has_work,
237 .do_interrupt = openrisc_cpu_do_interrupt,
238 #endif /* !CONFIG_USER_ONLY */
239 };
240
openrisc_cpu_class_init(ObjectClass * oc,void * data)241 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
242 {
243 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
244 CPUClass *cc = CPU_CLASS(occ);
245 DeviceClass *dc = DEVICE_CLASS(oc);
246 ResettableClass *rc = RESETTABLE_CLASS(oc);
247
248 device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
249 &occ->parent_realize);
250 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL,
251 &occ->parent_phases);
252
253 cc->class_by_name = openrisc_cpu_class_by_name;
254 cc->has_work = openrisc_cpu_has_work;
255 cc->mmu_index = openrisc_cpu_mmu_index;
256 cc->dump_state = openrisc_cpu_dump_state;
257 cc->set_pc = openrisc_cpu_set_pc;
258 cc->get_pc = openrisc_cpu_get_pc;
259 cc->gdb_read_register = openrisc_cpu_gdb_read_register;
260 cc->gdb_write_register = openrisc_cpu_gdb_write_register;
261 #ifndef CONFIG_USER_ONLY
262 dc->vmsd = &vmstate_openrisc_cpu;
263 cc->sysemu_ops = &openrisc_sysemu_ops;
264 #endif
265 cc->gdb_num_core_regs = 32 + 3;
266 cc->disas_set_info = openrisc_disas_set_info;
267 cc->tcg_ops = &openrisc_tcg_ops;
268 }
269
270 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
271 { \
272 .parent = TYPE_OPENRISC_CPU, \
273 .instance_init = initfn, \
274 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
275 }
276
277 static const TypeInfo openrisc_cpus_type_infos[] = {
278 { /* base class should be registered first */
279 .name = TYPE_OPENRISC_CPU,
280 .parent = TYPE_CPU,
281 .instance_size = sizeof(OpenRISCCPU),
282 .instance_align = __alignof(OpenRISCCPU),
283 .instance_init = openrisc_cpu_initfn,
284 .abstract = true,
285 .class_size = sizeof(OpenRISCCPUClass),
286 .class_init = openrisc_cpu_class_init,
287 },
288 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
289 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
290 };
291
292 DEFINE_TYPES(openrisc_cpus_type_infos)
293