xref: /openbmc/linux/include/media/drv-intf/saa7146.h (revision 39d08ab9)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SAA7146__
3 #define __SAA7146__
4 
5 #include <linux/delay.h>	/* for delay-stuff */
6 #include <linux/slab.h>		/* for kmalloc/kfree */
7 #include <linux/pci.h>		/* for pci-config-stuff, vendor ids etc. */
8 #include <linux/init.h>		/* for "__init" */
9 #include <linux/interrupt.h>	/* for IMMEDIATE_BH */
10 #include <linux/kmod.h>		/* for kernel module loader */
11 #include <linux/i2c.h>		/* for i2c subsystem */
12 #include <asm/io.h>		/* for accessing devices */
13 #include <linux/stringify.h>
14 #include <linux/mutex.h>
15 #include <linux/scatterlist.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
18 
19 #include <linux/vmalloc.h>	/* for vmalloc() */
20 #include <linux/mm.h>		/* for vmalloc_to_page() */
21 
22 #define saa7146_write(sxy,adr,dat)    writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr)         readl(sxy->mem+(adr))
24 
25 extern unsigned int saa7146_debug;
26 
27 #ifndef DEBUG_VARIABLE
28 	#define DEBUG_VARIABLE saa7146_debug
29 #endif
30 
31 #define ERR(fmt, ...)	pr_err("%s: " fmt, __func__, ##__VA_ARGS__)
32 
33 #define _DBG(mask, fmt, ...)						\
34 do {									\
35 	if (DEBUG_VARIABLE & mask)					\
36 		pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__);	\
37 } while (0)
38 
39 /* simple debug messages */
40 #define DEB_S(fmt, ...)		_DBG(0x01, fmt, ##__VA_ARGS__)
41 /* more detailed debug messages */
42 #define DEB_D(fmt, ...)		_DBG(0x02, fmt, ##__VA_ARGS__)
43 /* print enter and exit of functions */
44 #define DEB_EE(fmt, ...)	_DBG(0x04, fmt, ##__VA_ARGS__)
45 /* i2c debug messages */
46 #define DEB_I2C(fmt, ...)	_DBG(0x08, fmt, ##__VA_ARGS__)
47 /* vbi debug messages */
48 #define DEB_VBI(fmt, ...)	_DBG(0x10, fmt, ##__VA_ARGS__)
49 /* interrupt debug messages */
50 #define DEB_INT(fmt, ...)	_DBG(0x20, fmt, ##__VA_ARGS__)
51 /* capture debug messages */
52 #define DEB_CAP(fmt, ...)	_DBG(0x40, fmt, ##__VA_ARGS__)
53 
54 #define SAA7146_ISR_CLEAR(x,y) \
55 	saa7146_write(x, ISR, (y));
56 
57 struct module;
58 
59 struct saa7146_dev;
60 struct saa7146_extension;
61 struct saa7146_vv;
62 
63 /* saa7146 page table */
64 struct saa7146_pgtable {
65 	unsigned int	size;
66 	__le32		*cpu;
67 	dma_addr_t	dma;
68 	/* used for offsets for u,v planes for planar capture modes */
69 	unsigned long	offset;
70 	/* used for custom pagetables (used for example by budget dvb cards) */
71 	struct scatterlist *slist;
72 	int		nents;
73 };
74 
75 struct saa7146_pci_extension_data {
76 	struct saa7146_extension *ext;
77 	void *ext_priv;			/* most likely a name string */
78 };
79 
80 #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device)		\
81 	{							\
82 		.vendor    = PCI_VENDOR_ID_PHILIPS,		\
83 		.device	   = PCI_DEVICE_ID_PHILIPS_SAA7146,	\
84 		.subvendor = x_vendor,				\
85 		.subdevice = x_device,				\
86 		.driver_data = (unsigned long)& x_var,		\
87 	}
88 
89 struct saa7146_extension
90 {
91 	char	name[32];		/* name of the device */
92 #define SAA7146_USE_I2C_IRQ	0x1
93 #define SAA7146_I2C_SHORT_DELAY	0x2
94 	int	flags;
95 
96 	/* pairs of subvendor and subdevice ids for
97 	   supported devices, last entry 0xffff, 0xfff */
98 	struct module *module;
99 	struct pci_driver driver;
100 	const struct pci_device_id *pci_tbl;
101 
102 	/* extension functions */
103 	int (*probe)(struct saa7146_dev *);
104 	int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *);
105 	int (*detach)(struct saa7146_dev*);
106 
107 	u32	irq_mask;	/* mask to indicate, which irq-events are handled by the extension */
108 	void	(*irq_func)(struct saa7146_dev*, u32* irq_mask);
109 };
110 
111 struct saa7146_dma
112 {
113 	dma_addr_t	dma_handle;
114 	__le32		*cpu_addr;
115 };
116 
117 struct saa7146_dev
118 {
119 	struct module			*module;
120 
121 	struct v4l2_device		v4l2_dev;
122 	struct v4l2_ctrl_handler	ctrl_handler;
123 
124 	/* different device locks */
125 	spinlock_t			slock;
126 	struct mutex			v4l2_lock;
127 
128 	unsigned char			__iomem *mem;		/* pointer to mapped IO memory */
129 	u32				revision;	/* chip revision; needed for bug-workarounds*/
130 
131 	/* pci-device & irq stuff*/
132 	char				name[32];
133 	struct pci_dev			*pci;
134 	u32				int_todo;
135 	spinlock_t			int_slock;
136 
137 	/* extension handling */
138 	struct saa7146_extension	*ext;		/* indicates if handled by extension */
139 	void				*ext_priv;	/* pointer for extension private use (most likely some private data) */
140 	struct saa7146_ext_vv		*ext_vv_data;
141 
142 	/* per device video/vbi information (if available) */
143 	struct saa7146_vv	*vv_data;
144 	void (*vv_callback)(struct saa7146_dev *dev, unsigned long status);
145 
146 	/* i2c-stuff */
147 	struct mutex			i2c_lock;
148 
149 	u32				i2c_bitrate;
150 	struct saa7146_dma		d_i2c;	/* pointer to i2c memory */
151 	wait_queue_head_t		i2c_wq;
152 	int				i2c_op;
153 
154 	/* memories */
155 	struct saa7146_dma		d_rps0;
156 	struct saa7146_dma		d_rps1;
157 };
158 
to_saa7146_dev(struct v4l2_device * v4l2_dev)159 static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev)
160 {
161 	return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev);
162 }
163 
164 /* from saa7146_i2c.c */
165 int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate);
166 
167 /* from saa7146_core.c */
168 int saa7146_register_extension(struct saa7146_extension*);
169 int saa7146_unregister_extension(struct saa7146_extension*);
170 struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc);
171 int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt);
172 void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt);
173 int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length );
174 void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt);
175 void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt);
176 void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data);
177 int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop);
178 
179 /* some memory sizes */
180 #define SAA7146_I2C_MEM		( 1*PAGE_SIZE)
181 #define SAA7146_RPS_MEM		( 1*PAGE_SIZE)
182 
183 /* some i2c constants */
184 #define SAA7146_I2C_TIMEOUT	100	/* i2c-timeout-value in ms */
185 #define SAA7146_I2C_RETRIES	3	/* how many times shall we retry an i2c-operation? */
186 #define SAA7146_I2C_DELAY	5	/* time we wait after certain i2c-operations */
187 
188 /* unsorted defines */
189 #define ME1    0x0000000800
190 #define PV1    0x0000000008
191 
192 /* gpio defines */
193 #define SAA7146_GPIO_INPUT 0x00
194 #define SAA7146_GPIO_IRQHI 0x10
195 #define SAA7146_GPIO_IRQLO 0x20
196 #define SAA7146_GPIO_IRQHL 0x30
197 #define SAA7146_GPIO_OUTLO 0x40
198 #define SAA7146_GPIO_OUTHI 0x50
199 
200 /* debi defines */
201 #define DEBINOSWAP 0x000e0000
202 
203 /* define for the register programming sequencer (rps) */
204 #define CMD_NOP		0x00000000  /* No operation */
205 #define CMD_CLR_EVENT	0x00000000  /* Clear event */
206 #define CMD_SET_EVENT	0x10000000  /* Set signal event */
207 #define CMD_PAUSE	0x20000000  /* Pause */
208 #define CMD_CHECK_LATE	0x30000000  /* Check late */
209 #define CMD_UPLOAD	0x40000000  /* Upload */
210 #define CMD_STOP	0x50000000  /* Stop */
211 #define CMD_INTERRUPT	0x60000000  /* Interrupt */
212 #define CMD_JUMP	0x80000000  /* Jump */
213 #define CMD_WR_REG	0x90000000  /* Write (load) register */
214 #define CMD_RD_REG	0xa0000000  /* Read (store) register */
215 #define CMD_WR_REG_MASK	0xc0000000  /* Write register with mask */
216 
217 #define CMD_OAN		MASK_27
218 #define CMD_INV		MASK_26
219 #define CMD_SIG4	MASK_25
220 #define CMD_SIG3	MASK_24
221 #define CMD_SIG2	MASK_23
222 #define CMD_SIG1	MASK_22
223 #define CMD_SIG0	MASK_21
224 #define CMD_O_FID_B	MASK_14
225 #define CMD_E_FID_B	MASK_13
226 #define CMD_O_FID_A	MASK_12
227 #define CMD_E_FID_A	MASK_11
228 
229 /* some events and command modifiers for rps1 squarewave generator */
230 #define EVT_HS          (1<<15)     // Source Line Threshold reached
231 #define EVT_VBI_B       (1<<9)      // VSYNC Event
232 #define RPS_OAN         (1<<27)     // 1: OR events, 0: AND events
233 #define RPS_INV         (1<<26)     // Invert (compound) event
234 #define GPIO3_MSK       0xFF000000  // GPIO #3 control bits
235 
236 /* Bit mask constants */
237 #define MASK_00   0x00000001    /* Mask value for bit 0 */
238 #define MASK_01   0x00000002    /* Mask value for bit 1 */
239 #define MASK_02   0x00000004    /* Mask value for bit 2 */
240 #define MASK_03   0x00000008    /* Mask value for bit 3 */
241 #define MASK_04   0x00000010    /* Mask value for bit 4 */
242 #define MASK_05   0x00000020    /* Mask value for bit 5 */
243 #define MASK_06   0x00000040    /* Mask value for bit 6 */
244 #define MASK_07   0x00000080    /* Mask value for bit 7 */
245 #define MASK_08   0x00000100    /* Mask value for bit 8 */
246 #define MASK_09   0x00000200    /* Mask value for bit 9 */
247 #define MASK_10   0x00000400    /* Mask value for bit 10 */
248 #define MASK_11   0x00000800    /* Mask value for bit 11 */
249 #define MASK_12   0x00001000    /* Mask value for bit 12 */
250 #define MASK_13   0x00002000    /* Mask value for bit 13 */
251 #define MASK_14   0x00004000    /* Mask value for bit 14 */
252 #define MASK_15   0x00008000    /* Mask value for bit 15 */
253 #define MASK_16   0x00010000    /* Mask value for bit 16 */
254 #define MASK_17   0x00020000    /* Mask value for bit 17 */
255 #define MASK_18   0x00040000    /* Mask value for bit 18 */
256 #define MASK_19   0x00080000    /* Mask value for bit 19 */
257 #define MASK_20   0x00100000    /* Mask value for bit 20 */
258 #define MASK_21   0x00200000    /* Mask value for bit 21 */
259 #define MASK_22   0x00400000    /* Mask value for bit 22 */
260 #define MASK_23   0x00800000    /* Mask value for bit 23 */
261 #define MASK_24   0x01000000    /* Mask value for bit 24 */
262 #define MASK_25   0x02000000    /* Mask value for bit 25 */
263 #define MASK_26   0x04000000    /* Mask value for bit 26 */
264 #define MASK_27   0x08000000    /* Mask value for bit 27 */
265 #define MASK_28   0x10000000    /* Mask value for bit 28 */
266 #define MASK_29   0x20000000    /* Mask value for bit 29 */
267 #define MASK_30   0x40000000    /* Mask value for bit 30 */
268 #define MASK_31   0x80000000    /* Mask value for bit 31 */
269 
270 #define MASK_B0   0x000000ff    /* Mask value for byte 0 */
271 #define MASK_B1   0x0000ff00    /* Mask value for byte 1 */
272 #define MASK_B2   0x00ff0000    /* Mask value for byte 2 */
273 #define MASK_B3   0xff000000    /* Mask value for byte 3 */
274 
275 #define MASK_W0   0x0000ffff    /* Mask value for word 0 */
276 #define MASK_W1   0xffff0000    /* Mask value for word 1 */
277 
278 #define MASK_PA   0xfffffffc    /* Mask value for physical address */
279 #define MASK_PR   0xfffffffe	/* Mask value for protection register */
280 #define MASK_ER   0xffffffff    /* Mask value for the entire register */
281 
282 #define MASK_NONE 0x00000000    /* No mask */
283 
284 /* register aliases */
285 #define BASE_ODD1         0x00  /* Video DMA 1 registers  */
286 #define BASE_EVEN1        0x04
287 #define PROT_ADDR1        0x08
288 #define PITCH1            0x0C
289 #define BASE_PAGE1        0x10  /* Video DMA 1 base page */
290 #define NUM_LINE_BYTE1    0x14
291 
292 #define BASE_ODD2         0x18  /* Video DMA 2 registers */
293 #define BASE_EVEN2        0x1C
294 #define PROT_ADDR2        0x20
295 #define PITCH2            0x24
296 #define BASE_PAGE2        0x28  /* Video DMA 2 base page */
297 #define NUM_LINE_BYTE2    0x2C
298 
299 #define BASE_ODD3         0x30  /* Video DMA 3 registers */
300 #define BASE_EVEN3        0x34
301 #define PROT_ADDR3        0x38
302 #define PITCH3            0x3C
303 #define BASE_PAGE3        0x40  /* Video DMA 3 base page */
304 #define NUM_LINE_BYTE3    0x44
305 
306 #define PCI_BT_V1         0x48  /* Video/FIFO 1 */
307 #define PCI_BT_V2         0x49  /* Video/FIFO 2 */
308 #define PCI_BT_V3         0x4A  /* Video/FIFO 3 */
309 #define PCI_BT_DEBI       0x4B  /* DEBI */
310 #define PCI_BT_A          0x4C  /* Audio */
311 
312 #define DD1_INIT          0x50  /* Init setting of DD1 interface */
313 
314 #define DD1_STREAM_B      0x54  /* DD1 B video data stream handling */
315 #define DD1_STREAM_A      0x56  /* DD1 A video data stream handling */
316 
317 #define BRS_CTRL          0x58  /* BRS control register */
318 #define HPS_CTRL          0x5C  /* HPS control register */
319 #define HPS_V_SCALE       0x60  /* HPS vertical scale */
320 #define HPS_V_GAIN        0x64  /* HPS vertical ACL and gain */
321 #define HPS_H_PRESCALE    0x68  /* HPS horizontal prescale   */
322 #define HPS_H_SCALE       0x6C  /* HPS horizontal scale */
323 #define BCS_CTRL          0x70  /* BCS control */
324 #define CHROMA_KEY_RANGE  0x74
325 #define CLIP_FORMAT_CTRL  0x78  /* HPS outputs formats & clipping */
326 
327 #define DEBI_CONFIG       0x7C
328 #define DEBI_COMMAND      0x80
329 #define DEBI_PAGE         0x84
330 #define DEBI_AD           0x88
331 
332 #define I2C_TRANSFER      0x8C
333 #define I2C_STATUS        0x90
334 
335 #define BASE_A1_IN        0x94	/* Audio 1 input DMA */
336 #define PROT_A1_IN        0x98
337 #define PAGE_A1_IN        0x9C
338 
339 #define BASE_A1_OUT       0xA0  /* Audio 1 output DMA */
340 #define PROT_A1_OUT       0xA4
341 #define PAGE_A1_OUT       0xA8
342 
343 #define BASE_A2_IN        0xAC  /* Audio 2 input DMA */
344 #define PROT_A2_IN        0xB0
345 #define PAGE_A2_IN        0xB4
346 
347 #define BASE_A2_OUT       0xB8  /* Audio 2 output DMA */
348 #define PROT_A2_OUT       0xBC
349 #define PAGE_A2_OUT       0xC0
350 
351 #define RPS_PAGE0         0xC4  /* RPS task 0 page register */
352 #define RPS_PAGE1         0xC8  /* RPS task 1 page register */
353 
354 #define RPS_THRESH0       0xCC  /* HBI threshold for task 0 */
355 #define RPS_THRESH1       0xD0  /* HBI threshold for task 1 */
356 
357 #define RPS_TOV0          0xD4  /* RPS timeout for task 0 */
358 #define RPS_TOV1          0xD8  /* RPS timeout for task 1 */
359 
360 #define IER               0xDC  /* Interrupt enable register */
361 
362 #define GPIO_CTRL         0xE0  /* GPIO 0-3 register */
363 
364 #define EC1SSR            0xE4  /* Event cnt set 1 source select */
365 #define EC2SSR            0xE8  /* Event cnt set 2 source select */
366 #define ECT1R             0xEC  /* Event cnt set 1 thresholds */
367 #define ECT2R             0xF0  /* Event cnt set 2 thresholds */
368 
369 #define ACON1             0xF4
370 #define ACON2             0xF8
371 
372 #define MC1               0xFC   /* Main control register 1 */
373 #define MC2               0x100  /* Main control register 2  */
374 
375 #define RPS_ADDR0         0x104  /* RPS task 0 address register */
376 #define RPS_ADDR1         0x108  /* RPS task 1 address register */
377 
378 #define ISR               0x10C  /* Interrupt status register */
379 #define PSR               0x110  /* Primary status register */
380 #define SSR               0x114  /* Secondary status register */
381 
382 #define EC1R              0x118  /* Event counter set 1 register */
383 #define EC2R              0x11C  /* Event counter set 2 register */
384 
385 #define PCI_VDP1          0x120  /* Video DMA pointer of FIFO 1 */
386 #define PCI_VDP2          0x124  /* Video DMA pointer of FIFO 2 */
387 #define PCI_VDP3          0x128  /* Video DMA pointer of FIFO 3 */
388 #define PCI_ADP1          0x12C  /* Audio DMA pointer of audio out 1 */
389 #define PCI_ADP2          0x130  /* Audio DMA pointer of audio in 1 */
390 #define PCI_ADP3          0x134  /* Audio DMA pointer of audio out 2 */
391 #define PCI_ADP4          0x138  /* Audio DMA pointer of audio in 2 */
392 #define PCI_DMA_DDP       0x13C  /* DEBI DMA pointer */
393 
394 #define LEVEL_REP         0x140,
395 #define A_TIME_SLOT1      0x180,  /* from 180 - 1BC */
396 #define A_TIME_SLOT2      0x1C0,  /* from 1C0 - 1FC */
397 
398 /* isr masks */
399 #define SPCI_PPEF       0x80000000  /* PCI parity error */
400 #define SPCI_PABO       0x40000000  /* PCI access error (target or master abort) */
401 #define SPCI_PPED       0x20000000  /* PCI parity error on 'real time data' */
402 #define SPCI_RPS_I1     0x10000000  /* Interrupt issued by RPS1 */
403 #define SPCI_RPS_I0     0x08000000  /* Interrupt issued by RPS0 */
404 #define SPCI_RPS_LATE1  0x04000000  /* RPS task 1 is late */
405 #define SPCI_RPS_LATE0  0x02000000  /* RPS task 0 is late */
406 #define SPCI_RPS_E1     0x01000000  /* RPS error from task 1 */
407 #define SPCI_RPS_E0     0x00800000  /* RPS error from task 0 */
408 #define SPCI_RPS_TO1    0x00400000  /* RPS timeout task 1 */
409 #define SPCI_RPS_TO0    0x00200000  /* RPS timeout task 0 */
410 #define SPCI_UPLD       0x00100000  /* RPS in upload */
411 #define SPCI_DEBI_S     0x00080000  /* DEBI status */
412 #define SPCI_DEBI_E     0x00040000  /* DEBI error */
413 #define SPCI_IIC_S      0x00020000  /* I2C status */
414 #define SPCI_IIC_E      0x00010000  /* I2C error */
415 #define SPCI_A2_IN      0x00008000  /* Audio 2 input DMA protection / limit */
416 #define SPCI_A2_OUT     0x00004000  /* Audio 2 output DMA protection / limit */
417 #define SPCI_A1_IN      0x00002000  /* Audio 1 input DMA protection / limit */
418 #define SPCI_A1_OUT     0x00001000  /* Audio 1 output DMA protection / limit */
419 #define SPCI_AFOU       0x00000800  /* Audio FIFO over- / underflow */
420 #define SPCI_V_PE       0x00000400  /* Video protection address */
421 #define SPCI_VFOU       0x00000200  /* Video FIFO over- / underflow */
422 #define SPCI_FIDA       0x00000100  /* Field ID video port A */
423 #define SPCI_FIDB       0x00000080  /* Field ID video port B */
424 #define SPCI_PIN3       0x00000040  /* GPIO pin 3 */
425 #define SPCI_PIN2       0x00000020  /* GPIO pin 2 */
426 #define SPCI_PIN1       0x00000010  /* GPIO pin 1 */
427 #define SPCI_PIN0       0x00000008  /* GPIO pin 0 */
428 #define SPCI_ECS        0x00000004  /* Event counter 1, 2, 4, 5 */
429 #define SPCI_EC3S       0x00000002  /* Event counter 3 */
430 #define SPCI_EC0S       0x00000001  /* Event counter 0 */
431 
432 /* i2c */
433 #define	SAA7146_I2C_ABORT	(1<<7)
434 #define	SAA7146_I2C_SPERR	(1<<6)
435 #define	SAA7146_I2C_APERR	(1<<5)
436 #define	SAA7146_I2C_DTERR	(1<<4)
437 #define	SAA7146_I2C_DRERR	(1<<3)
438 #define	SAA7146_I2C_AL		(1<<2)
439 #define	SAA7146_I2C_ERR		(1<<1)
440 #define	SAA7146_I2C_BUSY	(1<<0)
441 
442 #define	SAA7146_I2C_START	(0x3)
443 #define	SAA7146_I2C_CONT	(0x2)
444 #define	SAA7146_I2C_STOP	(0x1)
445 #define	SAA7146_I2C_NOP		(0x0)
446 
447 #define SAA7146_I2C_BUS_BIT_RATE_6400	(0x500)
448 #define SAA7146_I2C_BUS_BIT_RATE_3200	(0x100)
449 #define SAA7146_I2C_BUS_BIT_RATE_480	(0x400)
450 #define SAA7146_I2C_BUS_BIT_RATE_320	(0x600)
451 #define SAA7146_I2C_BUS_BIT_RATE_240	(0x700)
452 #define SAA7146_I2C_BUS_BIT_RATE_120	(0x000)
453 #define SAA7146_I2C_BUS_BIT_RATE_80	(0x200)
454 #define SAA7146_I2C_BUS_BIT_RATE_60	(0x300)
455 
SAA7146_IER_DISABLE(struct saa7146_dev * x,unsigned y)456 static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y)
457 {
458 	unsigned long flags;
459 	spin_lock_irqsave(&x->int_slock, flags);
460 	saa7146_write(x, IER, saa7146_read(x, IER) & ~y);
461 	spin_unlock_irqrestore(&x->int_slock, flags);
462 }
463 
SAA7146_IER_ENABLE(struct saa7146_dev * x,unsigned y)464 static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y)
465 {
466 	unsigned long flags;
467 	spin_lock_irqsave(&x->int_slock, flags);
468 	saa7146_write(x, IER, saa7146_read(x, IER) | y);
469 	spin_unlock_irqrestore(&x->int_slock, flags);
470 }
471 
472 #endif
473