1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ 14 #define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_SYNC_MNGR_GLBL 19 * (Prototype: SOB_GLBL) 20 ***************************************** 21 */ 22 23 /* DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK */ 24 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_SHIFT 0 25 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK 0x1 26 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_SHIFT 1 27 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_MASK 0x2 28 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_SHIFT 2 29 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_MASK 0x4 30 31 /* DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE */ 32 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_SHIFT 0 33 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK 0x7 34 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_SHIFT 4 35 #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK 0xFFFF0 36 37 /* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L */ 38 #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_SHIFT 0 39 #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_MASK 0xFFF 40 41 /* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H */ 42 #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_SHIFT 0 43 #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_MASK 0xFFFFFFFF 44 45 /* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L */ 46 #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_SHIFT 0 47 #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_MASK 0xFFF 48 49 /* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H */ 50 #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_SHIFT 0 51 #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_MASK 0xFFFFFFFF 52 53 /* DCORE0_SYNC_MNGR_GLBL_ASID_SEC */ 54 #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_SHIFT 0 55 #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_MASK 0xFFFF 56 #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_SHIFT 16 57 #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_MASK 0x10000 58 59 /* DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY */ 60 #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_SHIFT 0 61 #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_MASK 0xFFFF 62 #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_SHIFT 16 63 #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_MASK 0x10000 64 65 /* DCORE0_SYNC_MNGR_GLBL_LBW_DELAY */ 66 #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_SHIFT 0 67 #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_MASK 0xFFFF 68 #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_SHIFT 16 69 #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_MASK 0x10000 70 71 /* DCORE0_SYNC_MNGR_GLBL_PI_SIZE */ 72 #define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_SHIFT 0 73 #define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_MASK 0xFFFFFFFF 74 75 /* DCORE0_SYNC_MNGR_GLBL_SOB_ONLY */ 76 #define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_SHIFT 0 77 #define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK 0x1 78 79 /* DCORE0_SYNC_MNGR_GLBL_CQ_INTR */ 80 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_SHIFT 0 81 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK 0x1 82 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_SHIFT 8 83 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_MASK 0x100 84 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_SHIFT 16 85 #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK 0x3F0000 86 87 /* DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV */ 88 #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_SHIFT 0 89 #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_MASK 0xFFFF 90 #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_SHIFT 16 91 #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_MASK 0x10000 92 93 /* DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE */ 94 #define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_SHIFT 0 95 #define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_MASK 0xFFFFFFFF 96 97 /* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L */ 98 #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_SHIFT 0 99 #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_MASK 0xFFFFFFFF 100 101 /* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H */ 102 #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_SHIFT 0 103 #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_MASK 0xFFFFFFFF 104 105 /* DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2 */ 106 #define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_SHIFT 0 107 #define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_MASK 0xFF 108 109 /* DCORE0_SYNC_MNGR_GLBL_CQ_PI */ 110 #define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_SHIFT 0 111 #define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_MASK 0xFFFFFFFF 112 113 /* DCORE0_SYNC_MNGR_GLBL_CQ_SEC */ 114 #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_SHIFT 0 115 #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK 0x1 116 #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_SHIFT 4 117 #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_MASK 0x10 118 119 /* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L */ 120 #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_SHIFT 0 121 #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_MASK 0xFFFFFFFF 122 123 /* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H */ 124 #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_SHIFT 0 125 #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_MASK 0xFFFFFFFF 126 127 /* DCORE0_SYNC_MNGR_GLBL_LBW_DATA */ 128 #define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_SHIFT 0 129 #define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_MASK 0xFFFFFFFF 130 131 /* DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE */ 132 #define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_SHIFT 0 133 #define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK 0x1 134 135 #endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ */ 136