1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn32/dcn32_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn32/dcn32_resource.h"
35 #include "dcn321_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39
40 #include "dml/dcn321/dcn321_fpu.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn32/dcn32_hubbub.h"
46 #include "dcn32/dcn32_mpc.h"
47 #include "dcn32/dcn32_hubp.h"
48 #include "irq/dcn32/irq_service_dcn32.h"
49 #include "dcn32/dcn32_dpp.h"
50 #include "dcn32/dcn32_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hw_sequencer.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn30/dcn30_dio_stream_encoder.h"
59 #include "dcn32/dcn32_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
63 #include "dcn31/dcn31_apg.h"
64 #include "dcn31/dcn31_dio_link_encoder.h"
65 #include "dcn32/dcn32_dio_link_encoder.h"
66 #include "dcn321_dio_link_encoder.h"
67 #include "dce/dce_clock_source.h"
68 #include "dce/dce_audio.h"
69 #include "dce/dce_hwseq.h"
70 #include "clk_mgr.h"
71 #include "virtual/virtual_stream_encoder.h"
72 #include "dml/display_mode_vba.h"
73 #include "dcn32/dcn32_dccg.h"
74 #include "dcn10/dcn10_resource.h"
75 #include "link.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77
78 #include "dcn30/dcn30_dwb.h"
79 #include "dcn32/dcn32_mmhubbub.h"
80
81 #include "dcn/dcn_3_2_1_offset.h"
82 #include "dcn/dcn_3_2_1_sh_mask.h"
83 #include "nbio/nbio_4_3_0_offset.h"
84
85 #include "reg_helper.h"
86 #include "dce/dmub_abm.h"
87 #include "dce/dmub_psr.h"
88 #include "dce/dce_aux.h"
89 #include "dce/dce_i2c.h"
90
91 #include "dml/dcn30/display_mode_vba_30.h"
92 #include "vm_helper.h"
93 #include "dcn20/dcn20_vmid.h"
94
95 #define DC_LOGGER_INIT(logger)
96
97 enum dcn321_clk_src_array_id {
98 DCN321_CLK_SRC_PLL0,
99 DCN321_CLK_SRC_PLL1,
100 DCN321_CLK_SRC_PLL2,
101 DCN321_CLK_SRC_PLL3,
102 DCN321_CLK_SRC_PLL4,
103 DCN321_CLK_SRC_TOTAL
104 };
105
106 /* begin *********************
107 * macros to expend register list macro defined in HW object header file
108 */
109
110 /* DCN */
111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
112
113 #define BASE(seg) BASE_INNER(seg)
114
115 #define SR(reg_name)\
116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
117 reg ## reg_name
118 #define SR_ARR(reg_name, id)\
119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
120 reg ## reg_name
121 #define SR_ARR_INIT(reg_name, id, value)\
122 REG_STRUCT[id].reg_name = value
123
124 #define SRI(reg_name, block, id)\
125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 reg ## block ## id ## _ ## reg_name
127
128 #define SRI_ARR(reg_name, block, id)\
129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 reg ## block ## id ## _ ## reg_name
131
132 #define SR_ARR_I2C(reg_name, id) \
133 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
134
135 #define SRI_ARR_I2C(reg_name, block, id)\
136 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 reg ## block ## id ## _ ## reg_name
138
139 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
140 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 reg ## block ## id ## _ ## reg_name
142
143 #define SRI2(reg_name, block, id)\
144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
145 reg ## reg_name
146 #define SRI2_ARR(reg_name, block, id)\
147 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
148 reg ## reg_name
149
150 #define SRIR(var_name, reg_name, block, id)\
151 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 reg ## block ## id ## _ ## reg_name
153
154 #define SRII(reg_name, block, id)\
155 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
156 reg ## block ## id ## _ ## reg_name
157
158 #define SRII_ARR_2(reg_name, block, id, inst)\
159 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
161
162 #define SRII_MPC_RMU(reg_name, block, id)\
163 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 reg ## block ## id ## _ ## reg_name
165
166 #define SRII_DWB(reg_name, temp_name, block, id)\
167 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## temp_name
169
170 #define DCCG_SRII(reg_name, block, id)\
171 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
172 reg ## block ## id ## _ ## reg_name
173
174 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
175 .field_name = reg_name ## __ ## field_name ## post_fix
176
177 #define VUPDATE_SRII(reg_name, block, id)\
178 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
179 reg ## reg_name ## _ ## block ## id
180
181 /* NBIO */
182 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
183
184 #define NBIO_BASE(seg) \
185 NBIO_BASE_INNER(seg)
186
187 #define NBIO_SR(reg_name)\
188 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
189 regBIF_BX0_ ## reg_name
190 #define NBIO_SR_ARR(reg_name, id)\
191 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
192 regBIF_BX0_ ## reg_name
193
194 #define CTX ctx
195 #define REG(reg_name) \
196 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
197
198 static struct bios_registers bios_regs;
199
200 #define bios_regs_init() \
201 ( \
202 NBIO_SR(BIOS_SCRATCH_3),\
203 NBIO_SR(BIOS_SCRATCH_6)\
204 )
205
206 #define clk_src_regs_init(index, pllid)\
207 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
208
209 static struct dce110_clk_src_regs clk_src_regs[5];
210
211 static const struct dce110_clk_src_shift cs_shift = {
212 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
213 };
214
215 static const struct dce110_clk_src_mask cs_mask = {
216 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
217 };
218
219 #define abm_regs_init(id)\
220 ABM_DCN32_REG_LIST_RI(id)
221
222 static struct dce_abm_registers abm_regs[4];
223
224 static const struct dce_abm_shift abm_shift = {
225 ABM_MASK_SH_LIST_DCN32(__SHIFT)
226 };
227
228 static const struct dce_abm_mask abm_mask = {
229 ABM_MASK_SH_LIST_DCN32(_MASK)
230 };
231
232 #define audio_regs_init(id)\
233 AUD_COMMON_REG_LIST_RI(id)
234
235 static struct dce_audio_registers audio_regs[5];
236
237 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
238 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
239 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
240 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
241
242 static const struct dce_audio_shift audio_shift = {
243 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
244 };
245
246 static const struct dce_audio_mask audio_mask = {
247 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
248 };
249
250 #define vpg_regs_init(id)\
251 VPG_DCN3_REG_LIST_RI(id)
252
253 static struct dcn30_vpg_registers vpg_regs[10];
254
255 static const struct dcn30_vpg_shift vpg_shift = {
256 DCN3_VPG_MASK_SH_LIST(__SHIFT)
257 };
258
259 static const struct dcn30_vpg_mask vpg_mask = {
260 DCN3_VPG_MASK_SH_LIST(_MASK)
261 };
262
263 #define afmt_regs_init(id)\
264 AFMT_DCN3_REG_LIST_RI(id)
265
266 static struct dcn30_afmt_registers afmt_regs[6];
267
268 static const struct dcn30_afmt_shift afmt_shift = {
269 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
270 };
271
272 static const struct dcn30_afmt_mask afmt_mask = {
273 DCN3_AFMT_MASK_SH_LIST(_MASK)
274 };
275
276 #define apg_regs_init(id)\
277 APG_DCN31_REG_LIST_RI(id)
278
279 static struct dcn31_apg_registers apg_regs[4];
280
281 static const struct dcn31_apg_shift apg_shift = {
282 DCN31_APG_MASK_SH_LIST(__SHIFT)
283 };
284
285 static const struct dcn31_apg_mask apg_mask = {
286 DCN31_APG_MASK_SH_LIST(_MASK)
287 };
288
289 #define stream_enc_regs_init(id)\
290 SE_DCN32_REG_LIST_RI(id)
291
292 static struct dcn10_stream_enc_registers stream_enc_regs[5];
293
294 static const struct dcn10_stream_encoder_shift se_shift = {
295 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
296 };
297
298 static const struct dcn10_stream_encoder_mask se_mask = {
299 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
300 };
301
302
303 #define aux_regs_init(id)\
304 DCN2_AUX_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
307
308 #define hpd_regs_init(id)\
309 HPD_REG_LIST_RI(id)
310
311 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
312
313 #define link_regs_init(id, phyid)\
314 ( \
315 LE_DCN31_REG_LIST_RI(id), \
316 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
317 )
318 /*DPCS_DCN31_REG_LIST(id),*/ \
319
320 static struct dcn10_link_enc_registers link_enc_regs[5];
321
322 static const struct dcn10_link_enc_shift le_shift = {
323 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
324 // DPCS_DCN31_MASK_SH_LIST(__SHIFT)
325 };
326
327 static const struct dcn10_link_enc_mask le_mask = {
328 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
329 // DPCS_DCN31_MASK_SH_LIST(_MASK)
330 };
331
332 #define hpo_dp_stream_encoder_reg_init(id)\
333 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
334
335 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
336
337 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
338 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
339 };
340
341 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
342 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
343 };
344
345
346 #define hpo_dp_link_encoder_reg_init(id)\
347 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
352
353 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
354
355 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
356 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
357 };
358
359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
361 };
362
363 #define dpp_regs_init(id)\
364 DPP_REG_LIST_DCN30_COMMON_RI(id)
365
366 static struct dcn3_dpp_registers dpp_regs[4];
367
368 static const struct dcn3_dpp_shift tf_shift = {
369 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
370 };
371
372 static const struct dcn3_dpp_mask tf_mask = {
373 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
374 };
375
376
377 #define opp_regs_init(id)\
378 OPP_REG_LIST_DCN30_RI(id)
379
380 static struct dcn20_opp_registers opp_regs[4];
381
382 static const struct dcn20_opp_shift opp_shift = {
383 OPP_MASK_SH_LIST_DCN20(__SHIFT)
384 };
385
386 static const struct dcn20_opp_mask opp_mask = {
387 OPP_MASK_SH_LIST_DCN20(_MASK)
388 };
389
390 #define aux_engine_regs_init(id) \
391 ( \
392 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
393 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
394 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
395 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
396 )
397
398 static struct dce110_aux_registers aux_engine_regs[5];
399
400 static const struct dce110_aux_registers_shift aux_shift = {
401 DCN_AUX_MASK_SH_LIST(__SHIFT)
402 };
403
404 static const struct dce110_aux_registers_mask aux_mask = {
405 DCN_AUX_MASK_SH_LIST(_MASK)
406 };
407
408 #define dwbc_regs_dcn3_init(id)\
409 DWBC_COMMON_REG_LIST_DCN30_RI(id)
410
411 static struct dcn30_dwbc_registers dwbc30_regs[1];
412
413 static const struct dcn30_dwbc_shift dwbc30_shift = {
414 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
415 };
416
417 static const struct dcn30_dwbc_mask dwbc30_mask = {
418 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
419 };
420
421 #define mcif_wb_regs_dcn3_init(id)\
422 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
423
424 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
425
426 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
427 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
428 };
429
430 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
432 };
433
434 #define dsc_regsDCN20_init(id)\
435 DSC_REG_LIST_DCN20_RI(id)
436
437 static struct dcn20_dsc_registers dsc_regs[4];
438
439 static const struct dcn20_dsc_shift dsc_shift = {
440 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
441 };
442
443 static const struct dcn20_dsc_mask dsc_mask = {
444 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
445 };
446
447 static struct dcn30_mpc_registers mpc_regs;
448 #define dcn_mpc_regs_init()\
449 MPC_REG_LIST_DCN3_2_RI(0),\
450 MPC_REG_LIST_DCN3_2_RI(1),\
451 MPC_REG_LIST_DCN3_2_RI(2),\
452 MPC_REG_LIST_DCN3_2_RI(3),\
453 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
454 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
455 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
457 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
458
459 static const struct dcn30_mpc_shift mpc_shift = {
460 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
461 };
462
463 static const struct dcn30_mpc_mask mpc_mask = {
464 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
465 };
466
467 #define optc_regs_init(id)\
468 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
469
470 static struct dcn_optc_registers optc_regs[4];
471
472 static const struct dcn_optc_shift optc_shift = {
473 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
474 };
475
476 static const struct dcn_optc_mask optc_mask = {
477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
478 };
479
480 #define hubp_regs_init(id) \
481 HUBP_REG_LIST_DCN32_RI(id)
482
483 static struct dcn_hubp2_registers hubp_regs[4];
484
485 static const struct dcn_hubp2_shift hubp_shift = {
486 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
487 };
488
489 static const struct dcn_hubp2_mask hubp_mask = {
490 HUBP_MASK_SH_LIST_DCN32(_MASK)
491 };
492
493 static struct dcn_hubbub_registers hubbub_reg;
494 #define hubbub_reg_init()\
495 HUBBUB_REG_LIST_DCN32_RI(0)
496
497 static const struct dcn_hubbub_shift hubbub_shift = {
498 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
499 };
500
501 static const struct dcn_hubbub_mask hubbub_mask = {
502 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
503 };
504
505 static struct dccg_registers dccg_regs;
506
507 #define dccg_regs_init()\
508 DCCG_REG_LIST_DCN32_RI()
509
510 static const struct dccg_shift dccg_shift = {
511 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
512 };
513
514 static const struct dccg_mask dccg_mask = {
515 DCCG_MASK_SH_LIST_DCN32(_MASK)
516 };
517
518
519 #define SRII2(reg_name_pre, reg_name_post, id)\
520 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
521 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
522 reg ## reg_name_pre ## id ## _ ## reg_name_post
523
524
525 #define HWSEQ_DCN32_REG_LIST()\
526 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
527 SR(DIO_MEM_PWR_CTRL), \
528 SR(ODM_MEM_PWR_CTRL3), \
529 SR(MMHUBBUB_MEM_PWR_CNTL), \
530 SR(DCCG_GATE_DISABLE_CNTL), \
531 SR(DCCG_GATE_DISABLE_CNTL2), \
532 SR(DCFCLK_CNTL),\
533 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
534 SRII(PIXEL_RATE_CNTL, OTG, 0), \
535 SRII(PIXEL_RATE_CNTL, OTG, 1),\
536 SRII(PIXEL_RATE_CNTL, OTG, 2),\
537 SRII(PIXEL_RATE_CNTL, OTG, 3),\
538 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
539 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
542 SR(MICROSECOND_TIME_BASE_DIV), \
543 SR(MILLISECOND_TIME_BASE_DIV), \
544 SR(DISPCLK_FREQ_CHANGE_CNTL), \
545 SR(RBBMIF_TIMEOUT_DIS), \
546 SR(RBBMIF_TIMEOUT_DIS_2), \
547 SR(DCHUBBUB_CRC_CTRL), \
548 SR(DPP_TOP0_DPP_CRC_CTRL), \
549 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
550 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
551 SR(MPC_CRC_CTRL), \
552 SR(MPC_CRC_RESULT_GB), \
553 SR(MPC_CRC_RESULT_C), \
554 SR(MPC_CRC_RESULT_AR), \
555 SR(DOMAIN0_PG_CONFIG), \
556 SR(DOMAIN1_PG_CONFIG), \
557 SR(DOMAIN2_PG_CONFIG), \
558 SR(DOMAIN3_PG_CONFIG), \
559 SR(DOMAIN16_PG_CONFIG), \
560 SR(DOMAIN17_PG_CONFIG), \
561 SR(DOMAIN18_PG_CONFIG), \
562 SR(DOMAIN19_PG_CONFIG), \
563 SR(DOMAIN0_PG_STATUS), \
564 SR(DOMAIN1_PG_STATUS), \
565 SR(DOMAIN2_PG_STATUS), \
566 SR(DOMAIN3_PG_STATUS), \
567 SR(DOMAIN16_PG_STATUS), \
568 SR(DOMAIN17_PG_STATUS), \
569 SR(DOMAIN18_PG_STATUS), \
570 SR(DOMAIN19_PG_STATUS), \
571 SR(D1VGA_CONTROL), \
572 SR(D2VGA_CONTROL), \
573 SR(D3VGA_CONTROL), \
574 SR(D4VGA_CONTROL), \
575 SR(D5VGA_CONTROL), \
576 SR(D6VGA_CONTROL), \
577 SR(DC_IP_REQUEST_CNTL), \
578 SR(AZALIA_AUDIO_DTO), \
579 SR(AZALIA_CONTROLLER_CLOCK_GATING)
580
581 static struct dce_hwseq_registers hwseq_reg;
582
583 #define hwseq_reg_init()\
584 HWSEQ_DCN32_REG_LIST()
585
586 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
587 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
588 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
589 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
590 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
591 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
592 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
593 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
595 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
599 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
600 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
601 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
602 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
603 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
604 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
605 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
616 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
618 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
619
620 static const struct dce_hwseq_shift hwseq_shift = {
621 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
622 };
623
624 static const struct dce_hwseq_mask hwseq_mask = {
625 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
626 };
627 #define vmid_regs_init(id)\
628 DCN20_VMID_REG_LIST_RI(id)
629
630 static struct dcn_vmid_registers vmid_regs[16];
631
632 static const struct dcn20_vmid_shift vmid_shifts = {
633 DCN20_VMID_MASK_SH_LIST(__SHIFT)
634 };
635
636 static const struct dcn20_vmid_mask vmid_masks = {
637 DCN20_VMID_MASK_SH_LIST(_MASK)
638 };
639
640 static const struct resource_caps res_cap_dcn321 = {
641 .num_timing_generator = 4,
642 .num_opp = 4,
643 .num_video_plane = 4,
644 .num_audio = 5,
645 .num_stream_encoder = 5,
646 .num_hpo_dp_stream_encoder = 4,
647 .num_hpo_dp_link_encoder = 2,
648 .num_pll = 5,
649 .num_dwb = 1,
650 .num_ddc = 5,
651 .num_vmid = 16,
652 .num_mpc_3dlut = 4,
653 .num_dsc = 4,
654 };
655
656 static const struct dc_plane_cap plane_cap = {
657 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
658 .per_pixel_alpha = true,
659
660 .pixel_format_support = {
661 .argb8888 = true,
662 .nv12 = true,
663 .fp16 = true,
664 .p010 = true,
665 .ayuv = false,
666 },
667
668 .max_upscale_factor = {
669 .argb8888 = 16000,
670 .nv12 = 16000,
671 .fp16 = 16000
672 },
673
674 // 6:1 downscaling ratio: 1000/6 = 166.666
675 .max_downscale_factor = {
676 .argb8888 = 167,
677 .nv12 = 167,
678 .fp16 = 167
679 },
680 64,
681 64
682 };
683
684 static const struct dc_debug_options debug_defaults_drv = {
685 .disable_dmcu = true,
686 .force_abm_enable = false,
687 .timing_trace = false,
688 .clock_trace = true,
689 .disable_pplib_clock_request = false,
690 .pipe_split_policy = MPC_SPLIT_AVOID,
691 .force_single_disp_pipe_split = false,
692 .disable_dcc = DCC_ENABLE,
693 .vsr_support = true,
694 .performance_trace = false,
695 .max_downscale_src_width = 7680,/*upto 8K*/
696 .disable_pplib_wm_range = false,
697 .scl_reset_length10 = true,
698 .sanity_checks = false,
699 .underflow_assert_delay_us = 0xFFFFFFFF,
700 .dwb_fi_phase = -1, // -1 = disable,
701 .dmub_command_table = true,
702 .enable_mem_low_power = {
703 .bits = {
704 .vga = false,
705 .i2c = false,
706 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
707 .dscl = false,
708 .cm = false,
709 .mpc = false,
710 .optc = true,
711 }
712 },
713 .use_max_lb = true,
714 .force_disable_subvp = false,
715 .exit_idle_opt_for_cursor_updates = true,
716 .enable_single_display_2to1_odm_policy = true,
717
718 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
719 .enable_double_buffered_dsc_pg_support = true,
720 .enable_dp_dig_pixel_rate_div_policy = 1,
721 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
722 .alloc_extra_way_for_cursor = true,
723 .min_prefetch_in_strobe_ns = 60000, // 60us
724 .disable_unbounded_requesting = false,
725 .override_dispclk_programming = true,
726 .disable_fpo_optimizations = false,
727 .fpo_vactive_margin_us = 2000, // 2000us
728 .disable_fpo_vactive = false,
729 .disable_boot_optimizations = false,
730 .disable_subvp_high_refresh = false,
731 .fpo_vactive_min_active_margin_us = 200,
732 .fpo_vactive_max_blank_us = 1000,
733 .enable_legacy_fast_update = false,
734 .disable_dc_mode_overwrite = true,
735 };
736
dcn321_aux_engine_create(struct dc_context * ctx,uint32_t inst)737 static struct dce_aux *dcn321_aux_engine_create(
738 struct dc_context *ctx,
739 uint32_t inst)
740 {
741 struct aux_engine_dce110 *aux_engine =
742 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
743
744 if (!aux_engine)
745 return NULL;
746
747 #undef REG_STRUCT
748 #define REG_STRUCT aux_engine_regs
749 aux_engine_regs_init(0),
750 aux_engine_regs_init(1),
751 aux_engine_regs_init(2),
752 aux_engine_regs_init(3),
753 aux_engine_regs_init(4);
754
755 dce110_aux_engine_construct(aux_engine, ctx, inst,
756 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
757 &aux_engine_regs[inst],
758 &aux_mask,
759 &aux_shift,
760 ctx->dc->caps.extended_aux_timeout_support);
761
762 return &aux_engine->base;
763 }
764 #define i2c_inst_regs_init(id)\
765 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
766
767 static struct dce_i2c_registers i2c_hw_regs[5];
768
769 static const struct dce_i2c_shift i2c_shifts = {
770 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
771 };
772
773 static const struct dce_i2c_mask i2c_masks = {
774 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
775 };
776
dcn321_i2c_hw_create(struct dc_context * ctx,uint32_t inst)777 static struct dce_i2c_hw *dcn321_i2c_hw_create(
778 struct dc_context *ctx,
779 uint32_t inst)
780 {
781 struct dce_i2c_hw *dce_i2c_hw =
782 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
783
784 if (!dce_i2c_hw)
785 return NULL;
786
787 #undef REG_STRUCT
788 #define REG_STRUCT i2c_hw_regs
789 i2c_inst_regs_init(1),
790 i2c_inst_regs_init(2),
791 i2c_inst_regs_init(3),
792 i2c_inst_regs_init(4),
793 i2c_inst_regs_init(5);
794
795 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
796 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
797
798 return dce_i2c_hw;
799 }
800
dcn321_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)801 static struct clock_source *dcn321_clock_source_create(
802 struct dc_context *ctx,
803 struct dc_bios *bios,
804 enum clock_source_id id,
805 const struct dce110_clk_src_regs *regs,
806 bool dp_clk_src)
807 {
808 struct dce110_clk_src *clk_src =
809 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
810
811 if (!clk_src)
812 return NULL;
813
814 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
815 regs, &cs_shift, &cs_mask)) {
816 clk_src->base.dp_clk_src = dp_clk_src;
817 return &clk_src->base;
818 }
819
820 kfree(clk_src);
821 BREAK_TO_DEBUGGER();
822 return NULL;
823 }
824
dcn321_hubbub_create(struct dc_context * ctx)825 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
826 {
827 int i;
828
829 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
830 GFP_KERNEL);
831
832 if (!hubbub2)
833 return NULL;
834
835 #undef REG_STRUCT
836 #define REG_STRUCT hubbub_reg
837 hubbub_reg_init();
838
839 #undef REG_STRUCT
840 #define REG_STRUCT vmid_regs
841 vmid_regs_init(0),
842 vmid_regs_init(1),
843 vmid_regs_init(2),
844 vmid_regs_init(3),
845 vmid_regs_init(4),
846 vmid_regs_init(5),
847 vmid_regs_init(6),
848 vmid_regs_init(7),
849 vmid_regs_init(8),
850 vmid_regs_init(9),
851 vmid_regs_init(10),
852 vmid_regs_init(11),
853 vmid_regs_init(12),
854 vmid_regs_init(13),
855 vmid_regs_init(14),
856 vmid_regs_init(15);
857
858 hubbub32_construct(hubbub2, ctx,
859 &hubbub_reg,
860 &hubbub_shift,
861 &hubbub_mask,
862 ctx->dc->dml.ip.det_buffer_size_kbytes,
863 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
864 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
865
866
867 for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
868 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
869
870 vmid->ctx = ctx;
871
872 vmid->regs = &vmid_regs[i];
873 vmid->shifts = &vmid_shifts;
874 vmid->masks = &vmid_masks;
875 }
876
877 return &hubbub2->base;
878 }
879
dcn321_hubp_create(struct dc_context * ctx,uint32_t inst)880 static struct hubp *dcn321_hubp_create(
881 struct dc_context *ctx,
882 uint32_t inst)
883 {
884 struct dcn20_hubp *hubp2 =
885 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
886
887 if (!hubp2)
888 return NULL;
889
890 #undef REG_STRUCT
891 #define REG_STRUCT hubp_regs
892 hubp_regs_init(0),
893 hubp_regs_init(1),
894 hubp_regs_init(2),
895 hubp_regs_init(3);
896
897 if (hubp32_construct(hubp2, ctx, inst,
898 &hubp_regs[inst], &hubp_shift, &hubp_mask))
899 return &hubp2->base;
900
901 BREAK_TO_DEBUGGER();
902 kfree(hubp2);
903 return NULL;
904 }
905
dcn321_dpp_destroy(struct dpp ** dpp)906 static void dcn321_dpp_destroy(struct dpp **dpp)
907 {
908 kfree(TO_DCN30_DPP(*dpp));
909 *dpp = NULL;
910 }
911
dcn321_dpp_create(struct dc_context * ctx,uint32_t inst)912 static struct dpp *dcn321_dpp_create(
913 struct dc_context *ctx,
914 uint32_t inst)
915 {
916 struct dcn3_dpp *dpp3 =
917 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
918
919 if (!dpp3)
920 return NULL;
921
922 #undef REG_STRUCT
923 #define REG_STRUCT dpp_regs
924 dpp_regs_init(0),
925 dpp_regs_init(1),
926 dpp_regs_init(2),
927 dpp_regs_init(3);
928
929 if (dpp32_construct(dpp3, ctx, inst,
930 &dpp_regs[inst], &tf_shift, &tf_mask))
931 return &dpp3->base;
932
933 BREAK_TO_DEBUGGER();
934 kfree(dpp3);
935 return NULL;
936 }
937
dcn321_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)938 static struct mpc *dcn321_mpc_create(
939 struct dc_context *ctx,
940 int num_mpcc,
941 int num_rmu)
942 {
943 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
944 GFP_KERNEL);
945
946 if (!mpc30)
947 return NULL;
948
949 #undef REG_STRUCT
950 #define REG_STRUCT mpc_regs
951 dcn_mpc_regs_init();
952
953 dcn32_mpc_construct(mpc30, ctx,
954 &mpc_regs,
955 &mpc_shift,
956 &mpc_mask,
957 num_mpcc,
958 num_rmu);
959
960 return &mpc30->base;
961 }
962
dcn321_opp_create(struct dc_context * ctx,uint32_t inst)963 static struct output_pixel_processor *dcn321_opp_create(
964 struct dc_context *ctx, uint32_t inst)
965 {
966 struct dcn20_opp *opp2 =
967 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
968
969 if (!opp2) {
970 BREAK_TO_DEBUGGER();
971 return NULL;
972 }
973
974 #undef REG_STRUCT
975 #define REG_STRUCT opp_regs
976 opp_regs_init(0),
977 opp_regs_init(1),
978 opp_regs_init(2),
979 opp_regs_init(3);
980
981 dcn20_opp_construct(opp2, ctx, inst,
982 &opp_regs[inst], &opp_shift, &opp_mask);
983 return &opp2->base;
984 }
985
986
dcn321_timing_generator_create(struct dc_context * ctx,uint32_t instance)987 static struct timing_generator *dcn321_timing_generator_create(
988 struct dc_context *ctx,
989 uint32_t instance)
990 {
991 struct optc *tgn10 =
992 kzalloc(sizeof(struct optc), GFP_KERNEL);
993
994 if (!tgn10)
995 return NULL;
996
997 #undef REG_STRUCT
998 #define REG_STRUCT optc_regs
999 optc_regs_init(0),
1000 optc_regs_init(1),
1001 optc_regs_init(2),
1002 optc_regs_init(3);
1003
1004 tgn10->base.inst = instance;
1005 tgn10->base.ctx = ctx;
1006
1007 tgn10->tg_regs = &optc_regs[instance];
1008 tgn10->tg_shift = &optc_shift;
1009 tgn10->tg_mask = &optc_mask;
1010
1011 dcn32_timing_generator_init(tgn10);
1012
1013 return &tgn10->base;
1014 }
1015
1016 static const struct encoder_feature_support link_enc_feature = {
1017 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1018 .max_hdmi_pixel_clock = 600000,
1019 .hdmi_ycbcr420_supported = true,
1020 .dp_ycbcr420_supported = true,
1021 .fec_supported = true,
1022 .flags.bits.IS_HBR2_CAPABLE = true,
1023 .flags.bits.IS_HBR3_CAPABLE = true,
1024 .flags.bits.IS_TPS3_CAPABLE = true,
1025 .flags.bits.IS_TPS4_CAPABLE = true
1026 };
1027
dcn321_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1028 static struct link_encoder *dcn321_link_encoder_create(
1029 struct dc_context *ctx,
1030 const struct encoder_init_data *enc_init_data)
1031 {
1032 struct dcn20_link_encoder *enc20 =
1033 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1034
1035 if (!enc20)
1036 return NULL;
1037
1038 #undef REG_STRUCT
1039 #define REG_STRUCT link_enc_aux_regs
1040 aux_regs_init(0),
1041 aux_regs_init(1),
1042 aux_regs_init(2),
1043 aux_regs_init(3),
1044 aux_regs_init(4);
1045
1046 #undef REG_STRUCT
1047 #define REG_STRUCT link_enc_hpd_regs
1048 hpd_regs_init(0),
1049 hpd_regs_init(1),
1050 hpd_regs_init(2),
1051 hpd_regs_init(3),
1052 hpd_regs_init(4);
1053
1054 #undef REG_STRUCT
1055 #define REG_STRUCT link_enc_regs
1056 link_regs_init(0, A),
1057 link_regs_init(1, B),
1058 link_regs_init(2, C),
1059 link_regs_init(3, D),
1060 link_regs_init(4, E);
1061
1062 dcn321_link_encoder_construct(enc20,
1063 enc_init_data,
1064 &link_enc_feature,
1065 &link_enc_regs[enc_init_data->transmitter],
1066 &link_enc_aux_regs[enc_init_data->channel - 1],
1067 &link_enc_hpd_regs[enc_init_data->hpd_source],
1068 &le_shift,
1069 &le_mask);
1070
1071 return &enc20->enc10.base;
1072 }
1073
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1074 static void read_dce_straps(
1075 struct dc_context *ctx,
1076 struct resource_straps *straps)
1077 {
1078 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1079 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1080
1081 }
1082
dcn321_create_audio(struct dc_context * ctx,unsigned int inst)1083 static struct audio *dcn321_create_audio(
1084 struct dc_context *ctx, unsigned int inst)
1085 {
1086
1087 #undef REG_STRUCT
1088 #define REG_STRUCT audio_regs
1089 audio_regs_init(0),
1090 audio_regs_init(1),
1091 audio_regs_init(2),
1092 audio_regs_init(3),
1093 audio_regs_init(4);
1094
1095 return dce_audio_create(ctx, inst,
1096 &audio_regs[inst], &audio_shift, &audio_mask);
1097 }
1098
dcn321_vpg_create(struct dc_context * ctx,uint32_t inst)1099 static struct vpg *dcn321_vpg_create(
1100 struct dc_context *ctx,
1101 uint32_t inst)
1102 {
1103 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1104
1105 if (!vpg3)
1106 return NULL;
1107
1108 #undef REG_STRUCT
1109 #define REG_STRUCT vpg_regs
1110 vpg_regs_init(0),
1111 vpg_regs_init(1),
1112 vpg_regs_init(2),
1113 vpg_regs_init(3),
1114 vpg_regs_init(4),
1115 vpg_regs_init(5),
1116 vpg_regs_init(6),
1117 vpg_regs_init(7),
1118 vpg_regs_init(8),
1119 vpg_regs_init(9);
1120
1121 vpg3_construct(vpg3, ctx, inst,
1122 &vpg_regs[inst],
1123 &vpg_shift,
1124 &vpg_mask);
1125
1126 return &vpg3->base;
1127 }
1128
dcn321_afmt_create(struct dc_context * ctx,uint32_t inst)1129 static struct afmt *dcn321_afmt_create(
1130 struct dc_context *ctx,
1131 uint32_t inst)
1132 {
1133 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1134
1135 if (!afmt3)
1136 return NULL;
1137
1138 #undef REG_STRUCT
1139 #define REG_STRUCT afmt_regs
1140 afmt_regs_init(0),
1141 afmt_regs_init(1),
1142 afmt_regs_init(2),
1143 afmt_regs_init(3),
1144 afmt_regs_init(4),
1145 afmt_regs_init(5);
1146
1147 afmt3_construct(afmt3, ctx, inst,
1148 &afmt_regs[inst],
1149 &afmt_shift,
1150 &afmt_mask);
1151
1152 return &afmt3->base;
1153 }
1154
dcn321_apg_create(struct dc_context * ctx,uint32_t inst)1155 static struct apg *dcn321_apg_create(
1156 struct dc_context *ctx,
1157 uint32_t inst)
1158 {
1159 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1160
1161 if (!apg31)
1162 return NULL;
1163
1164 #undef REG_STRUCT
1165 #define REG_STRUCT apg_regs
1166 apg_regs_init(0),
1167 apg_regs_init(1),
1168 apg_regs_init(2),
1169 apg_regs_init(3);
1170
1171 apg31_construct(apg31, ctx, inst,
1172 &apg_regs[inst],
1173 &apg_shift,
1174 &apg_mask);
1175
1176 return &apg31->base;
1177 }
1178
dcn321_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1179 static struct stream_encoder *dcn321_stream_encoder_create(
1180 enum engine_id eng_id,
1181 struct dc_context *ctx)
1182 {
1183 struct dcn10_stream_encoder *enc1;
1184 struct vpg *vpg;
1185 struct afmt *afmt;
1186 int vpg_inst;
1187 int afmt_inst;
1188
1189 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1190 if (eng_id <= ENGINE_ID_DIGF) {
1191 vpg_inst = eng_id;
1192 afmt_inst = eng_id;
1193 } else
1194 return NULL;
1195
1196 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1197 vpg = dcn321_vpg_create(ctx, vpg_inst);
1198 afmt = dcn321_afmt_create(ctx, afmt_inst);
1199
1200 if (!enc1 || !vpg || !afmt) {
1201 kfree(enc1);
1202 kfree(vpg);
1203 kfree(afmt);
1204 return NULL;
1205 }
1206
1207 #undef REG_STRUCT
1208 #define REG_STRUCT stream_enc_regs
1209 stream_enc_regs_init(0),
1210 stream_enc_regs_init(1),
1211 stream_enc_regs_init(2),
1212 stream_enc_regs_init(3),
1213 stream_enc_regs_init(4);
1214
1215 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1216 eng_id, vpg, afmt,
1217 &stream_enc_regs[eng_id],
1218 &se_shift, &se_mask);
1219
1220 return &enc1->base;
1221 }
1222
dcn321_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1223 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1224 enum engine_id eng_id,
1225 struct dc_context *ctx)
1226 {
1227 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1228 struct vpg *vpg;
1229 struct apg *apg;
1230 uint32_t hpo_dp_inst;
1231 uint32_t vpg_inst;
1232 uint32_t apg_inst;
1233
1234 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1235 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1236
1237 /* Mapping of VPG register blocks to HPO DP block instance:
1238 * VPG[6] -> HPO_DP[0]
1239 * VPG[7] -> HPO_DP[1]
1240 * VPG[8] -> HPO_DP[2]
1241 * VPG[9] -> HPO_DP[3]
1242 */
1243 vpg_inst = hpo_dp_inst + 6;
1244
1245 /* Mapping of APG register blocks to HPO DP block instance:
1246 * APG[0] -> HPO_DP[0]
1247 * APG[1] -> HPO_DP[1]
1248 * APG[2] -> HPO_DP[2]
1249 * APG[3] -> HPO_DP[3]
1250 */
1251 apg_inst = hpo_dp_inst;
1252
1253 /* allocate HPO stream encoder and create VPG sub-block */
1254 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1255 vpg = dcn321_vpg_create(ctx, vpg_inst);
1256 apg = dcn321_apg_create(ctx, apg_inst);
1257
1258 if (!hpo_dp_enc31 || !vpg || !apg) {
1259 kfree(hpo_dp_enc31);
1260 kfree(vpg);
1261 kfree(apg);
1262 return NULL;
1263 }
1264
1265 #undef REG_STRUCT
1266 #define REG_STRUCT hpo_dp_stream_enc_regs
1267 hpo_dp_stream_encoder_reg_init(0),
1268 hpo_dp_stream_encoder_reg_init(1),
1269 hpo_dp_stream_encoder_reg_init(2),
1270 hpo_dp_stream_encoder_reg_init(3);
1271
1272 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1273 hpo_dp_inst, eng_id, vpg, apg,
1274 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1275 &hpo_dp_se_shift, &hpo_dp_se_mask);
1276
1277 return &hpo_dp_enc31->base;
1278 }
1279
dcn321_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1280 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1281 uint8_t inst,
1282 struct dc_context *ctx)
1283 {
1284 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1285
1286 /* allocate HPO link encoder */
1287 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1288
1289 #undef REG_STRUCT
1290 #define REG_STRUCT hpo_dp_link_enc_regs
1291 hpo_dp_link_encoder_reg_init(0),
1292 hpo_dp_link_encoder_reg_init(1);
1293
1294 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1295 &hpo_dp_link_enc_regs[inst],
1296 &hpo_dp_le_shift, &hpo_dp_le_mask);
1297
1298 return &hpo_dp_enc31->base;
1299 }
1300
dcn321_hwseq_create(struct dc_context * ctx)1301 static struct dce_hwseq *dcn321_hwseq_create(
1302 struct dc_context *ctx)
1303 {
1304 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1305
1306 #undef REG_STRUCT
1307 #define REG_STRUCT hwseq_reg
1308 hwseq_reg_init();
1309
1310 if (hws) {
1311 hws->ctx = ctx;
1312 hws->regs = &hwseq_reg;
1313 hws->shifts = &hwseq_shift;
1314 hws->masks = &hwseq_mask;
1315 }
1316 return hws;
1317 }
1318 static const struct resource_create_funcs res_create_funcs = {
1319 .read_dce_straps = read_dce_straps,
1320 .create_audio = dcn321_create_audio,
1321 .create_stream_encoder = dcn321_stream_encoder_create,
1322 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1323 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1324 .create_hwseq = dcn321_hwseq_create,
1325 };
1326
dcn321_resource_destruct(struct dcn321_resource_pool * pool)1327 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1328 {
1329 unsigned int i;
1330
1331 for (i = 0; i < pool->base.stream_enc_count; i++) {
1332 if (pool->base.stream_enc[i] != NULL) {
1333 if (pool->base.stream_enc[i]->vpg != NULL) {
1334 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1335 pool->base.stream_enc[i]->vpg = NULL;
1336 }
1337 if (pool->base.stream_enc[i]->afmt != NULL) {
1338 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1339 pool->base.stream_enc[i]->afmt = NULL;
1340 }
1341 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1342 pool->base.stream_enc[i] = NULL;
1343 }
1344 }
1345
1346 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1347 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1348 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1349 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1350 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1351 }
1352 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1353 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1354 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1355 }
1356 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1357 pool->base.hpo_dp_stream_enc[i] = NULL;
1358 }
1359 }
1360
1361 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1362 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1363 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1364 pool->base.hpo_dp_link_enc[i] = NULL;
1365 }
1366 }
1367
1368 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1369 if (pool->base.dscs[i] != NULL)
1370 dcn20_dsc_destroy(&pool->base.dscs[i]);
1371 }
1372
1373 if (pool->base.mpc != NULL) {
1374 kfree(TO_DCN20_MPC(pool->base.mpc));
1375 pool->base.mpc = NULL;
1376 }
1377 if (pool->base.hubbub != NULL) {
1378 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1379 pool->base.hubbub = NULL;
1380 }
1381 for (i = 0; i < pool->base.pipe_count; i++) {
1382 if (pool->base.dpps[i] != NULL)
1383 dcn321_dpp_destroy(&pool->base.dpps[i]);
1384
1385 if (pool->base.ipps[i] != NULL)
1386 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1387
1388 if (pool->base.hubps[i] != NULL) {
1389 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1390 pool->base.hubps[i] = NULL;
1391 }
1392
1393 if (pool->base.irqs != NULL)
1394 dal_irq_service_destroy(&pool->base.irqs);
1395 }
1396
1397 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1398 if (pool->base.engines[i] != NULL)
1399 dce110_engine_destroy(&pool->base.engines[i]);
1400 if (pool->base.hw_i2cs[i] != NULL) {
1401 kfree(pool->base.hw_i2cs[i]);
1402 pool->base.hw_i2cs[i] = NULL;
1403 }
1404 if (pool->base.sw_i2cs[i] != NULL) {
1405 kfree(pool->base.sw_i2cs[i]);
1406 pool->base.sw_i2cs[i] = NULL;
1407 }
1408 }
1409
1410 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1411 if (pool->base.opps[i] != NULL)
1412 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1413 }
1414
1415 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1416 if (pool->base.timing_generators[i] != NULL) {
1417 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1418 pool->base.timing_generators[i] = NULL;
1419 }
1420 }
1421
1422 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1423 if (pool->base.dwbc[i] != NULL) {
1424 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1425 pool->base.dwbc[i] = NULL;
1426 }
1427 if (pool->base.mcif_wb[i] != NULL) {
1428 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1429 pool->base.mcif_wb[i] = NULL;
1430 }
1431 }
1432
1433 for (i = 0; i < pool->base.audio_count; i++) {
1434 if (pool->base.audios[i])
1435 dce_aud_destroy(&pool->base.audios[i]);
1436 }
1437
1438 for (i = 0; i < pool->base.clk_src_count; i++) {
1439 if (pool->base.clock_sources[i] != NULL) {
1440 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1441 pool->base.clock_sources[i] = NULL;
1442 }
1443 }
1444
1445 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1446 if (pool->base.mpc_lut[i] != NULL) {
1447 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1448 pool->base.mpc_lut[i] = NULL;
1449 }
1450 if (pool->base.mpc_shaper[i] != NULL) {
1451 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1452 pool->base.mpc_shaper[i] = NULL;
1453 }
1454 }
1455
1456 if (pool->base.dp_clock_source != NULL) {
1457 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1458 pool->base.dp_clock_source = NULL;
1459 }
1460
1461 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1462 if (pool->base.multiple_abms[i] != NULL)
1463 dce_abm_destroy(&pool->base.multiple_abms[i]);
1464 }
1465
1466 if (pool->base.psr != NULL)
1467 dmub_psr_destroy(&pool->base.psr);
1468
1469 if (pool->base.dccg != NULL)
1470 dcn_dccg_destroy(&pool->base.dccg);
1471
1472 if (pool->base.oem_device != NULL) {
1473 struct dc *dc = pool->base.oem_device->ctx->dc;
1474
1475 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1476 }
1477 }
1478
1479
dcn321_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1480 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1481 {
1482 int i;
1483 uint32_t dwb_count = pool->res_cap->num_dwb;
1484
1485 for (i = 0; i < dwb_count; i++) {
1486 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1487 GFP_KERNEL);
1488
1489 if (!dwbc30) {
1490 dm_error("DC: failed to create dwbc30!\n");
1491 return false;
1492 }
1493
1494 #undef REG_STRUCT
1495 #define REG_STRUCT dwbc30_regs
1496 dwbc_regs_dcn3_init(0);
1497
1498 dcn30_dwbc_construct(dwbc30, ctx,
1499 &dwbc30_regs[i],
1500 &dwbc30_shift,
1501 &dwbc30_mask,
1502 i);
1503
1504 pool->dwbc[i] = &dwbc30->base;
1505 }
1506 return true;
1507 }
1508
dcn321_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1509 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1510 {
1511 int i;
1512 uint32_t dwb_count = pool->res_cap->num_dwb;
1513
1514 for (i = 0; i < dwb_count; i++) {
1515 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1516 GFP_KERNEL);
1517
1518 if (!mcif_wb30) {
1519 dm_error("DC: failed to create mcif_wb30!\n");
1520 return false;
1521 }
1522
1523 #undef REG_STRUCT
1524 #define REG_STRUCT mcif_wb30_regs
1525 mcif_wb_regs_dcn3_init(0);
1526
1527 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1528 &mcif_wb30_regs[i],
1529 &mcif_wb30_shift,
1530 &mcif_wb30_mask,
1531 i);
1532
1533 pool->mcif_wb[i] = &mcif_wb30->base;
1534 }
1535 return true;
1536 }
1537
dcn321_dsc_create(struct dc_context * ctx,uint32_t inst)1538 static struct display_stream_compressor *dcn321_dsc_create(
1539 struct dc_context *ctx, uint32_t inst)
1540 {
1541 struct dcn20_dsc *dsc =
1542 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1543
1544 if (!dsc) {
1545 BREAK_TO_DEBUGGER();
1546 return NULL;
1547 }
1548
1549 #undef REG_STRUCT
1550 #define REG_STRUCT dsc_regs
1551 dsc_regsDCN20_init(0),
1552 dsc_regsDCN20_init(1),
1553 dsc_regsDCN20_init(2),
1554 dsc_regsDCN20_init(3);
1555
1556 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1557
1558 dsc->max_image_width = 6016;
1559
1560 return &dsc->base;
1561 }
1562
dcn321_destroy_resource_pool(struct resource_pool ** pool)1563 static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1564 {
1565 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1566
1567 dcn321_resource_destruct(dcn321_pool);
1568 kfree(dcn321_pool);
1569 *pool = NULL;
1570 }
1571
1572 static struct dc_cap_funcs cap_funcs = {
1573 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1574 };
1575
dcn321_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1576 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1577 {
1578 DC_FP_START();
1579 dcn321_update_bw_bounding_box_fpu(dc, bw_params);
1580 DC_FP_END();
1581 }
1582
1583 static struct resource_funcs dcn321_res_pool_funcs = {
1584 .destroy = dcn321_destroy_resource_pool,
1585 .link_enc_create = dcn321_link_encoder_create,
1586 .link_enc_create_minimal = NULL,
1587 .panel_cntl_create = dcn32_panel_cntl_create,
1588 .validate_bandwidth = dcn32_validate_bandwidth,
1589 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1590 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1591 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1592 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1593 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1594 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1595 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1596 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1597 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1598 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1599 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1600 .update_bw_bounding_box = dcn321_update_bw_bounding_box,
1601 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1602 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1603 .add_phantom_pipes = dcn32_add_phantom_pipes,
1604 .remove_phantom_pipes = dcn32_remove_phantom_pipes,
1605 .retain_phantom_pipes = dcn32_retain_phantom_pipes,
1606 .save_mall_state = dcn32_save_mall_state,
1607 .restore_mall_state = dcn32_restore_mall_state,
1608 };
1609
read_pipe_fuses(struct dc_context * ctx)1610 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1611 {
1612 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1613 /* DCN321 support max 4 pipes */
1614 value = value & 0xf;
1615 return value;
1616 }
1617
1618
dcn321_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn321_resource_pool * pool)1619 static bool dcn321_resource_construct(
1620 uint8_t num_virtual_links,
1621 struct dc *dc,
1622 struct dcn321_resource_pool *pool)
1623 {
1624 int i, j;
1625 struct dc_context *ctx = dc->ctx;
1626 struct irq_service_init_data init_data;
1627 struct ddc_service_init_data ddc_init_data = {0};
1628 uint32_t pipe_fuses = 0;
1629 uint32_t num_pipes = 4;
1630
1631 #undef REG_STRUCT
1632 #define REG_STRUCT bios_regs
1633 bios_regs_init();
1634
1635 #undef REG_STRUCT
1636 #define REG_STRUCT clk_src_regs
1637 clk_src_regs_init(0, A),
1638 clk_src_regs_init(1, B),
1639 clk_src_regs_init(2, C),
1640 clk_src_regs_init(3, D),
1641 clk_src_regs_init(4, E);
1642
1643 #undef REG_STRUCT
1644 #define REG_STRUCT abm_regs
1645 abm_regs_init(0),
1646 abm_regs_init(1),
1647 abm_regs_init(2),
1648 abm_regs_init(3);
1649
1650 #undef REG_STRUCT
1651 #define REG_STRUCT dccg_regs
1652 dccg_regs_init();
1653
1654
1655 ctx->dc_bios->regs = &bios_regs;
1656
1657 pool->base.res_cap = &res_cap_dcn321;
1658 /* max number of pipes for ASIC before checking for pipe fuses */
1659 num_pipes = pool->base.res_cap->num_timing_generator;
1660 pipe_fuses = read_pipe_fuses(ctx);
1661
1662 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1663 if (pipe_fuses & 1 << i)
1664 num_pipes--;
1665
1666 if (pipe_fuses & 1)
1667 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1668
1669 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1670 ASSERT(0); //Entire DCN is harvested!
1671
1672 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1673 * value will be changed, update max_num_dpp and max_num_otg for dml.
1674 */
1675 dcn3_21_ip.max_num_dpp = num_pipes;
1676 dcn3_21_ip.max_num_otg = num_pipes;
1677
1678 pool->base.funcs = &dcn321_res_pool_funcs;
1679
1680 /*************************************************
1681 * Resource + asic cap harcoding *
1682 *************************************************/
1683 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1684 pool->base.timing_generator_count = num_pipes;
1685 pool->base.pipe_count = num_pipes;
1686 pool->base.mpcc_count = num_pipes;
1687 dc->caps.max_downscale_ratio = 600;
1688 dc->caps.i2c_speed_in_khz = 100;
1689 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1690 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1691 dc->caps.max_cursor_size = 64;
1692 dc->caps.min_horizontal_blanking_period = 80;
1693 dc->caps.dmdata_alloc_size = 2048;
1694 dc->caps.mall_size_per_mem_channel = 4;
1695 dc->caps.mall_size_total = 0;
1696 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1697 dc->caps.cache_line_size = 64;
1698 dc->caps.cache_num_ways = 16;
1699
1700 /* Calculate the available MALL space */
1701 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
1702 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1703 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1704 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1705
1706 dc->caps.subvp_fw_processing_delay_us = 15;
1707 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1708 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1709 dc->caps.subvp_swath_height_margin_lines = 16;
1710 dc->caps.subvp_pstate_allow_width_us = 20;
1711 dc->caps.subvp_vertical_int_margin_us = 30;
1712 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1713 dc->caps.max_slave_planes = 2;
1714 dc->caps.max_slave_yuv_planes = 2;
1715 dc->caps.max_slave_rgb_planes = 2;
1716 dc->caps.post_blend_color_processing = true;
1717 dc->caps.force_dp_tps4_for_cp2520 = true;
1718 dc->caps.dp_hpo = true;
1719 dc->caps.dp_hdmi21_pcon_support = true;
1720 dc->caps.edp_dsc_support = true;
1721 dc->caps.extended_aux_timeout_support = true;
1722 dc->caps.dmcub_support = true;
1723 dc->caps.max_v_total = (1 << 15) - 1;
1724
1725 /* Color pipeline capabilities */
1726 dc->caps.color.dpp.dcn_arch = 1;
1727 dc->caps.color.dpp.input_lut_shared = 0;
1728 dc->caps.color.dpp.icsc = 1;
1729 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1730 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1731 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1732 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1733 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1734 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1735 dc->caps.color.dpp.post_csc = 1;
1736 dc->caps.color.dpp.gamma_corr = 1;
1737 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1738
1739 dc->caps.color.dpp.hw_3d_lut = 1;
1740 dc->caps.color.dpp.ogam_ram = 1;
1741 // no OGAM ROM on DCN2 and later ASICs
1742 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1743 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1744 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1745 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1746 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1747 dc->caps.color.dpp.ocsc = 0;
1748
1749 dc->caps.color.mpc.gamut_remap = 1;
1750 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1751 dc->caps.color.mpc.ogam_ram = 1;
1752 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1753 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1754 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1755 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1756 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1757 dc->caps.color.mpc.ocsc = 1;
1758
1759 /* Use pipe context based otg sync logic */
1760 dc->config.use_pipe_ctx_sync_logic = true;
1761
1762 dc->config.dc_mode_clk_limit_support = true;
1763 /* read VBIOS LTTPR caps */
1764 {
1765 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1766 enum bp_result bp_query_result;
1767 uint8_t is_vbios_lttpr_enable = 0;
1768
1769 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1770 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1771 }
1772
1773 /* interop bit is implicit */
1774 {
1775 dc->caps.vbios_lttpr_aware = true;
1776 }
1777 }
1778
1779 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1780 dc->debug = debug_defaults_drv;
1781
1782 // Init the vm_helper
1783 if (dc->vm_helper)
1784 vm_helper_init(dc->vm_helper, 16);
1785
1786 /*************************************************
1787 * Create resources *
1788 *************************************************/
1789
1790 /* Clock Sources for Pixel Clock*/
1791 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
1792 dcn321_clock_source_create(ctx, ctx->dc_bios,
1793 CLOCK_SOURCE_COMBO_PHY_PLL0,
1794 &clk_src_regs[0], false);
1795 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
1796 dcn321_clock_source_create(ctx, ctx->dc_bios,
1797 CLOCK_SOURCE_COMBO_PHY_PLL1,
1798 &clk_src_regs[1], false);
1799 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
1800 dcn321_clock_source_create(ctx, ctx->dc_bios,
1801 CLOCK_SOURCE_COMBO_PHY_PLL2,
1802 &clk_src_regs[2], false);
1803 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
1804 dcn321_clock_source_create(ctx, ctx->dc_bios,
1805 CLOCK_SOURCE_COMBO_PHY_PLL3,
1806 &clk_src_regs[3], false);
1807 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
1808 dcn321_clock_source_create(ctx, ctx->dc_bios,
1809 CLOCK_SOURCE_COMBO_PHY_PLL4,
1810 &clk_src_regs[4], false);
1811
1812 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
1813
1814 /* todo: not reuse phy_pll registers */
1815 pool->base.dp_clock_source =
1816 dcn321_clock_source_create(ctx, ctx->dc_bios,
1817 CLOCK_SOURCE_ID_DP_DTO,
1818 &clk_src_regs[0], true);
1819
1820 for (i = 0; i < pool->base.clk_src_count; i++) {
1821 if (pool->base.clock_sources[i] == NULL) {
1822 dm_error("DC: failed to create clock sources!\n");
1823 BREAK_TO_DEBUGGER();
1824 goto create_fail;
1825 }
1826 }
1827
1828 /* DCCG */
1829 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1830 if (pool->base.dccg == NULL) {
1831 dm_error("DC: failed to create dccg!\n");
1832 BREAK_TO_DEBUGGER();
1833 goto create_fail;
1834 }
1835
1836 /* DML */
1837 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1838
1839 /* IRQ Service */
1840 init_data.ctx = dc->ctx;
1841 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
1842 if (!pool->base.irqs)
1843 goto create_fail;
1844
1845 /* HUBBUB */
1846 pool->base.hubbub = dcn321_hubbub_create(ctx);
1847 if (pool->base.hubbub == NULL) {
1848 BREAK_TO_DEBUGGER();
1849 dm_error("DC: failed to create hubbub!\n");
1850 goto create_fail;
1851 }
1852
1853 /* HUBPs, DPPs, OPPs, TGs, ABMs */
1854 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1855
1856 /* if pipe is disabled, skip instance of HW pipe,
1857 * i.e, skip ASIC register instance
1858 */
1859 if (pipe_fuses & 1 << i)
1860 continue;
1861
1862 pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
1863 if (pool->base.hubps[j] == NULL) {
1864 BREAK_TO_DEBUGGER();
1865 dm_error(
1866 "DC: failed to create hubps!\n");
1867 goto create_fail;
1868 }
1869
1870 pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
1871 if (pool->base.dpps[j] == NULL) {
1872 BREAK_TO_DEBUGGER();
1873 dm_error(
1874 "DC: failed to create dpps!\n");
1875 goto create_fail;
1876 }
1877
1878 pool->base.opps[j] = dcn321_opp_create(ctx, i);
1879 if (pool->base.opps[j] == NULL) {
1880 BREAK_TO_DEBUGGER();
1881 dm_error(
1882 "DC: failed to create output pixel processor!\n");
1883 goto create_fail;
1884 }
1885
1886 pool->base.timing_generators[j] = dcn321_timing_generator_create(
1887 ctx, i);
1888 if (pool->base.timing_generators[j] == NULL) {
1889 BREAK_TO_DEBUGGER();
1890 dm_error("DC: failed to create tg!\n");
1891 goto create_fail;
1892 }
1893
1894 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
1895 &abm_regs[i],
1896 &abm_shift,
1897 &abm_mask);
1898 if (pool->base.multiple_abms[j] == NULL) {
1899 dm_error("DC: failed to create abm for pipe %d!\n", i);
1900 BREAK_TO_DEBUGGER();
1901 goto create_fail;
1902 }
1903
1904 /* index for resource pool arrays for next valid pipe */
1905 j++;
1906 }
1907
1908 /* PSR */
1909 pool->base.psr = dmub_psr_create(ctx);
1910 if (pool->base.psr == NULL) {
1911 dm_error("DC: failed to create psr obj!\n");
1912 BREAK_TO_DEBUGGER();
1913 goto create_fail;
1914 }
1915
1916 /* MPCCs */
1917 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
1918 if (pool->base.mpc == NULL) {
1919 BREAK_TO_DEBUGGER();
1920 dm_error("DC: failed to create mpc!\n");
1921 goto create_fail;
1922 }
1923
1924 /* DSCs */
1925 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1926 pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
1927 if (pool->base.dscs[i] == NULL) {
1928 BREAK_TO_DEBUGGER();
1929 dm_error("DC: failed to create display stream compressor %d!\n", i);
1930 goto create_fail;
1931 }
1932 }
1933
1934 /* DWB */
1935 if (!dcn321_dwbc_create(ctx, &pool->base)) {
1936 BREAK_TO_DEBUGGER();
1937 dm_error("DC: failed to create dwbc!\n");
1938 goto create_fail;
1939 }
1940
1941 /* MMHUBBUB */
1942 if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
1943 BREAK_TO_DEBUGGER();
1944 dm_error("DC: failed to create mcif_wb!\n");
1945 goto create_fail;
1946 }
1947
1948 /* AUX and I2C */
1949 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1950 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
1951 if (pool->base.engines[i] == NULL) {
1952 BREAK_TO_DEBUGGER();
1953 dm_error(
1954 "DC:failed to create aux engine!!\n");
1955 goto create_fail;
1956 }
1957 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
1958 if (pool->base.hw_i2cs[i] == NULL) {
1959 BREAK_TO_DEBUGGER();
1960 dm_error(
1961 "DC:failed to create hw i2c!!\n");
1962 goto create_fail;
1963 }
1964 pool->base.sw_i2cs[i] = NULL;
1965 }
1966
1967 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1968 if (!resource_construct(num_virtual_links, dc, &pool->base,
1969 &res_create_funcs))
1970 goto create_fail;
1971
1972 /* HW Sequencer init functions and Plane caps */
1973 dcn32_hw_sequencer_init_functions(dc);
1974
1975 dc->caps.max_planes = pool->base.pipe_count;
1976
1977 for (i = 0; i < dc->caps.max_planes; ++i)
1978 dc->caps.planes[i] = plane_cap;
1979
1980 dc->cap_funcs = cap_funcs;
1981
1982 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1983 ddc_init_data.ctx = dc->ctx;
1984 ddc_init_data.link = NULL;
1985 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1986 ddc_init_data.id.enum_id = 0;
1987 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1988 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1989 } else {
1990 pool->base.oem_device = NULL;
1991 }
1992
1993 return true;
1994
1995 create_fail:
1996
1997 dcn321_resource_destruct(pool);
1998
1999 return false;
2000 }
2001
dcn321_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2002 struct resource_pool *dcn321_create_resource_pool(
2003 const struct dc_init_data *init_data,
2004 struct dc *dc)
2005 {
2006 struct dcn321_resource_pool *pool =
2007 kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
2008
2009 if (!pool)
2010 return NULL;
2011
2012 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
2013 return &pool->base;
2014
2015 BREAK_TO_DEBUGGER();
2016 kfree(pool);
2017 return NULL;
2018 }
2019