1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
4  *
5  *  Integrated Consumer Infrared Controller
6  *
7  *  Copyright (C) 2010  Andy Walls <awalls@md.metrocast.net>
8  */
9 
10 #include <linux/slab.h>
11 #include <linux/kfifo.h>
12 #include <linux/module.h>
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
15 
16 #include "cx25840-core.h"
17 
18 static unsigned int ir_debug;
19 module_param(ir_debug, int, 0644);
20 MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
21 
22 #define CX25840_IR_REG_BASE	0x200
23 
24 #define CX25840_IR_CNTRL_REG	0x200
25 #define CNTRL_WIN_3_3	0x00000000
26 #define CNTRL_WIN_4_3	0x00000001
27 #define CNTRL_WIN_3_4	0x00000002
28 #define CNTRL_WIN_4_4	0x00000003
29 #define CNTRL_WIN	0x00000003
30 #define CNTRL_EDG_NONE	0x00000000
31 #define CNTRL_EDG_FALL	0x00000004
32 #define CNTRL_EDG_RISE	0x00000008
33 #define CNTRL_EDG_BOTH	0x0000000C
34 #define CNTRL_EDG	0x0000000C
35 #define CNTRL_DMD	0x00000010
36 #define CNTRL_MOD	0x00000020
37 #define CNTRL_RFE	0x00000040
38 #define CNTRL_TFE	0x00000080
39 #define CNTRL_RXE	0x00000100
40 #define CNTRL_TXE	0x00000200
41 #define CNTRL_RIC	0x00000400
42 #define CNTRL_TIC	0x00000800
43 #define CNTRL_CPL	0x00001000
44 #define CNTRL_LBM	0x00002000
45 #define CNTRL_R		0x00004000
46 
47 #define CX25840_IR_TXCLK_REG	0x204
48 #define TXCLK_TCD	0x0000FFFF
49 
50 #define CX25840_IR_RXCLK_REG	0x208
51 #define RXCLK_RCD	0x0000FFFF
52 
53 #define CX25840_IR_CDUTY_REG	0x20C
54 #define CDUTY_CDC	0x0000000F
55 
56 #define CX25840_IR_STATS_REG	0x210
57 #define STATS_RTO	0x00000001
58 #define STATS_ROR	0x00000002
59 #define STATS_RBY	0x00000004
60 #define STATS_TBY	0x00000008
61 #define STATS_RSR	0x00000010
62 #define STATS_TSR	0x00000020
63 
64 #define CX25840_IR_IRQEN_REG	0x214
65 #define IRQEN_RTE	0x00000001
66 #define IRQEN_ROE	0x00000002
67 #define IRQEN_RSE	0x00000010
68 #define IRQEN_TSE	0x00000020
69 #define IRQEN_MSK	0x00000033
70 
71 #define CX25840_IR_FILTR_REG	0x218
72 #define FILTR_LPF	0x0000FFFF
73 
74 #define CX25840_IR_FIFO_REG	0x23C
75 #define FIFO_RXTX	0x0000FFFF
76 #define FIFO_RXTX_LVL	0x00010000
77 #define FIFO_RXTX_RTO	0x0001FFFF
78 #define FIFO_RX_NDV	0x00020000
79 #define FIFO_RX_DEPTH	8
80 #define FIFO_TX_DEPTH	8
81 
82 #define CX25840_VIDCLK_FREQ	108000000 /* 108 MHz, BT.656 */
83 #define CX25840_IR_REFCLK_FREQ	(CX25840_VIDCLK_FREQ / 2)
84 
85 /*
86  * We use this union internally for convenience, but callers to tx_write
87  * and rx_read will be expecting records of type struct ir_raw_event.
88  * Always ensure the size of this union is dictated by struct ir_raw_event.
89  */
90 union cx25840_ir_fifo_rec {
91 	u32 hw_fifo_data;
92 	struct ir_raw_event ir_core_data;
93 };
94 
95 #define CX25840_IR_RX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
96 #define CX25840_IR_TX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
97 
98 struct cx25840_ir_state {
99 	struct i2c_client *c;
100 
101 	struct v4l2_subdev_ir_parameters rx_params;
102 	struct mutex rx_params_lock; /* protects Rx parameter settings cache */
103 	atomic_t rxclk_divider;
104 	atomic_t rx_invert;
105 
106 	struct kfifo rx_kfifo;
107 	spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
108 
109 	struct v4l2_subdev_ir_parameters tx_params;
110 	struct mutex tx_params_lock; /* protects Tx parameter settings cache */
111 	atomic_t txclk_divider;
112 };
113 
to_ir_state(struct v4l2_subdev * sd)114 static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
115 {
116 	struct cx25840_state *state = to_state(sd);
117 	return state ? state->ir_state : NULL;
118 }
119 
120 
121 /*
122  * Rx and Tx Clock Divider register computations
123  *
124  * Note the largest clock divider value of 0xffff corresponds to:
125  *	(0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
126  * which fits in 21 bits, so we'll use unsigned int for time arguments.
127  */
count_to_clock_divider(unsigned int d)128 static inline u16 count_to_clock_divider(unsigned int d)
129 {
130 	if (d > RXCLK_RCD + 1)
131 		d = RXCLK_RCD;
132 	else if (d < 2)
133 		d = 1;
134 	else
135 		d--;
136 	return (u16) d;
137 }
138 
carrier_freq_to_clock_divider(unsigned int freq)139 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
140 {
141 	return count_to_clock_divider(
142 			  DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
143 }
144 
clock_divider_to_carrier_freq(unsigned int divider)145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
146 {
147 	return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
148 }
149 
clock_divider_to_freq(unsigned int divider,unsigned int rollovers)150 static inline unsigned int clock_divider_to_freq(unsigned int divider,
151 						 unsigned int rollovers)
152 {
153 	return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
154 				 (divider + 1) * rollovers);
155 }
156 
157 /*
158  * Low Pass Filter register calculations
159  *
160  * Note the largest count value of 0xffff corresponds to:
161  *	0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
162  * which fits in 21 bits, so we'll use unsigned int for time arguments.
163  */
count_to_lpf_count(unsigned int d)164 static inline u16 count_to_lpf_count(unsigned int d)
165 {
166 	if (d > FILTR_LPF)
167 		d = FILTR_LPF;
168 	else if (d < 4)
169 		d = 0;
170 	return (u16) d;
171 }
172 
ns_to_lpf_count(unsigned int ns)173 static inline u16 ns_to_lpf_count(unsigned int ns)
174 {
175 	return count_to_lpf_count(
176 		DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
177 }
178 
lpf_count_to_ns(unsigned int count)179 static inline unsigned int lpf_count_to_ns(unsigned int count)
180 {
181 	/* Duration of the Low Pass Filter rejection window in ns */
182 	return DIV_ROUND_CLOSEST(count * 1000,
183 				 CX25840_IR_REFCLK_FREQ / 1000000);
184 }
185 
lpf_count_to_us(unsigned int count)186 static inline unsigned int lpf_count_to_us(unsigned int count)
187 {
188 	/* Duration of the Low Pass Filter rejection window in us */
189 	return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
190 }
191 
192 /*
193  * FIFO register pulse width count computations
194  */
clock_divider_to_resolution(u16 divider)195 static u32 clock_divider_to_resolution(u16 divider)
196 {
197 	/*
198 	 * Resolution is the duration of 1 tick of the readable portion of
199 	 * the pulse width counter as read from the FIFO.  The two lsb's are
200 	 * not readable, hence the << 2.  This function returns ns.
201 	 */
202 	return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
203 				 CX25840_IR_REFCLK_FREQ / 1000000);
204 }
205 
pulse_width_count_to_ns(u16 count,u16 divider)206 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
207 {
208 	u64 n;
209 	u32 rem;
210 
211 	/*
212 	 * The 2 lsb's of the pulse width timer count are not readable, hence
213 	 * the (count << 2) | 0x3
214 	 */
215 	n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
216 	rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000);     /* / MHz => ns */
217 	if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
218 		n++;
219 	return n;
220 }
221 
222 #if 0
223 /* Keep as we will need this for Transmit functionality */
224 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
225 {
226 	u64 n;
227 	u32 d;
228 	u32 rem;
229 
230 	/*
231 	 * The 2 lsb's of the pulse width timer count are not accessible, hence
232 	 * the (1 << 2)
233 	 */
234 	n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
235 	d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
236 	rem = do_div(n, d);
237 	if (rem >= d / 2)
238 		n++;
239 
240 	if (n > FIFO_RXTX)
241 		n = FIFO_RXTX;
242 	else if (n == 0)
243 		n = 1;
244 	return (u16) n;
245 }
246 
247 #endif
pulse_width_count_to_us(u16 count,u16 divider)248 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
249 {
250 	u64 n;
251 	u32 rem;
252 
253 	/*
254 	 * The 2 lsb's of the pulse width timer count are not readable, hence
255 	 * the (count << 2) | 0x3
256 	 */
257 	n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
258 	rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
259 	if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
260 		n++;
261 	return (unsigned int) n;
262 }
263 
264 /*
265  * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
266  *
267  * The total pulse clock count is an 18 bit pulse width timer count as the most
268  * significant part and (up to) 16 bit clock divider count as a modulus.
269  * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
270  * width timer count's least significant bit.
271  */
ns_to_pulse_clocks(u32 ns)272 static u64 ns_to_pulse_clocks(u32 ns)
273 {
274 	u64 clocks;
275 	u32 rem;
276 	clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles  */
277 	rem = do_div(clocks, 1000);                         /* /1000 = cycles */
278 	if (rem >= 1000 / 2)
279 		clocks++;
280 	return clocks;
281 }
282 
pulse_clocks_to_clock_divider(u64 count)283 static u16 pulse_clocks_to_clock_divider(u64 count)
284 {
285 	do_div(count, (FIFO_RXTX << 2) | 0x3);
286 
287 	/* net result needs to be rounded down and decremented by 1 */
288 	if (count > RXCLK_RCD + 1)
289 		count = RXCLK_RCD;
290 	else if (count < 2)
291 		count = 1;
292 	else
293 		count--;
294 	return (u16) count;
295 }
296 
297 /*
298  * IR Control Register helpers
299  */
300 enum tx_fifo_watermark {
301 	TX_FIFO_HALF_EMPTY = 0,
302 	TX_FIFO_EMPTY      = CNTRL_TIC,
303 };
304 
305 enum rx_fifo_watermark {
306 	RX_FIFO_HALF_FULL = 0,
307 	RX_FIFO_NOT_EMPTY = CNTRL_RIC,
308 };
309 
control_tx_irq_watermark(struct i2c_client * c,enum tx_fifo_watermark level)310 static inline void control_tx_irq_watermark(struct i2c_client *c,
311 					    enum tx_fifo_watermark level)
312 {
313 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
314 }
315 
control_rx_irq_watermark(struct i2c_client * c,enum rx_fifo_watermark level)316 static inline void control_rx_irq_watermark(struct i2c_client *c,
317 					    enum rx_fifo_watermark level)
318 {
319 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
320 }
321 
control_tx_enable(struct i2c_client * c,bool enable)322 static inline void control_tx_enable(struct i2c_client *c, bool enable)
323 {
324 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
325 			enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
326 }
327 
control_rx_enable(struct i2c_client * c,bool enable)328 static inline void control_rx_enable(struct i2c_client *c, bool enable)
329 {
330 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
331 			enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
332 }
333 
control_tx_modulation_enable(struct i2c_client * c,bool enable)334 static inline void control_tx_modulation_enable(struct i2c_client *c,
335 						bool enable)
336 {
337 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
338 			enable ? CNTRL_MOD : 0);
339 }
340 
control_rx_demodulation_enable(struct i2c_client * c,bool enable)341 static inline void control_rx_demodulation_enable(struct i2c_client *c,
342 						  bool enable)
343 {
344 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
345 			enable ? CNTRL_DMD : 0);
346 }
347 
control_rx_s_edge_detection(struct i2c_client * c,u32 edge_types)348 static inline void control_rx_s_edge_detection(struct i2c_client *c,
349 					       u32 edge_types)
350 {
351 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
352 			edge_types & CNTRL_EDG_BOTH);
353 }
354 
control_rx_s_carrier_window(struct i2c_client * c,unsigned int carrier,unsigned int * carrier_range_low,unsigned int * carrier_range_high)355 static void control_rx_s_carrier_window(struct i2c_client *c,
356 					unsigned int carrier,
357 					unsigned int *carrier_range_low,
358 					unsigned int *carrier_range_high)
359 {
360 	u32 v;
361 	unsigned int c16 = carrier * 16;
362 
363 	if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
364 		v = CNTRL_WIN_3_4;
365 		*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
366 	} else {
367 		v = CNTRL_WIN_3_3;
368 		*carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
369 	}
370 
371 	if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
372 		v |= CNTRL_WIN_4_3;
373 		*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
374 	} else {
375 		v |= CNTRL_WIN_3_3;
376 		*carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
377 	}
378 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
379 }
380 
control_tx_polarity_invert(struct i2c_client * c,bool invert)381 static inline void control_tx_polarity_invert(struct i2c_client *c,
382 					      bool invert)
383 {
384 	cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
385 			invert ? CNTRL_CPL : 0);
386 }
387 
388 /*
389  * IR Rx & Tx Clock Register helpers
390  */
txclk_tx_s_carrier(struct i2c_client * c,unsigned int freq,u16 * divider)391 static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
392 				       unsigned int freq,
393 				       u16 *divider)
394 {
395 	*divider = carrier_freq_to_clock_divider(freq);
396 	cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
397 	return clock_divider_to_carrier_freq(*divider);
398 }
399 
rxclk_rx_s_carrier(struct i2c_client * c,unsigned int freq,u16 * divider)400 static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
401 				       unsigned int freq,
402 				       u16 *divider)
403 {
404 	*divider = carrier_freq_to_clock_divider(freq);
405 	cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
406 	return clock_divider_to_carrier_freq(*divider);
407 }
408 
txclk_tx_s_max_pulse_width(struct i2c_client * c,u32 ns,u16 * divider)409 static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
410 				      u16 *divider)
411 {
412 	u64 pulse_clocks;
413 
414 	if (ns > IR_MAX_DURATION)
415 		ns = IR_MAX_DURATION;
416 	pulse_clocks = ns_to_pulse_clocks(ns);
417 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
418 	cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
419 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
420 }
421 
rxclk_rx_s_max_pulse_width(struct i2c_client * c,u32 ns,u16 * divider)422 static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
423 				      u16 *divider)
424 {
425 	u64 pulse_clocks;
426 
427 	if (ns > IR_MAX_DURATION)
428 		ns = IR_MAX_DURATION;
429 	pulse_clocks = ns_to_pulse_clocks(ns);
430 	*divider = pulse_clocks_to_clock_divider(pulse_clocks);
431 	cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
432 	return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
433 }
434 
435 /*
436  * IR Tx Carrier Duty Cycle register helpers
437  */
cduty_tx_s_duty_cycle(struct i2c_client * c,unsigned int duty_cycle)438 static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
439 					  unsigned int duty_cycle)
440 {
441 	u32 n;
442 	n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
443 	if (n != 0)
444 		n--;
445 	if (n > 15)
446 		n = 15;
447 	cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
448 	return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
449 }
450 
451 /*
452  * IR Filter Register helpers
453  */
filter_rx_s_min_width(struct i2c_client * c,u32 min_width_ns)454 static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
455 {
456 	u32 count = ns_to_lpf_count(min_width_ns);
457 	cx25840_write4(c, CX25840_IR_FILTR_REG, count);
458 	return lpf_count_to_ns(count);
459 }
460 
461 /*
462  * IR IRQ Enable Register helpers
463  */
irqenable_rx(struct v4l2_subdev * sd,u32 mask)464 static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
465 {
466 	struct cx25840_state *state = to_state(sd);
467 
468 	if (is_cx23885(state) || is_cx23887(state))
469 		mask ^= IRQEN_MSK;
470 	mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
471 	cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
472 			~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
473 }
474 
irqenable_tx(struct v4l2_subdev * sd,u32 mask)475 static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
476 {
477 	struct cx25840_state *state = to_state(sd);
478 
479 	if (is_cx23885(state) || is_cx23887(state))
480 		mask ^= IRQEN_MSK;
481 	mask &= IRQEN_TSE;
482 	cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
483 }
484 
485 /*
486  * V4L2 Subdevice IR Ops
487  */
cx25840_ir_irq_handler(struct v4l2_subdev * sd,u32 status,bool * handled)488 int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
489 {
490 	struct cx25840_state *state = to_state(sd);
491 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
492 	struct i2c_client *c = NULL;
493 	unsigned long flags;
494 
495 	union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
496 	unsigned int i, j, k;
497 	u32 events, v;
498 	int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
499 	u32 cntrl, irqen, stats;
500 
501 	*handled = false;
502 	if (ir_state == NULL)
503 		return -ENODEV;
504 
505 	c = ir_state->c;
506 
507 	/* Only support the IR controller for the CX2388[57] AV Core for now */
508 	if (!(is_cx23885(state) || is_cx23887(state)))
509 		return -ENODEV;
510 
511 	cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
512 	irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
513 	if (is_cx23885(state) || is_cx23887(state))
514 		irqen ^= IRQEN_MSK;
515 	stats = cx25840_read4(c, CX25840_IR_STATS_REG);
516 
517 	tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
518 	rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
519 	rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
520 	ror = stats & STATS_ROR; /* Rx FIFO Over Run */
521 
522 	tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
523 	rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
524 	rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
525 	roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
526 
527 	v4l2_dbg(2, ir_debug, sd, "IR IRQ Status:  %s %s %s %s %s %s\n",
528 		 tsr ? "tsr" : "   ", rsr ? "rsr" : "   ",
529 		 rto ? "rto" : "   ", ror ? "ror" : "   ",
530 		 stats & STATS_TBY ? "tby" : "   ",
531 		 stats & STATS_RBY ? "rby" : "   ");
532 
533 	v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
534 		 tse ? "tse" : "   ", rse ? "rse" : "   ",
535 		 rte ? "rte" : "   ", roe ? "roe" : "   ");
536 
537 	/*
538 	 * Transmitter interrupt service
539 	 */
540 	if (tse && tsr) {
541 		/*
542 		 * TODO:
543 		 * Check the watermark threshold setting
544 		 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
545 		 * Push the data to the hardware FIFO.
546 		 * If there was nothing more to send in the tx_kfifo, disable
547 		 *	the TSR IRQ and notify the v4l2_device.
548 		 * If there was something in the tx_kfifo, check the tx_kfifo
549 		 *      level and notify the v4l2_device, if it is low.
550 		 */
551 		/* For now, inhibit TSR interrupt until Tx is implemented */
552 		irqenable_tx(sd, 0);
553 		events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
554 		v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
555 		*handled = true;
556 	}
557 
558 	/*
559 	 * Receiver interrupt service
560 	 */
561 	kror = 0;
562 	if ((rse && rsr) || (rte && rto)) {
563 		/*
564 		 * Receive data on RSR to clear the STATS_RSR.
565 		 * Receive data on RTO, since we may not have yet hit the RSR
566 		 * watermark when we receive the RTO.
567 		 */
568 		for (i = 0, v = FIFO_RX_NDV;
569 		     (v & FIFO_RX_NDV) && !kror; i = 0) {
570 			for (j = 0;
571 			     (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
572 				v = cx25840_read4(c, CX25840_IR_FIFO_REG);
573 				rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
574 				i++;
575 			}
576 			if (i == 0)
577 				break;
578 			j = i * sizeof(union cx25840_ir_fifo_rec);
579 			k = kfifo_in_locked(&ir_state->rx_kfifo,
580 					    (unsigned char *) rx_data, j,
581 					    &ir_state->rx_kfifo_lock);
582 			if (k != j)
583 				kror++; /* rx_kfifo over run */
584 		}
585 		*handled = true;
586 	}
587 
588 	events = 0;
589 	v = 0;
590 	if (kror) {
591 		events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
592 		v4l2_err(sd, "IR receiver software FIFO overrun\n");
593 	}
594 	if (roe && ror) {
595 		/*
596 		 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
597 		 * the Rx FIFO Over Run status (STATS_ROR)
598 		 */
599 		v |= CNTRL_RFE;
600 		events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
601 		v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
602 	}
603 	if (rte && rto) {
604 		/*
605 		 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
606 		 * the Rx Pulse Width Timer Time Out (STATS_RTO)
607 		 */
608 		v |= CNTRL_RXE;
609 		events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
610 	}
611 	if (v) {
612 		/* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
613 		cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
614 		cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
615 		*handled = true;
616 	}
617 	spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
618 	if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
619 		events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
620 	spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
621 
622 	if (events)
623 		v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
624 	return 0;
625 }
626 
627 /* Receiver */
cx25840_ir_rx_read(struct v4l2_subdev * sd,u8 * buf,size_t count,ssize_t * num)628 static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
629 			      ssize_t *num)
630 {
631 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
632 	bool invert;
633 	u16 divider;
634 	unsigned int i, n;
635 	union cx25840_ir_fifo_rec *p;
636 	unsigned u, v, w;
637 
638 	if (ir_state == NULL)
639 		return -ENODEV;
640 
641 	invert = (bool) atomic_read(&ir_state->rx_invert);
642 	divider = (u16) atomic_read(&ir_state->rxclk_divider);
643 
644 	n = count / sizeof(union cx25840_ir_fifo_rec)
645 		* sizeof(union cx25840_ir_fifo_rec);
646 	if (n == 0) {
647 		*num = 0;
648 		return 0;
649 	}
650 
651 	n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
652 			     &ir_state->rx_kfifo_lock);
653 
654 	n /= sizeof(union cx25840_ir_fifo_rec);
655 	*num = n * sizeof(union cx25840_ir_fifo_rec);
656 
657 	for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
658 
659 		if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
660 			/* Assume RTO was because of no IR light input */
661 			u = 0;
662 			w = 1;
663 		} else {
664 			u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
665 			if (invert)
666 				u = u ? 0 : 1;
667 			w = 0;
668 		}
669 
670 		v = (unsigned) pulse_width_count_to_ns(
671 				  (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;
672 		if (v > IR_MAX_DURATION)
673 			v = IR_MAX_DURATION;
674 
675 		p->ir_core_data = (struct ir_raw_event)
676 			{ .pulse = u, .duration = v, .timeout = w };
677 
678 		v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns  %s  %s\n",
679 			 v, u ? "mark" : "space", w ? "(timed out)" : "");
680 		if (w)
681 			v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
682 	}
683 	return 0;
684 }
685 
cx25840_ir_rx_g_parameters(struct v4l2_subdev * sd,struct v4l2_subdev_ir_parameters * p)686 static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
687 				      struct v4l2_subdev_ir_parameters *p)
688 {
689 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
690 
691 	if (ir_state == NULL)
692 		return -ENODEV;
693 
694 	mutex_lock(&ir_state->rx_params_lock);
695 	memcpy(p, &ir_state->rx_params,
696 				      sizeof(struct v4l2_subdev_ir_parameters));
697 	mutex_unlock(&ir_state->rx_params_lock);
698 	return 0;
699 }
700 
cx25840_ir_rx_shutdown(struct v4l2_subdev * sd)701 static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
702 {
703 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
704 	struct i2c_client *c;
705 
706 	if (ir_state == NULL)
707 		return -ENODEV;
708 
709 	c = ir_state->c;
710 	mutex_lock(&ir_state->rx_params_lock);
711 
712 	/* Disable or slow down all IR Rx circuits and counters */
713 	irqenable_rx(sd, 0);
714 	control_rx_enable(c, false);
715 	control_rx_demodulation_enable(c, false);
716 	control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
717 	filter_rx_s_min_width(c, 0);
718 	cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
719 
720 	ir_state->rx_params.shutdown = true;
721 
722 	mutex_unlock(&ir_state->rx_params_lock);
723 	return 0;
724 }
725 
cx25840_ir_rx_s_parameters(struct v4l2_subdev * sd,struct v4l2_subdev_ir_parameters * p)726 static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
727 				      struct v4l2_subdev_ir_parameters *p)
728 {
729 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
730 	struct i2c_client *c;
731 	struct v4l2_subdev_ir_parameters *o;
732 	u16 rxclk_divider;
733 
734 	if (ir_state == NULL)
735 		return -ENODEV;
736 
737 	if (p->shutdown)
738 		return cx25840_ir_rx_shutdown(sd);
739 
740 	if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
741 		return -ENOSYS;
742 
743 	c = ir_state->c;
744 	o = &ir_state->rx_params;
745 
746 	mutex_lock(&ir_state->rx_params_lock);
747 
748 	o->shutdown = p->shutdown;
749 
750 	p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
751 	o->mode = p->mode;
752 
753 	p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
754 	o->bytes_per_data_element = p->bytes_per_data_element;
755 
756 	/* Before we tweak the hardware, we have to disable the receiver */
757 	irqenable_rx(sd, 0);
758 	control_rx_enable(c, false);
759 
760 	control_rx_demodulation_enable(c, p->modulation);
761 	o->modulation = p->modulation;
762 
763 	if (p->modulation) {
764 		p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
765 						     &rxclk_divider);
766 
767 		o->carrier_freq = p->carrier_freq;
768 
769 		p->duty_cycle = 50;
770 		o->duty_cycle = p->duty_cycle;
771 
772 		control_rx_s_carrier_window(c, p->carrier_freq,
773 					    &p->carrier_range_lower,
774 					    &p->carrier_range_upper);
775 		o->carrier_range_lower = p->carrier_range_lower;
776 		o->carrier_range_upper = p->carrier_range_upper;
777 
778 		p->max_pulse_width =
779 			(u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
780 	} else {
781 		p->max_pulse_width =
782 			    rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
783 						       &rxclk_divider);
784 	}
785 	o->max_pulse_width = p->max_pulse_width;
786 	atomic_set(&ir_state->rxclk_divider, rxclk_divider);
787 
788 	p->noise_filter_min_width =
789 			    filter_rx_s_min_width(c, p->noise_filter_min_width);
790 	o->noise_filter_min_width = p->noise_filter_min_width;
791 
792 	p->resolution = clock_divider_to_resolution(rxclk_divider);
793 	o->resolution = p->resolution;
794 
795 	/* FIXME - make this dependent on resolution for better performance */
796 	control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
797 
798 	control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
799 
800 	o->invert_level = p->invert_level;
801 	atomic_set(&ir_state->rx_invert, p->invert_level);
802 
803 	o->interrupt_enable = p->interrupt_enable;
804 	o->enable = p->enable;
805 	if (p->enable) {
806 		unsigned long flags;
807 
808 		spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
809 		kfifo_reset(&ir_state->rx_kfifo);
810 		spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
811 		if (p->interrupt_enable)
812 			irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
813 		control_rx_enable(c, p->enable);
814 	}
815 
816 	mutex_unlock(&ir_state->rx_params_lock);
817 	return 0;
818 }
819 
820 /* Transmitter */
cx25840_ir_tx_write(struct v4l2_subdev * sd,u8 * buf,size_t count,ssize_t * num)821 static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
822 			       ssize_t *num)
823 {
824 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
825 
826 	if (ir_state == NULL)
827 		return -ENODEV;
828 
829 #if 0
830 	/*
831 	 * FIXME - the code below is an incomplete and untested sketch of what
832 	 * may need to be done.  The critical part is to get 4 (or 8) pulses
833 	 * from the tx_kfifo, or converted from ns to the proper units from the
834 	 * input, and push them off to the hardware Tx FIFO right away, if the
835 	 * HW TX fifo needs service.  The rest can be pushed to the tx_kfifo in
836 	 * a less critical timeframe.  Also watch out for overruning the
837 	 * tx_kfifo - don't let it happen and let the caller know not all his
838 	 * pulses were written.
839 	 */
840 	u32 *ns_pulse = (u32 *) buf;
841 	unsigned int n;
842 	u32 fifo_pulse[FIFO_TX_DEPTH];
843 	u32 mark;
844 
845 	/* Compute how much we can fit in the tx kfifo */
846 	n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
847 	n = min(n, (unsigned int) count);
848 	n /= sizeof(u32);
849 
850 	/* FIXME - turn on Tx Fifo service interrupt
851 	 * check hardware fifo level, and other stuff
852 	 */
853 	for (i = 0; i < n; ) {
854 		for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
855 			mark = ns_pulse[i] & LEVEL_MASK;
856 			fifo_pulse[j] = ns_to_pulse_width_count(
857 					 ns_pulse[i] &
858 					       ~LEVEL_MASK,
859 					 ir_state->txclk_divider);
860 			if (mark)
861 				fifo_pulse[j] &= FIFO_RXTX_LVL;
862 			i++;
863 		}
864 		kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
865 							       j * sizeof(u32));
866 	}
867 	*num = n * sizeof(u32);
868 #else
869 	/* For now enable the Tx FIFO Service interrupt & pretend we did work */
870 	irqenable_tx(sd, IRQEN_TSE);
871 	*num = count;
872 #endif
873 	return 0;
874 }
875 
cx25840_ir_tx_g_parameters(struct v4l2_subdev * sd,struct v4l2_subdev_ir_parameters * p)876 static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
877 				      struct v4l2_subdev_ir_parameters *p)
878 {
879 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
880 
881 	if (ir_state == NULL)
882 		return -ENODEV;
883 
884 	mutex_lock(&ir_state->tx_params_lock);
885 	memcpy(p, &ir_state->tx_params,
886 				      sizeof(struct v4l2_subdev_ir_parameters));
887 	mutex_unlock(&ir_state->tx_params_lock);
888 	return 0;
889 }
890 
cx25840_ir_tx_shutdown(struct v4l2_subdev * sd)891 static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
892 {
893 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
894 	struct i2c_client *c;
895 
896 	if (ir_state == NULL)
897 		return -ENODEV;
898 
899 	c = ir_state->c;
900 	mutex_lock(&ir_state->tx_params_lock);
901 
902 	/* Disable or slow down all IR Tx circuits and counters */
903 	irqenable_tx(sd, 0);
904 	control_tx_enable(c, false);
905 	control_tx_modulation_enable(c, false);
906 	cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
907 
908 	ir_state->tx_params.shutdown = true;
909 
910 	mutex_unlock(&ir_state->tx_params_lock);
911 	return 0;
912 }
913 
cx25840_ir_tx_s_parameters(struct v4l2_subdev * sd,struct v4l2_subdev_ir_parameters * p)914 static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
915 				      struct v4l2_subdev_ir_parameters *p)
916 {
917 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
918 	struct i2c_client *c;
919 	struct v4l2_subdev_ir_parameters *o;
920 	u16 txclk_divider;
921 
922 	if (ir_state == NULL)
923 		return -ENODEV;
924 
925 	if (p->shutdown)
926 		return cx25840_ir_tx_shutdown(sd);
927 
928 	if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
929 		return -ENOSYS;
930 
931 	c = ir_state->c;
932 	o = &ir_state->tx_params;
933 	mutex_lock(&ir_state->tx_params_lock);
934 
935 	o->shutdown = p->shutdown;
936 
937 	p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
938 	o->mode = p->mode;
939 
940 	p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
941 	o->bytes_per_data_element = p->bytes_per_data_element;
942 
943 	/* Before we tweak the hardware, we have to disable the transmitter */
944 	irqenable_tx(sd, 0);
945 	control_tx_enable(c, false);
946 
947 	control_tx_modulation_enable(c, p->modulation);
948 	o->modulation = p->modulation;
949 
950 	if (p->modulation) {
951 		p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
952 						     &txclk_divider);
953 		o->carrier_freq = p->carrier_freq;
954 
955 		p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
956 		o->duty_cycle = p->duty_cycle;
957 
958 		p->max_pulse_width =
959 			(u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
960 	} else {
961 		p->max_pulse_width =
962 			    txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
963 						       &txclk_divider);
964 	}
965 	o->max_pulse_width = p->max_pulse_width;
966 	atomic_set(&ir_state->txclk_divider, txclk_divider);
967 
968 	p->resolution = clock_divider_to_resolution(txclk_divider);
969 	o->resolution = p->resolution;
970 
971 	/* FIXME - make this dependent on resolution for better performance */
972 	control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
973 
974 	control_tx_polarity_invert(c, p->invert_carrier_sense);
975 	o->invert_carrier_sense = p->invert_carrier_sense;
976 
977 	/*
978 	 * FIXME: we don't have hardware help for IO pin level inversion
979 	 * here like we have on the CX23888.
980 	 * Act on this with some mix of logical inversion of data levels,
981 	 * carrier polarity, and carrier duty cycle.
982 	 */
983 	o->invert_level = p->invert_level;
984 
985 	o->interrupt_enable = p->interrupt_enable;
986 	o->enable = p->enable;
987 	if (p->enable) {
988 		/* reset tx_fifo here */
989 		if (p->interrupt_enable)
990 			irqenable_tx(sd, IRQEN_TSE);
991 		control_tx_enable(c, p->enable);
992 	}
993 
994 	mutex_unlock(&ir_state->tx_params_lock);
995 	return 0;
996 }
997 
998 
999 /*
1000  * V4L2 Subdevice Core Ops support
1001  */
cx25840_ir_log_status(struct v4l2_subdev * sd)1002 int cx25840_ir_log_status(struct v4l2_subdev *sd)
1003 {
1004 	struct cx25840_state *state = to_state(sd);
1005 	struct i2c_client *c = state->c;
1006 	char *s;
1007 	int i, j;
1008 	u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1009 
1010 	/* The CX23888 chip doesn't have an IR controller on the A/V core */
1011 	if (is_cx23888(state))
1012 		return 0;
1013 
1014 	cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1015 	txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1016 	rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1017 	cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1018 	stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1019 	irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1020 	if (is_cx23885(state) || is_cx23887(state))
1021 		irqen ^= IRQEN_MSK;
1022 	filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1023 
1024 	v4l2_info(sd, "IR Receiver:\n");
1025 	v4l2_info(sd, "\tEnabled:                           %s\n",
1026 		  cntrl & CNTRL_RXE ? "yes" : "no");
1027 	v4l2_info(sd, "\tDemodulation from a carrier:       %s\n",
1028 		  cntrl & CNTRL_DMD ? "enabled" : "disabled");
1029 	v4l2_info(sd, "\tFIFO:                              %s\n",
1030 		  cntrl & CNTRL_RFE ? "enabled" : "disabled");
1031 	switch (cntrl & CNTRL_EDG) {
1032 	case CNTRL_EDG_NONE:
1033 		s = "disabled";
1034 		break;
1035 	case CNTRL_EDG_FALL:
1036 		s = "falling edge";
1037 		break;
1038 	case CNTRL_EDG_RISE:
1039 		s = "rising edge";
1040 		break;
1041 	case CNTRL_EDG_BOTH:
1042 		s = "rising & falling edges";
1043 		break;
1044 	default:
1045 		s = "??? edge";
1046 		break;
1047 	}
1048 	v4l2_info(sd, "\tPulse timers' start/stop trigger:  %s\n", s);
1049 	v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1050 		  cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1051 	v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1052 		  cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1053 	v4l2_info(sd, "\tLoopback mode:                     %s\n",
1054 		  cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1055 	if (cntrl & CNTRL_DMD) {
1056 		v4l2_info(sd, "\tExpected carrier (16 clocks):      %u Hz\n",
1057 			  clock_divider_to_carrier_freq(rxclk));
1058 		switch (cntrl & CNTRL_WIN) {
1059 		case CNTRL_WIN_3_3:
1060 			i = 3;
1061 			j = 3;
1062 			break;
1063 		case CNTRL_WIN_4_3:
1064 			i = 4;
1065 			j = 3;
1066 			break;
1067 		case CNTRL_WIN_3_4:
1068 			i = 3;
1069 			j = 4;
1070 			break;
1071 		case CNTRL_WIN_4_4:
1072 			i = 4;
1073 			j = 4;
1074 			break;
1075 		default:
1076 			i = 0;
1077 			j = 0;
1078 			break;
1079 		}
1080 		v4l2_info(sd, "\tNext carrier edge window:	    16 clocks -%1d/+%1d, %u to %u Hz\n",
1081 			  i, j,
1082 			  clock_divider_to_freq(rxclk, 16 + j),
1083 			  clock_divider_to_freq(rxclk, 16 - i));
1084 	}
1085 	v4l2_info(sd, "\tMax measurable pulse width:        %u us, %llu ns\n",
1086 		  pulse_width_count_to_us(FIFO_RXTX, rxclk),
1087 		  pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1088 	v4l2_info(sd, "\tLow pass filter:                   %s\n",
1089 		  filtr ? "enabled" : "disabled");
1090 	if (filtr)
1091 		v4l2_info(sd, "\tMin acceptable pulse width (LPF):  %u us, %u ns\n",
1092 			  lpf_count_to_us(filtr),
1093 			  lpf_count_to_ns(filtr));
1094 	v4l2_info(sd, "\tPulse width timer timed-out:       %s\n",
1095 		  stats & STATS_RTO ? "yes" : "no");
1096 	v4l2_info(sd, "\tPulse width timer time-out intr:   %s\n",
1097 		  irqen & IRQEN_RTE ? "enabled" : "disabled");
1098 	v4l2_info(sd, "\tFIFO overrun:                      %s\n",
1099 		  stats & STATS_ROR ? "yes" : "no");
1100 	v4l2_info(sd, "\tFIFO overrun interrupt:            %s\n",
1101 		  irqen & IRQEN_ROE ? "enabled" : "disabled");
1102 	v4l2_info(sd, "\tBusy:                              %s\n",
1103 		  stats & STATS_RBY ? "yes" : "no");
1104 	v4l2_info(sd, "\tFIFO service requested:            %s\n",
1105 		  stats & STATS_RSR ? "yes" : "no");
1106 	v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1107 		  irqen & IRQEN_RSE ? "enabled" : "disabled");
1108 
1109 	v4l2_info(sd, "IR Transmitter:\n");
1110 	v4l2_info(sd, "\tEnabled:                           %s\n",
1111 		  cntrl & CNTRL_TXE ? "yes" : "no");
1112 	v4l2_info(sd, "\tModulation onto a carrier:         %s\n",
1113 		  cntrl & CNTRL_MOD ? "enabled" : "disabled");
1114 	v4l2_info(sd, "\tFIFO:                              %s\n",
1115 		  cntrl & CNTRL_TFE ? "enabled" : "disabled");
1116 	v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1117 		  cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1118 	v4l2_info(sd, "\tCarrier polarity:                  %s\n",
1119 		  cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1120 				    : "space:noburst mark:burst");
1121 	if (cntrl & CNTRL_MOD) {
1122 		v4l2_info(sd, "\tCarrier (16 clocks):               %u Hz\n",
1123 			  clock_divider_to_carrier_freq(txclk));
1124 		v4l2_info(sd, "\tCarrier duty cycle:                %2u/16\n",
1125 			  cduty + 1);
1126 	}
1127 	v4l2_info(sd, "\tMax pulse width:                   %u us, %llu ns\n",
1128 		  pulse_width_count_to_us(FIFO_RXTX, txclk),
1129 		  pulse_width_count_to_ns(FIFO_RXTX, txclk));
1130 	v4l2_info(sd, "\tBusy:                              %s\n",
1131 		  stats & STATS_TBY ? "yes" : "no");
1132 	v4l2_info(sd, "\tFIFO service requested:            %s\n",
1133 		  stats & STATS_TSR ? "yes" : "no");
1134 	v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1135 		  irqen & IRQEN_TSE ? "enabled" : "disabled");
1136 
1137 	return 0;
1138 }
1139 
1140 
1141 const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1142 	.rx_read = cx25840_ir_rx_read,
1143 	.rx_g_parameters = cx25840_ir_rx_g_parameters,
1144 	.rx_s_parameters = cx25840_ir_rx_s_parameters,
1145 
1146 	.tx_write = cx25840_ir_tx_write,
1147 	.tx_g_parameters = cx25840_ir_tx_g_parameters,
1148 	.tx_s_parameters = cx25840_ir_tx_s_parameters,
1149 };
1150 
1151 
1152 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1153 	.bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1154 	.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1155 
1156 	.enable = false,
1157 	.interrupt_enable = false,
1158 	.shutdown = true,
1159 
1160 	.modulation = true,
1161 	.carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1162 
1163 	/* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1164 	/* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1165 	.noise_filter_min_width = 333333, /* ns */
1166 	.carrier_range_lower = 35000,
1167 	.carrier_range_upper = 37000,
1168 	.invert_level = false,
1169 };
1170 
1171 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1172 	.bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1173 	.mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1174 
1175 	.enable = false,
1176 	.interrupt_enable = false,
1177 	.shutdown = true,
1178 
1179 	.modulation = true,
1180 	.carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1181 	.duty_cycle = 25,      /* 25 %   - RC-5 carrier */
1182 	.invert_level = false,
1183 	.invert_carrier_sense = false,
1184 };
1185 
cx25840_ir_probe(struct v4l2_subdev * sd)1186 int cx25840_ir_probe(struct v4l2_subdev *sd)
1187 {
1188 	struct cx25840_state *state = to_state(sd);
1189 	struct cx25840_ir_state *ir_state;
1190 	struct v4l2_subdev_ir_parameters default_params;
1191 
1192 	/* Only init the IR controller for the CX2388[57] AV Core for now */
1193 	if (!(is_cx23885(state) || is_cx23887(state)))
1194 		return 0;
1195 
1196 	ir_state = devm_kzalloc(&state->c->dev, sizeof(*ir_state), GFP_KERNEL);
1197 	if (ir_state == NULL)
1198 		return -ENOMEM;
1199 
1200 	spin_lock_init(&ir_state->rx_kfifo_lock);
1201 	if (kfifo_alloc(&ir_state->rx_kfifo,
1202 			CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1203 		return -ENOMEM;
1204 
1205 	ir_state->c = state->c;
1206 	state->ir_state = ir_state;
1207 
1208 	/* Ensure no interrupts arrive yet */
1209 	if (is_cx23885(state) || is_cx23887(state))
1210 		cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1211 	else
1212 		cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1213 
1214 	mutex_init(&ir_state->rx_params_lock);
1215 	default_params = default_rx_params;
1216 	v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1217 
1218 	mutex_init(&ir_state->tx_params_lock);
1219 	default_params = default_tx_params;
1220 	v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1221 
1222 	return 0;
1223 }
1224 
cx25840_ir_remove(struct v4l2_subdev * sd)1225 int cx25840_ir_remove(struct v4l2_subdev *sd)
1226 {
1227 	struct cx25840_state *state = to_state(sd);
1228 	struct cx25840_ir_state *ir_state = to_ir_state(sd);
1229 
1230 	if (ir_state == NULL)
1231 		return -ENODEV;
1232 
1233 	cx25840_ir_rx_shutdown(sd);
1234 	cx25840_ir_tx_shutdown(sd);
1235 
1236 	kfifo_free(&ir_state->rx_kfifo);
1237 	state->ir_state = NULL;
1238 	return 0;
1239 }
1240