1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <fsl_ddr_sdram.h>
9 #include <asm/processor.h>
10 #include <fsl_immap.h>
11 #include <fsl_ddr.h>
12 #include <fsl_errata.h>
13 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
14 defined(CONFIG_ARM)
15 #include <asm/arch/clock.h>
16 #endif
17
18 #define CTLR_INTLV_MASK 0x20000000
19
20 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
21 defined(CONFIG_SYS_FSL_ERRATUM_A009803)
set_wait_for_bits_clear(void * ptr,u32 value,u32 bits)22 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
23 {
24 int timeout = 1000;
25
26 ddr_out32(ptr, value);
27
28 while (ddr_in32(ptr) & bits) {
29 udelay(100);
30 timeout--;
31 }
32 if (timeout <= 0)
33 puts("Error: wait for clear timeout.\n");
34 }
35 #endif
36
37 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
38 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
39 #endif
40
41 /*
42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
44 * step: 0 goes through the initialization in one pass
45 * 1 sets registers and returns before enabling controller
46 * 2 resumes from step 1 and continues to initialize
47 * Dividing the initialization to two steps to deassert DDR reset signal
48 * to comply with JEDEC specs for RDIMMs.
49 */
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)50 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
51 unsigned int ctrl_num, int step)
52 {
53 unsigned int i, bus_width;
54 struct ccsr_ddr __iomem *ddr;
55 u32 temp32;
56 u32 total_gb_size_per_controller;
57 int timeout;
58 int mod_bnds = 0;
59
60 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
61 u32 mr6;
62 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */
63 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
64 u32 *vref_seq = vref_seq1;
65 #endif
66 #ifdef CONFIG_FSL_DDR_BIST
67 u32 mtcr, err_detect, err_sbe;
68 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
69 #endif
70 #ifdef CONFIG_FSL_DDR_BIST
71 char buffer[CONFIG_SYS_CBSIZE];
72 #endif
73 switch (ctrl_num) {
74 case 0:
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
76 break;
77 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
78 case 1:
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
80 break;
81 #endif
82 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
83 case 2:
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
85 break;
86 #endif
87 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
88 case 3:
89 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
90 break;
91 #endif
92 default:
93 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
94 return;
95 }
96 mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
97
98 if (step == 2)
99 goto step2;
100
101 /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
103
104 if (regs->ddr_eor)
105 ddr_out32(&ddr->eor, regs->ddr_eor);
106
107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
108 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
109 if (i == 0) {
110 if (mod_bnds) {
111 debug("modified bnds\n");
112 ddr_out32(&ddr->cs0_bnds,
113 (regs->cs[i].bnds & 0xfffefffe) >> 1);
114 ddr_out32(&ddr->cs0_config,
115 (regs->cs[i].config &
116 ~CTLR_INTLV_MASK));
117 } else {
118 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
119 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
120 }
121 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
122
123 } else if (i == 1) {
124 if (mod_bnds) {
125 ddr_out32(&ddr->cs1_bnds,
126 (regs->cs[i].bnds & 0xfffefffe) >> 1);
127 } else {
128 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
129 }
130 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
131 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
132
133 } else if (i == 2) {
134 if (mod_bnds) {
135 ddr_out32(&ddr->cs2_bnds,
136 (regs->cs[i].bnds & 0xfffefffe) >> 1);
137 } else {
138 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
139 }
140 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
141 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
142
143 } else if (i == 3) {
144 if (mod_bnds) {
145 ddr_out32(&ddr->cs3_bnds,
146 (regs->cs[i].bnds & 0xfffefffe) >> 1);
147 } else {
148 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
149 }
150 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
151 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
152 }
153 }
154
155 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
156 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
157 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
158 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
159 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
160 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
161 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
162 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
163 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
164 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
165 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
166 ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
167 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
168 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
169 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
170 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
171 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
172 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
173 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
174 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
175 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
176 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
177 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
178 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
179 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
180 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
181 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
182 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
183 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
184 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
185 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
186 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
187 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
188 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
189 ddr_out32(&ddr->sdram_interval,
190 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
191 #else
192 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
193 #endif
194 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
195 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
196 #ifndef CONFIG_SYS_FSL_DDR_EMU
197 /*
198 * Skip these two registers if running on emulator
199 * because emulator doesn't have skew between bytes.
200 */
201
202 if (regs->ddr_wrlvl_cntl_2)
203 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
204 if (regs->ddr_wrlvl_cntl_3)
205 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
206 #endif
207
208 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
209 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
210 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
211 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
212 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
213 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
214 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
215 #ifdef CONFIG_DEEP_SLEEP
216 if (is_warm_boot()) {
217 ddr_out32(&ddr->sdram_cfg_2,
218 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
219 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
220 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
221
222 /* DRAM VRef will not be trained */
223 ddr_out32(&ddr->ddr_cdr2,
224 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
225 } else
226 #endif
227 {
228 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
229 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
230 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
231 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
232 }
233
234 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
235 /* part 1 of 2 */
236 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
237 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
238 ddr_out32(&ddr->ddr_sdram_rcw_2,
239 regs->ddr_sdram_rcw_2 & ~0xf0);
240 }
241 ddr_out32(&ddr->err_disable, regs->err_disable |
242 DDR_ERR_DISABLE_APED);
243 }
244 #else
245 ddr_out32(&ddr->err_disable, regs->err_disable);
246 #endif
247 ddr_out32(&ddr->err_int_en, regs->err_int_en);
248 for (i = 0; i < 64; i++) {
249 if (regs->debug[i]) {
250 debug("Write to debug_%d as %08x\n",
251 i+1, regs->debug[i]);
252 ddr_out32(&ddr->debug[i], regs->debug[i]);
253 }
254 }
255
256 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
257 /* Part 1 of 2 */
258 if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
259 /* Disable DRAM VRef training */
260 ddr_out32(&ddr->ddr_cdr2,
261 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
262 /* disable transmit bit deskew */
263 temp32 = ddr_in32(&ddr->debug[28]);
264 temp32 |= DDR_TX_BD_DIS;
265 ddr_out32(&ddr->debug[28], temp32);
266 ddr_out32(&ddr->debug[25], 0x9000);
267 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
268 /* Output enable forced off */
269 ddr_out32(&ddr->debug[37], 1 << 31);
270 /* Enable Vref training */
271 ddr_out32(&ddr->ddr_cdr2,
272 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
273 } else {
274 debug("Erratum A008511 doesn't apply.\n");
275 }
276 #endif
277
278 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
279 defined(CONFIG_SYS_FSL_ERRATUM_A008511)
280 /* Disable D_INIT */
281 ddr_out32(&ddr->sdram_cfg_2,
282 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
283 #endif
284
285 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
286 temp32 = ddr_in32(&ddr->debug[25]);
287 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
288 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
289 ddr_out32(&ddr->debug[25], temp32);
290 #endif
291
292 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
293 temp32 = get_ddr_freq(ctrl_num) / 1000000;
294 if ((temp32 > 1900) && (temp32 < 2300)) {
295 temp32 = ddr_in32(&ddr->debug[28]);
296 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
297 }
298 #endif
299 /*
300 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
301 * deasserted. Clocks start when any chip select is enabled and clock
302 * control register is set. Because all DDR components are connected to
303 * one reset signal, this needs to be done in two steps. Step 1 is to
304 * get the clocks started. Step 2 resumes after reset signal is
305 * deasserted.
306 */
307 if (step == 1) {
308 udelay(200);
309 return;
310 }
311
312 step2:
313 /* Set, but do not enable the memory */
314 temp32 = regs->ddr_sdram_cfg;
315 temp32 &= ~(SDRAM_CFG_MEM_EN);
316 ddr_out32(&ddr->sdram_cfg, temp32);
317
318 /*
319 * 500 painful micro-seconds must elapse between
320 * the DDR clock setup and the DDR config enable.
321 * DDR2 need 200 us, and DDR3 need 500 us from spec,
322 * we choose the max, that is 500 us for all of case.
323 */
324 udelay(500);
325 mb();
326 isb();
327
328 #ifdef CONFIG_DEEP_SLEEP
329 if (is_warm_boot()) {
330 /* enter self-refresh */
331 temp32 = ddr_in32(&ddr->sdram_cfg_2);
332 temp32 |= SDRAM_CFG2_FRC_SR;
333 ddr_out32(&ddr->sdram_cfg_2, temp32);
334 /* do board specific memory setup */
335 board_mem_sleep_setup();
336
337 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
338 } else
339 #endif
340 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
341 /* Let the controller go */
342 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
343 mb();
344 isb();
345
346 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
347 defined(CONFIG_SYS_FSL_ERRATUM_A009803)
348 /* Part 2 of 2 */
349 timeout = 40;
350 /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
351 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
352 (timeout > 0)) {
353 udelay(1000);
354 timeout--;
355 }
356 if (timeout <= 0) {
357 printf("Controler %d timeout, debug_2 = %x\n",
358 ctrl_num, ddr_in32(&ddr->debug[1]));
359 }
360
361 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
362 /* This erraum only applies to verion 5.2.0 */
363 if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
364 /* The vref setting sequence is different for range 2 */
365 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
366 vref_seq = vref_seq2;
367
368 /* Set VREF */
369 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
370 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
371 continue;
372
373 mr6 = (regs->ddr_sdram_mode_10 >> 16) |
374 MD_CNTL_MD_EN |
375 MD_CNTL_CS_SEL(i) |
376 MD_CNTL_MD_SEL(6) |
377 0x00200000;
378 temp32 = mr6 | vref_seq[0];
379 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
380 temp32, MD_CNTL_MD_EN);
381 udelay(1);
382 debug("MR6 = 0x%08x\n", temp32);
383 temp32 = mr6 | vref_seq[1];
384 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
385 temp32, MD_CNTL_MD_EN);
386 udelay(1);
387 debug("MR6 = 0x%08x\n", temp32);
388 temp32 = mr6 | vref_seq[2];
389 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
390 temp32, MD_CNTL_MD_EN);
391 udelay(1);
392 debug("MR6 = 0x%08x\n", temp32);
393 }
394 ddr_out32(&ddr->sdram_md_cntl, 0);
395 temp32 = ddr_in32(&ddr->debug[28]);
396 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
397 ddr_out32(&ddr->debug[28], temp32);
398 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
399 /* wait for idle */
400 timeout = 40;
401 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
402 (timeout > 0)) {
403 udelay(1000);
404 timeout--;
405 }
406 if (timeout <= 0) {
407 printf("Controler %d timeout, debug_2 = %x\n",
408 ctrl_num, ddr_in32(&ddr->debug[1]));
409 }
410 }
411 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
412
413 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
414 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
415 /* if it's RDIMM */
416 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
417 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
418 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
419 continue;
420 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
421 MD_CNTL_MD_EN |
422 MD_CNTL_CS_SEL(i) |
423 0x070000ed,
424 MD_CNTL_MD_EN);
425 udelay(1);
426 }
427 }
428
429 ddr_out32(&ddr->err_disable,
430 regs->err_disable & ~DDR_ERR_DISABLE_APED);
431 }
432 #endif
433 /* Restore D_INIT */
434 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
435 #endif
436
437 total_gb_size_per_controller = 0;
438 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
439 if (!(regs->cs[i].config & 0x80000000))
440 continue;
441 total_gb_size_per_controller += 1 << (
442 ((regs->cs[i].config >> 14) & 0x3) + 2 +
443 ((regs->cs[i].config >> 8) & 0x7) + 12 +
444 ((regs->cs[i].config >> 4) & 0x3) + 0 +
445 ((regs->cs[i].config >> 0) & 0x7) + 8 +
446 ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
447 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
448 26); /* minus 26 (count of 64M) */
449 }
450 /*
451 * total memory / bus width = transactions needed
452 * transactions needed / data rate = seconds
453 * to add plenty of buffer, double the time
454 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
455 * Let's wait for 800ms
456 */
457 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
458 >> SDRAM_CFG_DBW_SHIFT);
459 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
460 (get_ddr_freq(ctrl_num) >> 20)) << 2;
461 total_gb_size_per_controller >>= 4; /* shift down to gb size */
462 debug("total %d GB\n", total_gb_size_per_controller);
463 debug("Need to wait up to %d * 10ms\n", timeout);
464
465 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
466 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
467 (timeout >= 0)) {
468 udelay(10000); /* throttle polling rate */
469 timeout--;
470 }
471
472 if (timeout <= 0)
473 printf("Waiting for D_INIT timeout. Memory may not work.\n");
474
475 if (mod_bnds) {
476 debug("Reset to original bnds\n");
477 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
478 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
479 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
480 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
481 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
482 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
483 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
484 #endif
485 #endif
486 #endif
487 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
488 }
489
490 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
491 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
492 #endif
493
494 #ifdef CONFIG_DEEP_SLEEP
495 if (is_warm_boot()) {
496 /* exit self-refresh */
497 temp32 = ddr_in32(&ddr->sdram_cfg_2);
498 temp32 &= ~SDRAM_CFG2_FRC_SR;
499 ddr_out32(&ddr->sdram_cfg_2, temp32);
500 }
501 #endif
502
503 #ifdef CONFIG_FSL_DDR_BIST
504 #define BIST_PATTERN1 0xFFFFFFFF
505 #define BIST_PATTERN2 0x0
506 #define BIST_CR 0x80010000
507 #define BIST_CR_EN 0x80000000
508 #define BIST_CR_STAT 0x00000001
509 /* Perform build-in test on memory. Three-way interleaving is not yet
510 * supported by this code. */
511 if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
512 puts("Running BIST test. This will take a while...");
513 cs0_config = ddr_in32(&ddr->cs0_config);
514 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
515 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
516 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
517 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
518 if (cs0_config & CTLR_INTLV_MASK) {
519 /* set bnds to non-interleaving */
520 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
521 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
522 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
523 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
524 }
525 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
526 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
527 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
528 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
529 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
530 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
531 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
532 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
533 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
534 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
535 mtcr = BIST_CR;
536 ddr_out32(&ddr->mtcr, mtcr);
537 timeout = 100;
538 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
539 mdelay(1000);
540 timeout--;
541 mtcr = ddr_in32(&ddr->mtcr);
542 }
543 if (timeout <= 0)
544 puts("Timeout\n");
545 else
546 puts("Done\n");
547 err_detect = ddr_in32(&ddr->err_detect);
548 err_sbe = ddr_in32(&ddr->err_sbe);
549 if (mtcr & BIST_CR_STAT) {
550 printf("BIST test failed on controller %d.\n",
551 ctrl_num);
552 }
553 if (err_detect || (err_sbe & 0xffff)) {
554 printf("ECC error detected on controller %d.\n",
555 ctrl_num);
556 }
557
558 if (cs0_config & CTLR_INTLV_MASK) {
559 /* restore bnds registers */
560 ddr_out32(&ddr->cs0_bnds, cs0_bnds);
561 ddr_out32(&ddr->cs1_bnds, cs1_bnds);
562 ddr_out32(&ddr->cs2_bnds, cs2_bnds);
563 ddr_out32(&ddr->cs3_bnds, cs3_bnds);
564 }
565 }
566 #endif
567 }
568