1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * camss-csiphy-3ph-1-0.c
4  *
5  * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
6  *
7  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8  * Copyright (C) 2016-2018 Linaro Ltd.
9  */
10 
11 #include "camss.h"
12 #include "camss-csiphy.h"
13 
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 
18 #define CSIPHY_3PH_LNn_CFG1(n)			(0x000 + 0x100 * (n))
19 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG	(BIT(7) | BIT(6))
20 #define CSIPHY_3PH_LNn_CFG2(n)			(0x004 + 0x100 * (n))
21 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT	BIT(3)
22 #define CSIPHY_3PH_LNn_CFG3(n)			(0x008 + 0x100 * (n))
23 #define CSIPHY_3PH_LNn_CFG4(n)			(0x00c + 0x100 * (n))
24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS	0xa4
25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660	0xa5
26 #define CSIPHY_3PH_LNn_CFG5(n)			(0x010 + 0x100 * (n))
27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM		0x02
28 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT	0x50
29 #define CSIPHY_3PH_LNn_TEST_IMP(n)		(0x01c + 0x100 * (n))
30 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP	0xa
31 #define CSIPHY_3PH_LNn_MISC1(n)			(0x028 + 0x100 * (n))
32 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE		BIT(2)
33 #define CSIPHY_3PH_LNn_CFG6(n)			(0x02c + 0x100 * (n))
34 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT	BIT(0)
35 #define CSIPHY_3PH_LNn_CFG7(n)			(0x030 + 0x100 * (n))
36 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT		0x2
37 #define CSIPHY_3PH_LNn_CFG8(n)			(0x034 + 0x100 * (n))
38 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP	BIT(0)
39 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE	BIT(1)
40 #define CSIPHY_3PH_LNn_CFG9(n)			(0x038 + 0x100 * (n))
41 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP	0x1
42 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n)	(0x03c + 0x100 * (n))
43 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL	0xb8
44 
45 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n)	(0x800 + 0x4 * (n))
46 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE	BIT(7)
47 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B	BIT(0)
48 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID	BIT(1)
49 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n)	(0x8b0 + 0x4 * (n))
50 
51 #define CSIPHY_DEFAULT_PARAMS            0
52 #define CSIPHY_LANE_ENABLE               1
53 #define CSIPHY_SETTLE_CNT_LOWER_BYTE     2
54 #define CSIPHY_SETTLE_CNT_HIGHER_BYTE    3
55 #define CSIPHY_DNP_PARAMS                4
56 #define CSIPHY_2PH_REGS                  5
57 #define CSIPHY_3PH_REGS                  6
58 
59 struct csiphy_reg_t {
60 	s32 reg_addr;
61 	s32 reg_data;
62 	s32 delay;
63 	u32 csiphy_param_type;
64 };
65 
66 /* GEN2 1.0 2PH */
67 static const struct
68 csiphy_reg_t lane_regs_sdm845[5][14] = {
69 	{
70 		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
71 		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
72 		{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
73 		{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
74 		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
75 		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
76 		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
77 		{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
78 		{0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
79 		{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
80 		{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
81 		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
82 		{0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
83 		{0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
84 	},
85 	{
86 		{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
87 		{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
88 		{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
89 		{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
90 		{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
91 		{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
92 		{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
93 		{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
94 		{0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
95 		{0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
96 		{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
97 		{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
98 		{0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
99 		{0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
100 	},
101 	{
102 		{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
103 		{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
104 		{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
105 		{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
106 		{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
107 		{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
108 		{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
109 		{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
110 		{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
111 		{0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
112 		{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
113 		{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
114 		{0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
115 		{0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
116 	},
117 	{
118 		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
119 		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
120 		{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
121 		{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
122 		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
123 		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
124 		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
125 		{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
126 		{0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
127 		{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
128 		{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
129 		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
130 		{0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
131 		{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
132 	},
133 	{
134 		{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
135 		{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
136 		{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
137 		{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
138 		{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
139 		{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
140 		{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
141 		{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
142 		{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
143 		{0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
144 		{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
145 		{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
146 		{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
147 		{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
148 	},
149 };
150 
151 /* GEN2 1.2.1 2PH */
152 static const struct
153 csiphy_reg_t lane_regs_sm8250[5][20] = {
154 	{
155 		{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
156 		{0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
157 		{0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
158 		{0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
159 		{0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
160 		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
161 		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
162 		{0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
163 		{0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
164 		{0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
165 		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
166 		{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
167 		{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
168 		{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
169 		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
170 		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
171 		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
172 		{0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
173 		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
174 		{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
175 	},
176 	{
177 		{0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
178 		{0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
179 		{0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
180 		{0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
181 		{0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
182 		{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
183 		{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
184 		{0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
185 		{0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
186 		{0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
187 		{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
188 		{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
189 		{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
190 		{0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
191 		{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
192 		{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
193 		{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
194 		{0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
195 		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
196 		{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
197 	},
198 	{
199 		{0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
200 		{0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
201 		{0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
202 		{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
203 		{0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
204 		{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
205 		{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
206 		{0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
207 		{0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
208 		{0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
209 		{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
210 		{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
211 		{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
212 		{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
213 		{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
214 		{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
215 		{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
216 		{0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
217 		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
218 		{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
219 	},
220 	{
221 		{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
222 		{0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
223 		{0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
224 		{0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
225 		{0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
226 		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
227 		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
228 		{0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
229 		{0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
230 		{0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
231 		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
232 		{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
233 		{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
234 		{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
235 		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
236 		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
237 		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
238 		{0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
239 		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
240 		{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
241 	},
242 	{
243 		{0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
244 		{0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
245 		{0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
246 		{0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
247 		{0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
248 		{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
249 		{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
250 		{0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
251 		{0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
252 		{0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
253 		{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
254 		{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
255 		{0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
256 		{0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
257 		{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
258 		{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
259 		{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
260 		{0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS},
261 		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
262 		{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
263 	},
264 };
265 
csiphy_hw_version_read(struct csiphy_device * csiphy,struct device * dev)266 static void csiphy_hw_version_read(struct csiphy_device *csiphy,
267 				   struct device *dev)
268 {
269 	u32 hw_version;
270 
271 	writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID,
272 	       csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
273 
274 	hw_version = readl_relaxed(csiphy->base +
275 				   CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12));
276 	hw_version |= readl_relaxed(csiphy->base +
277 				   CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8;
278 	hw_version |= readl_relaxed(csiphy->base +
279 				   CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16;
280 	hw_version |= readl_relaxed(csiphy->base +
281 				   CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24;
282 
283 	dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
284 }
285 
286 /*
287  * csiphy_reset - Perform software reset on CSIPHY module
288  * @csiphy: CSIPHY device
289  */
csiphy_reset(struct csiphy_device * csiphy)290 static void csiphy_reset(struct csiphy_device *csiphy)
291 {
292 	writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
293 	usleep_range(5000, 8000);
294 	writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
295 }
296 
csiphy_isr(int irq,void * dev)297 static irqreturn_t csiphy_isr(int irq, void *dev)
298 {
299 	struct csiphy_device *csiphy = dev;
300 	int i;
301 
302 	for (i = 0; i < 11; i++) {
303 		int c = i + 22;
304 		u8 val = readl_relaxed(csiphy->base +
305 				       CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i));
306 
307 		writel_relaxed(val, csiphy->base +
308 				    CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c));
309 	}
310 
311 	writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
312 	writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
313 
314 	for (i = 22; i < 33; i++)
315 		writel_relaxed(0x0, csiphy->base +
316 				    CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
317 
318 	return IRQ_HANDLED;
319 }
320 
321 /*
322  * csiphy_settle_cnt_calc - Calculate settle count value
323  *
324  * Helper function to calculate settle count value. This is
325  * based on the CSI2 T_hs_settle parameter which in turn
326  * is calculated based on the CSI2 transmitter link frequency.
327  *
328  * Return settle count value or 0 if the CSI2 link frequency
329  * is not available
330  */
csiphy_settle_cnt_calc(s64 link_freq,u32 timer_clk_rate)331 static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
332 {
333 	u32 ui; /* ps */
334 	u32 timer_period; /* ps */
335 	u32 t_hs_prepare_max; /* ps */
336 	u32 t_hs_settle; /* ps */
337 	u8 settle_cnt;
338 
339 	if (link_freq <= 0)
340 		return 0;
341 
342 	ui = div_u64(1000000000000LL, link_freq);
343 	ui /= 2;
344 	t_hs_prepare_max = 85000 + 6 * ui;
345 	t_hs_settle = t_hs_prepare_max;
346 
347 	timer_period = div_u64(1000000000000LL, timer_clk_rate);
348 	settle_cnt = t_hs_settle / timer_period - 6;
349 
350 	return settle_cnt;
351 }
352 
csiphy_gen1_config_lanes(struct csiphy_device * csiphy,struct csiphy_config * cfg,u8 settle_cnt)353 static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy,
354 				     struct csiphy_config *cfg,
355 				     u8 settle_cnt)
356 {
357 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
358 	int i, l = 0;
359 	u8 val;
360 
361 	for (i = 0; i <= c->num_data; i++) {
362 		if (i == c->num_data)
363 			l = 7;
364 		else
365 			l = c->data[i].pos * 2;
366 
367 		val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
368 		val |= 0x17;
369 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
370 
371 		val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT;
372 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
373 
374 		val = settle_cnt;
375 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
376 
377 		val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM |
378 			CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT;
379 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
380 
381 		val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT;
382 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
383 
384 		val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT;
385 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
386 
387 		val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP |
388 			CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE;
389 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
390 
391 		val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP;
392 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
393 
394 		val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP;
395 		writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
396 
397 		val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL;
398 		writel_relaxed(val, csiphy->base +
399 				    CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l));
400 	}
401 
402 	val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
403 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
404 
405 	if (csiphy->camss->version == CAMSS_660)
406 		val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660;
407 	else
408 		val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
409 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
410 
411 	val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
412 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
413 }
414 
csiphy_gen2_config_lanes(struct csiphy_device * csiphy,u8 settle_cnt)415 static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
416 				     u8 settle_cnt)
417 {
418 	const struct csiphy_reg_t *r;
419 	int i, l, array_size;
420 	u32 val;
421 
422 	switch (csiphy->camss->version) {
423 	case CAMSS_845:
424 		r = &lane_regs_sdm845[0][0];
425 		array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
426 		break;
427 	case CAMSS_8250:
428 		r = &lane_regs_sm8250[0][0];
429 		array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
430 		break;
431 	default:
432 		WARN(1, "unknown cspi version\n");
433 		return;
434 	}
435 
436 	for (l = 0; l < 5; l++) {
437 		for (i = 0; i < array_size; i++, r++) {
438 			switch (r->csiphy_param_type) {
439 			case CSIPHY_SETTLE_CNT_LOWER_BYTE:
440 				val = settle_cnt & 0xff;
441 				break;
442 			case CSIPHY_DNP_PARAMS:
443 				continue;
444 			default:
445 				val = r->reg_data;
446 				break;
447 			}
448 			writel_relaxed(val, csiphy->base + r->reg_addr);
449 		}
450 	}
451 }
452 
csiphy_get_lane_mask(struct csiphy_lanes_cfg * lane_cfg)453 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
454 {
455 	u8 lane_mask;
456 	int i;
457 
458 	lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
459 
460 	for (i = 0; i < lane_cfg->num_data; i++)
461 		lane_mask |= 1 << lane_cfg->data[i].pos;
462 
463 	return lane_mask;
464 }
465 
csiphy_lanes_enable(struct csiphy_device * csiphy,struct csiphy_config * cfg,s64 link_freq,u8 lane_mask)466 static void csiphy_lanes_enable(struct csiphy_device *csiphy,
467 				struct csiphy_config *cfg,
468 				s64 link_freq, u8 lane_mask)
469 {
470 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
471 	bool is_gen2 = (csiphy->camss->version == CAMSS_845 ||
472 			csiphy->camss->version == CAMSS_8250);
473 	u8 settle_cnt;
474 	u8 val;
475 	int i;
476 
477 	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
478 
479 	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
480 	for (i = 0; i < c->num_data; i++)
481 		val |= BIT(c->data[i].pos * 2);
482 
483 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
484 
485 	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
486 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
487 
488 	val = 0x02;
489 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(7));
490 
491 	val = 0x00;
492 	writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
493 
494 	if (is_gen2)
495 		csiphy_gen2_config_lanes(csiphy, settle_cnt);
496 	else
497 		csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
498 
499 	/* IRQ_MASK registers - disable all interrupts */
500 	for (i = 11; i < 22; i++)
501 		writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
502 }
503 
csiphy_lanes_disable(struct csiphy_device * csiphy,struct csiphy_config * cfg)504 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
505 				 struct csiphy_config *cfg)
506 {
507 	writel_relaxed(0, csiphy->base +
508 			  CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
509 
510 	writel_relaxed(0, csiphy->base +
511 			  CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
512 }
513 
514 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
515 	.get_lane_mask = csiphy_get_lane_mask,
516 	.hw_version_read = csiphy_hw_version_read,
517 	.reset = csiphy_reset,
518 	.lanes_enable = csiphy_lanes_enable,
519 	.lanes_disable = csiphy_lanes_disable,
520 	.isr = csiphy_isr,
521 };
522