xref: /openbmc/linux/include/sound/cs8427.h (revision 1a59d1b8)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef __SOUND_CS8427_H
3 #define __SOUND_CS8427_H
4 
5 /*
6  *  Routines for Cirrus Logic CS8427
7  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
8  */
9 
10 #include <sound/i2c.h>
11 
12 #define CS8427_BASE_ADDR	0x10	/* base I2C address */
13 
14 #define CS8427_REG_AUTOINC	0x80	/* flag - autoincrement */
15 #define CS8427_REG_CONTROL1	0x01
16 #define CS8427_REG_CONTROL2	0x02
17 #define CS8427_REG_DATAFLOW	0x03
18 #define CS8427_REG_CLOCKSOURCE	0x04
19 #define CS8427_REG_SERIALINPUT	0x05
20 #define CS8427_REG_SERIALOUTPUT	0x06
21 #define CS8427_REG_INT1STATUS	0x07
22 #define CS8427_REG_INT2STATUS	0x08
23 #define CS8427_REG_INT1MASK	0x09
24 #define CS8427_REG_INT1MODEMSB	0x0a
25 #define CS8427_REG_INT1MODELSB	0x0b
26 #define CS8427_REG_INT2MASK	0x0c
27 #define CS8427_REG_INT2MODEMSB	0x0d
28 #define CS8427_REG_INT2MODELSB	0x0e
29 #define CS8427_REG_RECVCSDATA	0x0f
30 #define CS8427_REG_RECVERRORS	0x10
31 #define CS8427_REG_RECVERRMASK	0x11
32 #define CS8427_REG_CSDATABUF	0x12
33 #define CS8427_REG_UDATABUF	0x13
34 #define CS8427_REG_QSUBCODE	0x14	/* 0x14-0x1d (10 bytes) */
35 #define CS8427_REG_OMCKRMCKRATIO 0x1e
36 #define CS8427_REG_CORU_DATABUF	0x20	/* 24 byte buffer area */
37 #define CS8427_REG_ID_AND_VER	0x7f
38 
39 /* CS8427_REG_CONTROL1 bits */
40 #define CS8427_SWCLK		(1<<7)	/* 0 = RMCK default, 1 = OMCK output on RMCK pin */
41 #define CS8427_VSET		(1<<6)	/* 0 = valid PCM data, 1 = invalid PCM data */
42 #define CS8427_MUTESAO		(1<<5)	/* mute control for the serial audio output port, 0 = disabled, 1 = enabled */
43 #define CS8427_MUTEAES		(1<<4)	/* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */
44 #define CS8427_INTMASK		(3<<1)	/* interrupt output pin setup mask */
45 #define CS8427_INTACTHIGH	(0<<1)	/* active high */
46 #define CS8427_INTACTLOW	(1<<1)	/* active low */
47 #define CS8427_INTOPENDRAIN	(2<<1)	/* open drain, active low */
48 #define CS8427_TCBLDIR		(1<<0)	/* 0 = TCBL is an input, 1 = TCBL is an output */
49 
50 /* CS8427_REQ_CONTROL2 bits */
51 #define CS8427_HOLDMASK		(3<<5)	/* action when a receiver error occurs */
52 #define CS8427_HOLDLASTSAMPLE	(0<<5)	/* hold the last valid sample */
53 #define CS8427_HOLDZERO		(1<<5)	/* replace the current audio sample with zero (mute) */
54 #define CS8427_HOLDNOCHANGE	(2<<5)	/* do not change the received audio sample */
55 #define CS8427_RMCKF		(1<<4)	/* 0 = 256*Fsi, 1 = 128*Fsi */
56 #define CS8427_MMR		(1<<3)	/* AES3 receiver operation, 0 = stereo, 1 = mono */
57 #define CS8427_MMT		(1<<2)	/* AES3 transmitter operation, 0 = stereo, 1 = mono */
58 #define CS8427_MMTCS		(1<<1)	/* 0 = use A + B CS data, 1 = use MMTLR CS data */
59 #define CS8427_MMTLR		(1<<0)	/* 0 = use A CS data, 1 = use B CS data */
60 
61 /* CS8427_REG_DATAFLOW */
62 #define CS8427_TXOFF		(1<<6)	/* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
63 #define CS8427_AESBP		(1<<5)	/* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
64 #define CS8427_TXDMASK		(3<<3)	/* AES3 Transmitter Data Source Mask */
65 #define CS8427_TXDSERIAL	(1<<3)	/* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER	(2<<3)	/* TXD - AES3 receiver */
67 #define CS8427_SPDMASK		(3<<1)	/* Serial Audio Output Port Data Source Mask */
68 #define CS8427_SPDSERIAL	(1<<1)	/* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER	(2<<1)	/* SPD - AES3 receiver */
70 
71 /* CS8427_REG_CLOCKSOURCE */
72 #define CS8427_RUN		(1<<6)	/* 0 = clock off, 1 = clock on */
73 #define CS8427_CLKMASK		(3<<4)	/* OMCK frequency mask */
74 #define CS8427_CLK256		(0<<4)	/* 256*Fso */
75 #define CS8427_CLK384		(1<<4)	/* 384*Fso */
76 #define CS8427_CLK512		(2<<4)	/* 512*Fso */
77 #define CS8427_OUTC		(1<<3)	/* Output Time Base, 0 = OMCK, 1 = recovered input clock */
78 #define CS8427_INC		(1<<2)	/* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */
79 #define CS8427_RXDMASK		(3<<0)	/* Recovered Input Clock Source Mask */
80 #define CS8427_RXDILRCK		(0<<0)	/* 256*Fsi from ILRCK pin */
81 #define CS8427_RXDAES3INPUT	(1<<0)	/* 256*Fsi from AES3 input */
82 #define CS8427_EXTCLOCKRESET	(2<<0)	/* bypass PLL, 256*Fsi clock, synchronous reset */
83 #define CS8427_EXTCLOCK		(3<<0)	/* bypass PLL, 256*Fsi clock */
84 
85 /* CS8427_REG_SERIALINPUT */
86 #define CS8427_SIMS		(1<<7)	/* 0 = slave, 1 = master mode */
87 #define CS8427_SISF		(1<<6)	/* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */
88 #define CS8427_SIRESMASK	(3<<4)	/* Resolution of the input data for right justified formats */
89 #define CS8427_SIRES24		(0<<4)	/* SIRES 24-bit */
90 #define CS8427_SIRES20		(1<<4)	/* SIRES 20-bit */
91 #define CS8427_SIRES16		(2<<4)	/* SIRES 16-bit */
92 #define CS8427_SIJUST		(1<<3)	/* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */
93 #define CS8427_SIDEL		(1<<2)	/* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */
94 #define CS8427_SISPOL		(1<<1)	/* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
95 #define CS8427_SILRPOL		(1<<0)	/* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */
96 
97 /* CS8427_REG_SERIALOUTPUT */
98 #define CS8427_SOMS		(1<<7)	/* 0 = slave, 1 = master mode */
99 #define CS8427_SOSF		(1<<6)	/* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */
100 #define CS8427_SORESMASK	(3<<4)	/* Resolution of the output data on SDOUT and AES3 output */
101 #define CS8427_SORES24		(0<<4)	/* SIRES 24-bit */
102 #define CS8427_SORES20		(1<<4)	/* SIRES 20-bit */
103 #define CS8427_SORES16		(2<<4)	/* SIRES 16-bit */
104 #define CS8427_SORESDIRECT	(2<<4)	/* SIRES direct copy from AES3 receiver */
105 #define CS8427_SOJUST		(1<<3)	/* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */
106 #define CS8427_SODEL		(1<<2)	/* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */
107 #define CS8427_SOSPOL		(1<<1)	/* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
108 #define CS8427_SOLRPOL		(1<<0)	/* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */
109 
110 /* CS8427_REG_INT1STATUS */
111 #define CS8427_TSLIP		(1<<7)	/* AES3 transmitter source data slip interrupt */
112 #define CS8427_OSLIP		(1<<6)	/* Serial audio output port data slip interrupt */
113 #define CS8427_DETC		(1<<2)	/* D to E C-buffer transfer interrupt */
114 #define CS8427_EFTC		(1<<1)	/* E to F C-buffer transfer interrupt */
115 #define CS8427_RERR		(1<<0)	/* A receiver error has occurred */
116 
117 /* CS8427_REG_INT2STATUS */
118 #define CS8427_DETU		(1<<3)	/* D to E U-buffer transfer interrupt */
119 #define CS8427_EFTU		(1<<2)	/* E to F U-buffer transfer interrupt */
120 #define CS8427_QCH		(1<<1)	/* A new block of Q-subcode data is available for reading */
121 
122 /* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */
123 /* bits are defined in CS8427_REG_INT1STATUS */
124 /* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */
125 /* bits are defined in CS8427_REG_INT2STATUS */
126 #define CS8427_INTMODERISINGMSB	0
127 #define CS8427_INTMODERESINGLSB	0
128 #define CS8427_INTMODEFALLINGMSB 0
129 #define CS8427_INTMODEFALLINGLSB 1
130 #define CS8427_INTMODELEVELMSB	1
131 #define CS8427_INTMODELEVELLSB	0
132 
133 /* CS8427_REG_RECVCSDATA */
134 #define CS8427_AUXMASK		(15<<4)	/* auxiliary data field width */
135 #define CS8427_AUXSHIFT		4
136 #define CS8427_PRO		(1<<3)	/* Channel status block format indicator */
137 #define CS8427_AUDIO		(1<<2)	/* Audio indicator (0 = audio, 1 = nonaudio */
138 #define CS8427_COPY		(1<<1)	/* 0 = copyright asserted, 1 = copyright not asserted */
139 #define CS8427_ORIG		(1<<0)	/* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */
140 
141 /* CS8427_REG_RECVERRORS */
142 /* CS8427_REG_RECVERRMASK for CS8427_RERR */
143 #define CS8427_QCRC		(1<<6)	/* Q-subcode data CRC error indicator */
144 #define CS8427_CCRC		(1<<5)	/* Chancnel Status Block Cyclick Redundancy Check Bit */
145 #define CS8427_UNLOCK		(1<<4)	/* PLL lock status bit */
146 #define CS8427_V		(1<<3)	/* 0 = valid data */
147 #define CS8427_CONF		(1<<2)	/* Confidence bit */
148 #define CS8427_BIP		(1<<1)	/* Bi-phase error bit */
149 #define CS8427_PAR		(1<<0)	/* Parity error */
150 
151 /* CS8427_REG_CSDATABUF	*/
152 #define CS8427_BSEL		(1<<5)	/* 0 = CS data, 1 = U data */
153 #define CS8427_CBMR		(1<<4)	/* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */
154 #define CS8427_DETCI		(1<<3)	/* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
155 #define CS8427_EFTCI		(1<<2)	/* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
156 #define CS8427_CAM		(1<<1)	/* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */
157 #define CS8427_CHS		(1<<0)	/* Channel select bit, 0 = Channel A, 1 = Channel B */
158 
159 /* CS8427_REG_UDATABUF */
160 #define CS8427_UD		(1<<4)	/* User data pin (U) direction, 0 = input, 1 = output */
161 #define CS8427_UBMMASK		(3<<2)	/* Operating mode of the AES3 U bit manager */
162 #define CS8427_UBMZEROS		(0<<2)	/* transmit all zeros mode */
163 #define CS8427_UBMBLOCK		(1<<2)	/* block mode */
164 #define CS8427_DETUI		(1<<1)	/* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
165 #define CS8427_EFTUI		(1<<1)	/* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
166 
167 /* CS8427_REG_ID_AND_VER */
168 #define CS8427_IDMASK		(15<<4)
169 #define CS8427_IDSHIFT		4
170 #define CS8427_VERMASK		(15<<0)
171 #define CS8427_VERSHIFT		0
172 #define CS8427_VER8427A		0x71
173 
174 struct snd_pcm_substream;
175 
176 int snd_cs8427_init(struct snd_i2c_bus *bus, struct snd_i2c_device *device);
177 int snd_cs8427_create(struct snd_i2c_bus *bus, unsigned char addr,
178 		      unsigned int reset_timeout, struct snd_i2c_device **r_cs8427);
179 int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
180 			 unsigned char val);
181 int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
182 			    struct snd_pcm_substream *playback_substream,
183 			    struct snd_pcm_substream *capture_substream);
184 int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active);
185 int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate);
186 
187 #endif /* __SOUND_CS8427_H */
188