1 /* 2 * QEMU ARM CP Register access and descriptions 3 * 4 * Copyright (c) 2022 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #ifndef TARGET_ARM_CPREGS_H 22 #define TARGET_ARM_CPREGS_H 23 24 #include "hw/registerfields.h" 25 #include "exec/memop.h" 26 #include "target/arm/kvm-consts.h" 27 #include "cpu.h" 28 29 /* 30 * ARMCPRegInfo type field bits: 31 */ 32 enum { 33 /* 34 * Register must be handled specially during translation. 35 * The method is one of the values below: 36 */ 37 ARM_CP_SPECIAL_MASK = 0x000f, 38 /* Special: no change to PE state: writes ignored, reads ignored. */ 39 ARM_CP_NOP = 0x0001, 40 /* Special: sysreg is WFI, for v5 and v6. */ 41 ARM_CP_WFI = 0x0002, 42 /* Special: sysreg is NZCV. */ 43 ARM_CP_NZCV = 0x0003, 44 /* Special: sysreg is CURRENTEL. */ 45 ARM_CP_CURRENTEL = 0x0004, 46 /* Special: sysreg is DC ZVA or similar. */ 47 ARM_CP_DC_ZVA = 0x0005, 48 ARM_CP_DC_GVA = 0x0006, 49 ARM_CP_DC_GZVA = 0x0007, 50 /* Special: gcs instructions */ 51 ARM_CP_GCSPUSHM = 0x0008, 52 ARM_CP_GCSPOPM = 0x0009, 53 ARM_CP_GCSPUSHX = 0x000a, 54 ARM_CP_GCSPOPX = 0x000b, 55 ARM_CP_GCSPOPCX = 0x000c, 56 ARM_CP_GCSSS1 = 0x000d, 57 ARM_CP_GCSSS2 = 0x000e, 58 59 /* Flag: reads produce resetvalue; writes ignored. */ 60 ARM_CP_CONST = 1 << 4, 61 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ 62 ARM_CP_64BIT = 1 << 5, 63 /* 64 * Flag: TB should not be ended after a write to this register 65 * (the default is that the TB ends after cp writes). 66 */ 67 ARM_CP_SUPPRESS_TB_END = 1 << 6, 68 /* 69 * Flag: Permit a register definition to override a previous definition 70 * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new 71 * or the old must have the ARM_CP_OVERRIDE bit set. 72 */ 73 ARM_CP_OVERRIDE = 1 << 7, 74 /* 75 * Flag: Register is an alias view of some underlying state which is also 76 * visible via another register, and that the other register is handling 77 * migration and reset; registers marked ARM_CP_ALIAS will not be migrated 78 * but may have their state set by syncing of register state from KVM. 79 */ 80 ARM_CP_ALIAS = 1 << 8, 81 /* 82 * Flag: Register does I/O and therefore its accesses need to be marked 83 * with translator_io_start() and also end the TB. In particular, 84 * registers which implement clocks or timers require this. 85 */ 86 ARM_CP_IO = 1 << 9, 87 /* 88 * Flag: Register has no underlying state and does not support raw access 89 * for state saving/loading; it will not be used for either migration or 90 * KVM state synchronization. Typically this is for "registers" which are 91 * actually used as instructions for cache maintenance and so on. 92 */ 93 ARM_CP_NO_RAW = 1 << 10, 94 /* 95 * Flag: The read or write hook might raise an exception; the generated 96 * code will synchronize the CPU state before calling the hook so that it 97 * is safe for the hook to call raise_exception(). 98 */ 99 ARM_CP_RAISES_EXC = 1 << 11, 100 /* 101 * Flag: Writes to the sysreg might change the exception level - typically 102 * on older ARM chips. For those cases we need to re-read the new el when 103 * recomputing the translation flags. 104 */ 105 ARM_CP_NEWEL = 1 << 12, 106 /* 107 * Flag: Access check for this sysreg is identical to accessing FPU state 108 * from an instruction: use translation fp_access_check(). 109 */ 110 ARM_CP_FPU = 1 << 13, 111 /* 112 * Flag: Access check for this sysreg is identical to accessing SVE state 113 * from an instruction: use translation sve_access_check(). 114 */ 115 ARM_CP_SVE = 1 << 14, 116 /* Flag: Do not expose in gdb sysreg xml. */ 117 ARM_CP_NO_GDB = 1 << 15, 118 /* 119 * Flags: If EL3 but not EL2... 120 * - UNDEF: discard the cpreg, 121 * - KEEP: retain the cpreg as is, 122 * - C_NZ: set const on the cpreg, but retain resetvalue, 123 * - else: set const on the cpreg, zero resetvalue, aka RES0. 124 * See rule RJFFP in section D1.1.3 of DDI0487H.a. 125 */ 126 ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, 127 ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, 128 ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, 129 /* 130 * Flag: Access check for this sysreg is constrained by the 131 * ARM pseudocode function CheckSMEAccess(). 132 */ 133 ARM_CP_SME = 1 << 19, 134 /* 135 * Flag: one of the four EL2 registers which redirect to the 136 * equivalent EL1 register when FEAT_NV2 is enabled. 137 */ 138 ARM_CP_NV2_REDIRECT = 1 << 20, 139 /* 140 * Flag: this is a TLBI insn which (when FEAT_XS is present) also has 141 * an NXS variant at the same encoding except that crn is 1 greater, 142 * so when registering this cpreg automatically also register one 143 * for the TLBI NXS variant. (For QEMU the NXS variant behaves 144 * identically to the normal one, other than FGT trapping handling.) 145 */ 146 ARM_CP_ADD_TLBI_NXS = 1 << 21, 147 /* 148 * Flag: even though this sysreg has opc1 == 4 or 5, it 149 * should not trap to EL2 when HCR_EL2.NV is set. 150 */ 151 ARM_CP_NV_NO_TRAP = 1 << 22, 152 }; 153 154 /* 155 * Interface for defining coprocessor registers. 156 * Registers are defined in tables of arm_cp_reginfo structs 157 * which are passed to define_arm_cp_regs(). 158 */ 159 160 /* 161 * When looking up a coprocessor register we look for it 162 * via an integer which encodes all of: 163 * coprocessor number 164 * Crn, Crm, opc1, opc2 fields 165 * 32 or 64 bit register (ie is it accessed via MRC/MCR 166 * or via MRRC/MCRR?) 167 * non-secure/secure bank (AArch32 only) 168 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 169 * (In this case crn and opc2 should be zero.) 170 * For AArch64, there is no 32/64 bit size distinction; 171 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 172 * and 4 bit CRn and CRm. The encoding patterns are chosen 173 * to be easy to convert to and from the KVM encodings, and also 174 * so that the hashtable can contain both AArch32 and AArch64 175 * registers (to allow for interprocessing where we might run 176 * 32 bit code on a 64 bit core). 177 */ 178 /* 179 * This bit is private to our hashtable cpreg; in KVM register 180 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 181 * in the upper bits of the 64 bit ID. 182 */ 183 #define CP_REG_AA64_SHIFT 28 184 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 185 186 /* 187 * To enable banking of coprocessor registers depending on ns-bit we 188 * add a bit to distinguish between secure and non-secure cpregs in the 189 * hashtable. 190 */ 191 #define CP_REG_AA32_NS_SHIFT 29 192 #define CP_REG_AA32_NS_MASK (1 << CP_REG_AA32_NS_SHIFT) 193 194 /* Distinguish 32-bit and 64-bit views of AArch32 system registers. */ 195 #define CP_REG_AA32_64BIT_SHIFT 15 196 #define CP_REG_AA32_64BIT_MASK (1 << CP_REG_AA32_64BIT_SHIFT) 197 198 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 199 (((ns) << CP_REG_AA32_NS_SHIFT) | \ 200 ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ 201 ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 202 203 #define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \ 204 (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ 205 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 206 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 207 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 208 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 209 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 210 211 /* 212 * Convert a full 64 bit KVM register ID to the truncated 32 bit 213 * version used as a key for the coprocessor register hashtable 214 */ 215 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 216 { 217 uint32_t cpregid = kvmid; 218 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 219 cpregid |= CP_REG_AA64_MASK; 220 } else { 221 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 222 cpregid |= CP_REG_AA32_64BIT_MASK; 223 } 224 225 /* 226 * KVM is always non-secure so add the NS flag on AArch32 register 227 * entries. 228 */ 229 cpregid |= CP_REG_AA32_NS_MASK; 230 } 231 return cpregid; 232 } 233 234 /* 235 * Convert a truncated 32 bit hashtable key into the full 236 * 64 bit KVM register ID. 237 */ 238 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 239 { 240 uint64_t kvmid; 241 242 if (cpregid & CP_REG_AA64_MASK) { 243 kvmid = cpregid & ~CP_REG_AA64_MASK; 244 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 245 } else { 246 kvmid = cpregid & ~CP_REG_AA32_64BIT_MASK; 247 if (cpregid & CP_REG_AA32_64BIT_MASK) { 248 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 249 } else { 250 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 251 } 252 } 253 return kvmid; 254 } 255 256 /* 257 * Valid values for ARMCPRegInfo state field, indicating which of 258 * the AArch32 and AArch64 execution states this register is visible in. 259 * If the reginfo doesn't explicitly specify then it is AArch32 only. 260 * If the reginfo is declared to be visible in both states then a second 261 * reginfo is synthesised for the AArch32 view of the AArch64 register, 262 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 263 * Note that we rely on the values of these enums as we iterate through 264 * the various states in some places. 265 */ 266 typedef enum { 267 ARM_CP_STATE_AA32 = 0, 268 ARM_CP_STATE_AA64 = 1, 269 ARM_CP_STATE_BOTH = 2, 270 } CPState; 271 272 /* 273 * ARM CP register secure state flags. These flags identify security state 274 * attributes for a given CP register entry. 275 * The existence of both or neither secure and non-secure flags indicates that 276 * the register has both a secure and non-secure hash entry. A single one of 277 * these flags causes the register to only be hashed for the specified 278 * security state. 279 * Although definitions may have any combination of the S/NS bits, each 280 * registered entry will only have one to identify whether the entry is secure 281 * or non-secure. 282 */ 283 typedef enum { 284 ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ 285 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 286 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 287 } CPSecureState; 288 289 /* 290 * Access rights: 291 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 292 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 293 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 294 * (ie any of the privileged modes in Secure state, or Monitor mode). 295 * If a register is accessible in one privilege level it's always accessible 296 * in higher privilege levels too. Since "Secure PL1" also follows this rule 297 * (ie anything visible in PL2 is visible in S-PL1, some things are only 298 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 299 * terminology a little and call this PL3. 300 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 301 * with the ELx exception levels. 302 * 303 * If access permissions for a register are more complex than can be 304 * described with these bits, then use a laxer set of restrictions, and 305 * do the more restrictive/complex check inside a helper function. 306 */ 307 typedef enum { 308 PL3_R = 0x80, 309 PL3_W = 0x40, 310 PL2_R = 0x20 | PL3_R, 311 PL2_W = 0x10 | PL3_W, 312 PL1_R = 0x08 | PL2_R, 313 PL1_W = 0x04 | PL2_W, 314 PL0_R = 0x02 | PL1_R, 315 PL0_W = 0x01 | PL1_W, 316 317 /* 318 * For user-mode some registers are accessible to EL0 via a kernel 319 * trap-and-emulate ABI. In this case we define the read permissions 320 * as actually being PL0_R. However some bits of any given register 321 * may still be masked. 322 */ 323 #ifdef CONFIG_USER_ONLY 324 PL0U_R = PL0_R, 325 #else 326 PL0U_R = PL1_R, 327 #endif 328 329 PL3_RW = PL3_R | PL3_W, 330 PL2_RW = PL2_R | PL2_W, 331 PL1_RW = PL1_R | PL1_W, 332 PL0_RW = PL0_R | PL0_W, 333 } CPAccessRights; 334 335 typedef enum CPAccessResult { 336 /* Access is permitted */ 337 CP_ACCESS_OK = 0, 338 339 /* 340 * Combined with one of the following, the low 2 bits indicate the 341 * target exception level. If 0, the exception is taken to the usual 342 * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). 343 */ 344 CP_ACCESS_EL_MASK = 3, 345 346 /* 347 * Access fails due to a configurable trap or enable which would 348 * result in a categorized exception syndrome giving information about 349 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 350 * 0xc or 0x18). These traps are always to a specified target EL, 351 * never to the usual target EL. 352 */ 353 CP_ACCESS_TRAP_BIT = (1 << 2), 354 CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP_BIT | 1, 355 CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP_BIT | 2, 356 CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3, 357 358 /* 359 * Access fails with UNDEFINED, i.e. an exception syndrome 0x0 360 * ("uncategorized"), which is what an undefined insn produces. 361 * Note that this is not a catch-all case -- the set of cases which may 362 * result in this failure is specifically defined by the architecture. 363 * This trap is always to the usual target EL, never directly to a 364 * specified target EL. 365 */ 366 CP_ACCESS_UNDEFINED = (2 << 2), 367 368 /* 369 * Access fails with EXLOCK, a GCS exception syndrome. 370 * These traps are always to the current execution EL, 371 * which is the same as the usual target EL because 372 * they cannot occur from EL0. 373 */ 374 CP_ACCESS_EXLOCK = (3 << 2), 375 } CPAccessResult; 376 377 /* Indexes into fgt_read[] */ 378 #define FGTREG_HFGRTR 0 379 #define FGTREG_HDFGRTR 1 380 /* Indexes into fgt_write[] */ 381 #define FGTREG_HFGWTR 0 382 #define FGTREG_HDFGWTR 1 383 /* Indexes into fgt_exec[] */ 384 #define FGTREG_HFGITR 0 385 386 FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) 387 FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) 388 FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) 389 FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) 390 FIELD(HFGRTR_EL2, APDAKEY, 4, 1) 391 FIELD(HFGRTR_EL2, APDBKEY, 5, 1) 392 FIELD(HFGRTR_EL2, APGAKEY, 6, 1) 393 FIELD(HFGRTR_EL2, APIAKEY, 7, 1) 394 FIELD(HFGRTR_EL2, APIBKEY, 8, 1) 395 FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) 396 FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) 397 FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) 398 FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) 399 FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) 400 FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) 401 FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) 402 FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) 403 FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) 404 FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) 405 FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) 406 FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) 407 FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) 408 FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) 409 FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) 410 FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) 411 FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) 412 FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) 413 FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) 414 FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) 415 FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) 416 FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) 417 FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) 418 FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) 419 FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) 420 FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) 421 FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) 422 FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) 423 FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) 424 FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) 425 FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) 426 FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) 427 FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) 428 FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) 429 FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) 430 FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) 431 FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) 432 FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) 433 FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) 434 FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) 435 FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) 436 FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) 437 /* 51: RES0 */ 438 FIELD(HFGRTR_EL2, NGCS_EL0, 52, 1) 439 FIELD(HFGRTR_EL2, NGCS_EL1, 53, 1) 440 FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) 441 FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) 442 FIELD(HFGRTR_EL2, NRCWMASK_EL1, 56, 1) 443 FIELD(HFGRTR_EL2, NPIRE0_EL1, 57, 1) 444 FIELD(HFGRTR_EL2, NPIR_EL1, 58, 1) 445 FIELD(HFGRTR_EL2, NPOR_EL0, 59, 1) 446 FIELD(HFGRTR_EL2, NPOR_EL1, 60, 1) 447 FIELD(HFGRTR_EL2, NS2POR_EL1, 61, 1) 448 FIELD(HFGRTR_EL2, NMAIR2_EL1, 62, 1) 449 FIELD(HFGRTR_EL2, NAMAIR2_EL1, 63, 1) 450 451 /* These match HFGRTR but bits for RO registers are RES0 */ 452 FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) 453 FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) 454 FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) 455 FIELD(HFGWTR_EL2, APDAKEY, 4, 1) 456 FIELD(HFGWTR_EL2, APDBKEY, 5, 1) 457 FIELD(HFGWTR_EL2, APGAKEY, 6, 1) 458 FIELD(HFGWTR_EL2, APIAKEY, 7, 1) 459 FIELD(HFGWTR_EL2, APIBKEY, 8, 1) 460 FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) 461 FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) 462 FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) 463 FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) 464 FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) 465 FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) 466 FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) 467 FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) 468 FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) 469 FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) 470 FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) 471 FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) 472 FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) 473 FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) 474 FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) 475 FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) 476 FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) 477 FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) 478 FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) 479 FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) 480 FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) 481 FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) 482 FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) 483 FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) 484 FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) 485 FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) 486 FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) 487 FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) 488 FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) 489 FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) 490 FIELD(HFGWTR_EL2, NGCS_EL0, 52, 1) 491 FIELD(HFGWTR_EL2, NGCS_EL1, 53, 1) 492 FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) 493 FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) 494 FIELD(HFGWTR_EL2, NRCWMASK_EL1, 56, 1) 495 FIELD(HFGWTR_EL2, NPIRE0_EL1, 57, 1) 496 FIELD(HFGWTR_EL2, NPIR_EL1, 58, 1) 497 FIELD(HFGWTR_EL2, NPOR_EL0, 59, 1) 498 FIELD(HFGWTR_EL2, NPOR_EL1, 60, 1) 499 FIELD(HFGWTR_EL2, NS2POR_EL1, 61, 1) 500 FIELD(HFGWTR_EL2, NMAIR2_EL1, 62, 1) 501 FIELD(HFGWTR_EL2, NAMAIR2_EL1, 63, 1) 502 503 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) 504 FIELD(HFGITR_EL2, ICIALLU, 1, 1) 505 FIELD(HFGITR_EL2, ICIVAU, 2, 1) 506 FIELD(HFGITR_EL2, DCIVAC, 3, 1) 507 FIELD(HFGITR_EL2, DCISW, 4, 1) 508 FIELD(HFGITR_EL2, DCCSW, 5, 1) 509 FIELD(HFGITR_EL2, DCCISW, 6, 1) 510 FIELD(HFGITR_EL2, DCCVAU, 7, 1) 511 FIELD(HFGITR_EL2, DCCVAP, 8, 1) 512 FIELD(HFGITR_EL2, DCCVADP, 9, 1) 513 FIELD(HFGITR_EL2, DCCIVAC, 10, 1) 514 FIELD(HFGITR_EL2, DCZVA, 11, 1) 515 FIELD(HFGITR_EL2, ATS1E1R, 12, 1) 516 FIELD(HFGITR_EL2, ATS1E1W, 13, 1) 517 FIELD(HFGITR_EL2, ATS1E0R, 14, 1) 518 FIELD(HFGITR_EL2, ATS1E0W, 15, 1) 519 FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) 520 FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) 521 FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) 522 FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) 523 FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) 524 FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) 525 FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) 526 FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) 527 FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) 528 FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) 529 FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) 530 FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) 531 FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) 532 FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) 533 FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) 534 FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) 535 FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) 536 FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) 537 FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) 538 FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) 539 FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) 540 FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) 541 FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) 542 FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) 543 FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) 544 FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) 545 FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) 546 FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) 547 FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) 548 FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) 549 FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) 550 FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) 551 FIELD(HFGITR_EL2, CFPRCTX, 48, 1) 552 FIELD(HFGITR_EL2, DVPRCTX, 49, 1) 553 FIELD(HFGITR_EL2, CPPRCTX, 50, 1) 554 FIELD(HFGITR_EL2, ERET, 51, 1) 555 FIELD(HFGITR_EL2, SVC_EL0, 52, 1) 556 FIELD(HFGITR_EL2, SVC_EL1, 53, 1) 557 FIELD(HFGITR_EL2, DCCVAC, 54, 1) 558 FIELD(HFGITR_EL2, NBRBINJ, 55, 1) 559 FIELD(HFGITR_EL2, NBRBIALL, 56, 1) 560 FIELD(HFGITR_EL2, NGCSPUSHM_EL1, 57, 1) 561 FIELD(HFGITR_EL2, NGCSSTR_EL1, 58, 1) 562 FIELD(HFGITR_EL2, NGCSEPP, 59, 1) 563 FIELD(HFGITR_EL2, COSPRCTX, 60, 1) 564 FIELD(HFGITR_EL2, ATS1E1A, 62, 1) 565 566 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) 567 FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) 568 FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) 569 FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) 570 FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) 571 FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) 572 FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) 573 FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) 574 /* 8: RES0: OSLAR_EL1 is WO */ 575 FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) 576 FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) 577 FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) 578 FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) 579 FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) 580 FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) 581 FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) 582 FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) 583 FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) 584 FIELD(HDFGRTR_EL2, PMOVS, 18, 1) 585 FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) 586 /* 20: RES0: PMSWINC_EL0 is WO */ 587 /* 21: RES0: PMCR_EL0 is WO */ 588 FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) 589 FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) 590 FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) 591 FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) 592 FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) 593 FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) 594 FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) 595 FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) 596 FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) 597 FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) 598 FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) 599 FIELD(HDFGRTR_EL2, TRC, 33, 1) 600 FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) 601 FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) 602 FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) 603 FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) 604 /* 38, 39: RES0 */ 605 FIELD(HDFGRTR_EL2, TRCID, 40, 1) 606 FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) 607 /* 42: RES0: TRCOSLAR is WO */ 608 FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) 609 FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) 610 FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) 611 FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) 612 FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) 613 FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) 614 /* 49: RES0: TRFCR_EL1 is WO */ 615 FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) 616 FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) 617 FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) 618 FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) 619 FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) 620 FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) 621 FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) 622 FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) 623 FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) 624 FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) 625 FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) 626 FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) 627 FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) 628 FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) 629 630 /* 631 * These match HDFGRTR_EL2, but bits for RO registers are RES0. 632 * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. 633 */ 634 FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) 635 FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) 636 FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) 637 FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) 638 FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) 639 FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) 640 FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) 641 FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) 642 FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) 643 FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) 644 FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) 645 FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) 646 FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) 647 FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) 648 FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) 649 FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) 650 FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) 651 FIELD(HDFGWTR_EL2, PMOVS, 18, 1) 652 FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) 653 FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) 654 FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) 655 FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) 656 FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) 657 FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) 658 FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) 659 FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) 660 FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) 661 FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) 662 FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) 663 FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) 664 FIELD(HDFGWTR_EL2, TRC, 33, 1) 665 FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) 666 FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) 667 FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) 668 FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) 669 FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) 670 FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) 671 FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) 672 FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) 673 FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) 674 FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) 675 FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) 676 FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) 677 FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) 678 FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) 679 FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) 680 FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) 681 FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) 682 FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) 683 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) 684 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) 685 686 FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */ 687 /* Which fine-grained trap bit register to check, if any */ 688 FIELD(FGT, TYPE, 10, 3) 689 FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ 690 FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ 691 FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ 692 693 /* 694 * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt 695 * fields. We assume for brevity's sake that there are no duplicated 696 * bit names across the various FGT registers. 697 */ 698 #define DO_BIT(REG, BITNAME) \ 699 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT 700 701 /* Some bits have reversed sense, so 0 means trap and 1 means not */ 702 #define DO_REV_BIT(REG, BITNAME) \ 703 FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT 704 705 /* 706 * The FGT bits for TLBI maintenance instructions accessible at EL1 always 707 * affect the "normal" TLBI insns; they affect the corresponding TLBI insns 708 * with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g. 709 * FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use 710 * for the nXS qualified insn. 711 */ 712 #define DO_TLBINXS_BIT(REG, BITNAME) \ 713 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \ 714 FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK 715 716 typedef enum FGTBit { 717 /* 718 * These bits tell us which register arrays to use: 719 * if FGT_R is set then reads are checked against fgt_read[]; 720 * if FGT_W is set then writes are checked against fgt_write[]; 721 * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. 722 * 723 * For almost all bits in the R/W register pairs, the bit exists in 724 * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register 725 * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa 726 * for a WO register. There are unfortunately a couple of exceptions 727 * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but 728 * the FGT system only allows trapping of writes, not reads. 729 * 730 * Note that we arrange these bits so that a 0 FGTBit means "no trap". 731 */ 732 FGT_R = 1 << R_FGT_TYPE_SHIFT, 733 FGT_W = 2 << R_FGT_TYPE_SHIFT, 734 FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, 735 FGT_RW = FGT_R | FGT_W, 736 /* Bit to identify whether trap bit is reversed sense */ 737 FGT_REV = R_FGT_REV_MASK, 738 739 /* 740 * If a bit exists in HFGRTR/HDFGRTR then either the register being 741 * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either 742 * want to trap for both reads and writes or else it's harmless to mark 743 * it as trap-on-writes. 744 * If a bit exists only in HFGWTR/HDFGWTR then either the register being 745 * trapped is WO, or else it is one of the two oddball special cases 746 * which are RW but have only a write trap. We mark these as only 747 * FGT_W so we get the right behaviour for those special cases. 748 * (If a bit was added in future that provided only a read trap for an 749 * RW register we'd need to do something special to get the FGT_R bit 750 * only. But this seems unlikely to happen.) 751 * 752 * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if 753 * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. 754 */ 755 FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), 756 FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), 757 FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), 758 FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), 759 FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), 760 761 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ 762 DO_BIT(HFGRTR, AFSR0_EL1), 763 DO_BIT(HFGRTR, AFSR1_EL1), 764 DO_BIT(HFGRTR, AIDR_EL1), 765 DO_BIT(HFGRTR, AMAIR_EL1), 766 DO_BIT(HFGRTR, APDAKEY), 767 DO_BIT(HFGRTR, APDBKEY), 768 DO_BIT(HFGRTR, APGAKEY), 769 DO_BIT(HFGRTR, APIAKEY), 770 DO_BIT(HFGRTR, APIBKEY), 771 DO_BIT(HFGRTR, CCSIDR_EL1), 772 DO_BIT(HFGRTR, CLIDR_EL1), 773 DO_BIT(HFGRTR, CONTEXTIDR_EL1), 774 DO_BIT(HFGRTR, CPACR_EL1), 775 DO_BIT(HFGRTR, CSSELR_EL1), 776 DO_BIT(HFGRTR, CTR_EL0), 777 DO_BIT(HFGRTR, DCZID_EL0), 778 DO_BIT(HFGRTR, ESR_EL1), 779 DO_BIT(HFGRTR, FAR_EL1), 780 DO_BIT(HFGRTR, ISR_EL1), 781 DO_BIT(HFGRTR, LORC_EL1), 782 DO_BIT(HFGRTR, LOREA_EL1), 783 DO_BIT(HFGRTR, LORID_EL1), 784 DO_BIT(HFGRTR, LORN_EL1), 785 DO_BIT(HFGRTR, LORSA_EL1), 786 DO_BIT(HFGRTR, MAIR_EL1), 787 DO_BIT(HFGRTR, MIDR_EL1), 788 DO_BIT(HFGRTR, MPIDR_EL1), 789 DO_BIT(HFGRTR, PAR_EL1), 790 DO_BIT(HFGRTR, REVIDR_EL1), 791 DO_BIT(HFGRTR, SCTLR_EL1), 792 DO_BIT(HFGRTR, SCXTNUM_EL1), 793 DO_BIT(HFGRTR, SCXTNUM_EL0), 794 DO_BIT(HFGRTR, TCR_EL1), 795 DO_BIT(HFGRTR, TPIDR_EL1), 796 DO_BIT(HFGRTR, TPIDRRO_EL0), 797 DO_BIT(HFGRTR, TPIDR_EL0), 798 DO_BIT(HFGRTR, TTBR0_EL1), 799 DO_BIT(HFGRTR, TTBR1_EL1), 800 DO_BIT(HFGRTR, VBAR_EL1), 801 DO_BIT(HFGRTR, ICC_IGRPENN_EL1), 802 DO_BIT(HFGRTR, ERRIDR_EL1), 803 DO_REV_BIT(HFGRTR, NGCS_EL0), 804 DO_REV_BIT(HFGRTR, NGCS_EL1), 805 DO_REV_BIT(HFGRTR, NSMPRI_EL1), 806 DO_REV_BIT(HFGRTR, NTPIDR2_EL0), 807 DO_REV_BIT(HFGRTR, NPIRE0_EL1), 808 DO_REV_BIT(HFGRTR, NPIR_EL1), 809 DO_REV_BIT(HFGRTR, NMAIR2_EL1), 810 DO_REV_BIT(HFGRTR, NAMAIR2_EL1), 811 812 /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ 813 DO_BIT(HDFGRTR, DBGBCRN_EL1), 814 DO_BIT(HDFGRTR, DBGBVRN_EL1), 815 DO_BIT(HDFGRTR, DBGWCRN_EL1), 816 DO_BIT(HDFGRTR, DBGWVRN_EL1), 817 DO_BIT(HDFGRTR, MDSCR_EL1), 818 DO_BIT(HDFGRTR, DBGCLAIM), 819 DO_BIT(HDFGWTR, OSLAR_EL1), 820 DO_BIT(HDFGRTR, OSLSR_EL1), 821 DO_BIT(HDFGRTR, OSECCR_EL1), 822 DO_BIT(HDFGRTR, OSDLR_EL1), 823 DO_BIT(HDFGRTR, PMEVCNTRN_EL0), 824 DO_BIT(HDFGRTR, PMEVTYPERN_EL0), 825 DO_BIT(HDFGRTR, PMCCFILTR_EL0), 826 DO_BIT(HDFGRTR, PMCCNTR_EL0), 827 DO_BIT(HDFGRTR, PMCNTEN), 828 DO_BIT(HDFGRTR, PMINTEN), 829 DO_BIT(HDFGRTR, PMOVS), 830 DO_BIT(HDFGRTR, PMSELR_EL0), 831 DO_BIT(HDFGWTR, PMSWINC_EL0), 832 DO_BIT(HDFGWTR, PMCR_EL0), 833 DO_BIT(HDFGRTR, PMMIR_EL1), 834 DO_BIT(HDFGRTR, PMCEIDN_EL0), 835 836 /* Trap bits in HFGITR_EL2, starting from bit 0 */ 837 DO_BIT(HFGITR, ICIALLUIS), 838 DO_BIT(HFGITR, ICIALLU), 839 DO_BIT(HFGITR, ICIVAU), 840 DO_BIT(HFGITR, DCIVAC), 841 DO_BIT(HFGITR, DCISW), 842 DO_BIT(HFGITR, DCCSW), 843 DO_BIT(HFGITR, DCCISW), 844 DO_BIT(HFGITR, DCCVAU), 845 DO_BIT(HFGITR, DCCVAP), 846 DO_BIT(HFGITR, DCCVADP), 847 DO_BIT(HFGITR, DCCIVAC), 848 DO_BIT(HFGITR, DCZVA), 849 DO_BIT(HFGITR, ATS1E1R), 850 DO_BIT(HFGITR, ATS1E1W), 851 DO_BIT(HFGITR, ATS1E0R), 852 DO_BIT(HFGITR, ATS1E0W), 853 DO_BIT(HFGITR, ATS1E1RP), 854 DO_BIT(HFGITR, ATS1E1WP), 855 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS), 856 DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS), 857 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS), 858 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS), 859 DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS), 860 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS), 861 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS), 862 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS), 863 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS), 864 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS), 865 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS), 866 DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS), 867 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS), 868 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS), 869 DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS), 870 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS), 871 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS), 872 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS), 873 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS), 874 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS), 875 DO_TLBINXS_BIT(HFGITR, TLBIRVAE1), 876 DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1), 877 DO_TLBINXS_BIT(HFGITR, TLBIRVALE1), 878 DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1), 879 DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1), 880 DO_TLBINXS_BIT(HFGITR, TLBIVAE1), 881 DO_TLBINXS_BIT(HFGITR, TLBIASIDE1), 882 DO_TLBINXS_BIT(HFGITR, TLBIVAAE1), 883 DO_TLBINXS_BIT(HFGITR, TLBIVALE1), 884 DO_TLBINXS_BIT(HFGITR, TLBIVAALE1), 885 DO_BIT(HFGITR, CFPRCTX), 886 DO_BIT(HFGITR, DVPRCTX), 887 DO_BIT(HFGITR, CPPRCTX), 888 DO_BIT(HFGITR, DCCVAC), 889 DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), 890 DO_REV_BIT(HFGITR, NGCSEPP), 891 DO_BIT(HFGITR, ATS1E1A), 892 } FGTBit; 893 894 #undef DO_BIT 895 #undef DO_REV_BIT 896 897 typedef struct ARMCPRegInfo ARMCPRegInfo; 898 899 /* 900 * Access functions for coprocessor registers. These cannot fail and 901 * may not raise exceptions. 902 */ 903 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *ri); 904 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *ri, 905 uint64_t value); 906 /* Access permission check functions for coprocessor registers. */ 907 typedef CPAccessResult CPAccessFn(CPUARMState *env, 908 const ARMCPRegInfo *ri, 909 bool isread); 910 /* Hook function for register reset */ 911 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *ri); 912 913 #define CP_ANY 0xff 914 915 /* Flags in the high bits of nv2_redirect_offset */ 916 #define NV2_REDIR_NV1 0x4000 /* Only redirect when HCR_EL2.NV1 == 1 */ 917 #define NV2_REDIR_NO_NV1 0x8000 /* Only redirect when HCR_EL2.NV1 == 0 */ 918 #define NV2_REDIR_FLAG_MASK 0xc000 919 920 /* Definition of an ARM coprocessor register */ 921 struct ARMCPRegInfo { 922 /* Name of register (useful mainly for debugging, need not be unique) */ 923 const char *name; 924 /* 925 * Location of register: coprocessor number and (crn,crm,opc1,opc2) 926 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 927 * 'wildcard' field -- any value of that field in the MRC/MCR insn 928 * will be decoded to this register. The register read and write 929 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 930 * used by the program, so it is possible to register a wildcard and 931 * then behave differently on read/write if necessary. 932 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 933 * must both be zero. 934 * For AArch64-visible registers, opc0 is also used. 935 * Since there are no "coprocessors" in AArch64, cp is purely used as a 936 * way to distinguish (for KVM's benefit) guest-visible system registers 937 * from demuxed ones provided to preserve the "no side effects on 938 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 939 * visible (to match KVM's encoding); cp==0 will be converted to 940 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 941 */ 942 uint8_t cp; 943 uint8_t crn; 944 uint8_t crm; 945 uint8_t opc0; 946 uint8_t opc1; 947 uint8_t opc2; 948 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 949 CPState state; 950 /* Register type: ARM_CP_* bits/values */ 951 int type; 952 /* Access rights: PL*_[RW] */ 953 CPAccessRights access; 954 /* Security state: ARM_CP_SECSTATE_* bits/values */ 955 CPSecureState secure; 956 /* 957 * Which fine-grained trap register bit to check, if any. This 958 * value encodes both the trap register and bit within it. 959 */ 960 FGTBit fgt; 961 962 /* 963 * Offset from VNCR_EL2 when FEAT_NV2 redirects access to memory; 964 * may include an NV2_REDIR_* flag. 965 */ 966 uint32_t nv2_redirect_offset; 967 968 /* 969 * With VHE, with E2H, at EL2, access to this EL0/EL1 reg redirects 970 * to the EL2 reg with the specified key. 971 */ 972 uint32_t vhe_redir_to_el2; 973 974 /* 975 * For VHE. Before registration, this field holds the key for an 976 * EL02/EL12 reg to be created to point back to this EL0/EL1 reg. 977 * After registration, this field is set only on the EL02/EL12 reg 978 * and points back to the EL02/EL12 reg for redirection with E2H. 979 */ 980 uint32_t vhe_redir_to_el01; 981 982 /* 983 * Value of this register, if it is ARM_CP_CONST. Otherwise, if 984 * fieldoffset is non-zero, the reset value of the register. 985 */ 986 uint64_t resetvalue; 987 /* 988 * Offset of the field in CPUARMState for this register. 989 * This is not needed if either: 990 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 991 * 2. both readfn and writefn are specified 992 */ 993 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 994 995 /* 996 * Offsets of the secure and non-secure fields in CPUARMState for the 997 * register if it is banked. These fields are only used during the static 998 * registration of a register. During hashing the bank associated 999 * with a given security state is copied to fieldoffset which is used from 1000 * there on out. 1001 * 1002 * It is expected that register definitions use either fieldoffset or 1003 * bank_fieldoffsets in the definition but not both. It is also expected 1004 * that both bank offsets are set when defining a banked register. This 1005 * use indicates that a register is banked. 1006 */ 1007 ptrdiff_t bank_fieldoffsets[2]; 1008 1009 /* 1010 * Function for making any access checks for this register in addition to 1011 * those specified by the 'access' permissions bits. If NULL, no extra 1012 * checks required. The access check is performed at runtime, not at 1013 * translate time. 1014 */ 1015 CPAccessFn *accessfn; 1016 /* 1017 * Function for handling reads of this register. If NULL, then reads 1018 * will be done by loading from the offset into CPUARMState specified 1019 * by fieldoffset. 1020 */ 1021 CPReadFn *readfn; 1022 /* 1023 * Function for handling writes of this register. If NULL, then writes 1024 * will be done by writing to the offset into CPUARMState specified 1025 * by fieldoffset. 1026 */ 1027 CPWriteFn *writefn; 1028 /* 1029 * Function for doing a "raw" read; used when we need to copy 1030 * coprocessor state to the kernel for KVM or out for 1031 * migration. This only needs to be provided if there is also a 1032 * readfn and it has side effects (for instance clear-on-read bits). 1033 */ 1034 CPReadFn *raw_readfn; 1035 /* 1036 * Function for doing a "raw" write; used when we need to copy KVM 1037 * kernel coprocessor state into userspace, or for inbound 1038 * migration. This only needs to be provided if there is also a 1039 * writefn and it masks out "unwritable" bits or has write-one-to-clear 1040 * or similar behaviour. 1041 */ 1042 CPWriteFn *raw_writefn; 1043 /* 1044 * Function for resetting the register. If NULL, then reset will be done 1045 * by writing resetvalue to the field specified in fieldoffset. If 1046 * fieldoffset is 0 then no reset will be done. 1047 */ 1048 CPResetFn *resetfn; 1049 }; 1050 1051 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs); 1052 void define_arm_cp_regs_len(ARMCPU *cpu, const ARMCPRegInfo *regs, size_t len); 1053 1054 #define define_arm_cp_regs(CPU, REGS) \ 1055 do { \ 1056 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 1057 define_arm_cp_regs_len(CPU, REGS, ARRAY_SIZE(REGS)); \ 1058 } while (0) 1059 1060 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 1061 1062 /* 1063 * Definition of an ARM co-processor register as viewed from 1064 * userspace. This is used for presenting sanitised versions of 1065 * registers to userspace when emulating the Linux AArch64 CPU 1066 * ID/feature ABI (advertised as HWCAP_CPUID). 1067 */ 1068 typedef struct ARMCPRegUserSpaceInfo { 1069 /* Name of register */ 1070 const char *name; 1071 1072 /* Is the name actually a glob pattern */ 1073 bool is_glob; 1074 1075 /* Only some bits are exported to user space */ 1076 uint64_t exported_bits; 1077 1078 /* Fixed bits are applied after the mask */ 1079 uint64_t fixed_bits; 1080 } ARMCPRegUserSpaceInfo; 1081 1082 void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, 1083 const ARMCPRegUserSpaceInfo *mods, 1084 size_t mods_len); 1085 1086 #define modify_arm_cp_regs(REGS, MODS) \ 1087 do { \ 1088 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 1089 QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ 1090 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ 1091 MODS, ARRAY_SIZE(MODS)); \ 1092 } while (0) 1093 1094 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1095 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1096 uint64_t value); 1097 /* CPReadFn that can be used for read-as-zero behaviour */ 1098 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1099 1100 /* CPReadFn that just reads the value from ri->fieldoffset */ 1101 uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri); 1102 1103 /* CPWriteFn that just writes the value to ri->fieldoffset */ 1104 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); 1105 1106 /* 1107 * CPResetFn that does nothing, for use if no reset is required even 1108 * if fieldoffset is non zero. 1109 */ 1110 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *ri); 1111 1112 /* 1113 * Return MO_32 if the field in CPUARMState is uint32_t or 1114 * MO_64 if the field in CPUARMState is uint64_t. 1115 */ 1116 static inline MemOp cpreg_field_type(const ARMCPRegInfo *ri) 1117 { 1118 return (ri->state == ARM_CP_STATE_AA64 || (ri->type & ARM_CP_64BIT) 1119 ? MO_64 : MO_32); 1120 } 1121 1122 static inline bool cp_access_ok(int current_el, 1123 const ARMCPRegInfo *ri, int isread) 1124 { 1125 return (ri->access >> ((current_el * 2) + isread)) & 1; 1126 } 1127 1128 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1129 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1130 1131 /* 1132 * Return true if the cp register encoding is in the "feature ID space" as 1133 * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC 1134 * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED). 1135 */ 1136 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, 1137 uint8_t opc2, 1138 uint8_t crn, uint8_t crm) 1139 { 1140 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && 1141 crn == 0 && crm < 8; 1142 } 1143 1144 /* 1145 * As arm_cpreg_encoding_in_idspace(), but take the encoding from an 1146 * ARMCPRegInfo. 1147 */ 1148 static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri) 1149 { 1150 return ri->state == ARM_CP_STATE_AA64 && 1151 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, 1152 ri->crn, ri->crm); 1153 } 1154 1155 #ifdef CONFIG_USER_ONLY 1156 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } 1157 #else 1158 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); 1159 #endif 1160 1161 CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); 1162 1163 /** 1164 * arm_cpreg_trap_in_nv: Return true if cpreg traps in nested virtualization 1165 * 1166 * Return true if this cpreg is one which should be trapped to EL2 if 1167 * it is executed at EL1 when nested virtualization is enabled via HCR_EL2.NV. 1168 */ 1169 static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri) 1170 { 1171 /* 1172 * The Arm ARM defines the registers to be trapped in terms of 1173 * their names (I_TZTZL). However the underlying principle is "if 1174 * it would UNDEF at EL1 but work at EL2 then it should trap", and 1175 * the way the encoding of sysregs and system instructions is done 1176 * means that the right set of registers is exactly those where 1177 * the opc1 field is 4 or 5. (You can see this also in the assert 1178 * we do that the opc1 field and the permissions mask line up in 1179 * define_one_arm_cp_reg().) 1180 * Checking the opc1 field is easier for us and avoids the problem 1181 * that we do not consistently use the right architectural names 1182 * for all sysregs, since we treat the name field as largely for debug. 1183 * 1184 * However we do this check, it is going to be at least potentially 1185 * fragile to future new sysregs, but this seems the least likely 1186 * to break. 1187 * 1188 * In particular, note that the FEAT_MEC sysregs and instructions 1189 * are exceptions to this trapping rule, so they are marked as 1190 * ARM_CP_NV_NO_TRAP to indicate that they should not be trapped 1191 * to EL2. (They are an exception because the FEAT_MEC sysregs UNDEF 1192 * unless in Realm, and Realm is not expected to be virtualized.) 1193 */ 1194 1195 if (ri->type & ARM_CP_NV_NO_TRAP) { 1196 return false; 1197 } 1198 1199 return ri->opc1 == 4 || ri->opc1 == 5; 1200 } 1201 1202 /* Macros for accessing a specified CP register bank */ 1203 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 1204 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 1205 1206 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 1207 do { \ 1208 if (_secure) { \ 1209 (_env)->cp15._regname##_s = (_val); \ 1210 } else { \ 1211 (_env)->cp15._regname##_ns = (_val); \ 1212 } \ 1213 } while (0) 1214 1215 /* 1216 * Macros for automatically accessing a specific CP register bank depending on 1217 * the current secure state of the system. These macros are not intended for 1218 * supporting instruction translation reads/writes as these are dependent 1219 * solely on the SCR.NS bit and not the mode. 1220 */ 1221 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 1222 A32_BANKED_REG_GET((_env), _regname, \ 1223 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 1224 1225 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 1226 A32_BANKED_REG_SET((_env), _regname, \ 1227 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 1228 (_val)) 1229 1230 #endif /* TARGET_ARM_CPREGS_H */ 1231